blob: 09bf4e48ff63382154ef557c57259a23c139a95b [file] [log] [blame]
Heiko Schocherd7f77fb2006-06-19 11:02:41 +02001/*
2 * ppmc7xx.h
3 * ---------
Wolfgang Denkba940932006-07-19 13:50:38 +02004 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +02005 * Wind River PPMC 7xx/74xx board configuration file.
Wolfgang Denkba940932006-07-19 13:50:38 +02006 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +02007 * By Richard Danter (richard.danter@windriver.com)
8 * Copyright (C) 2005 Wind River Systems
9 */
10
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_PPMC7XX
16
17
18/*===================================================================
Wolfgang Denkba940932006-07-19 13:50:38 +020019 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020020 * User configurable settings - Modify to your preference
Wolfgang Denkba940932006-07-19 13:50:38 +020021 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020022 *===================================================================
23 */
24
25/*
26 * Debug
Wolfgang Denkba940932006-07-19 13:50:38 +020027 *
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +020028 * DEBUG - Define this is you want extra debug info
29 * GTREGREAD - Required to build with debug
30 * do_bdinfo - Required to build with debug
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020031 */
32
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +020033#ifdef DEBUG
34#define GTREGREAD(x) 0xFFFFFFFF
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020035#define do_bdinfo(a,b,c,d)
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +020036#endif
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020037
38/*
39 * CPU type
Wolfgang Denkba940932006-07-19 13:50:38 +020040 *
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +020041 * CONFIG_7xx - We have a 750 or 755 CPU
42 * CONFIG_74xx - We have a 7400 CPU
43 * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
44 * CONFIG_BUS_CLK - System bus clock in Hz
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020045 */
46
47#define CONFIG_7xx
48#undef CONFIG_74xx
49#undef CONFIG_ALTIVEC
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +020050#define CONFIG_BUS_CLK 66000000
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020051
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020052#define CONFIG_SYS_TEXT_BASE 0xFFF00000
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020053
54/*
55 * Monitor configuration
Wolfgang Denkba940932006-07-19 13:50:38 +020056 *
Jon Loeligeraa2d2c22007-07-04 22:33:17 -050057 * List of command sets to include in shell
Wolfgang Denkba940932006-07-19 13:50:38 +020058 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020059 * The following command sets have been tested and known to work:
Wolfgang Denkba940932006-07-19 13:50:38 +020060 *
Jon Loeligeraa2d2c22007-07-04 22:33:17 -050061 * CMD_CACHE - Cache control commands
62 * CMD_MEMORY - Memory display, change and test commands
63 * CMD_FLASH - Erase and program flash
64 * CMD_ENV - Environment commands
65 * CMD_RUN - Run commands stored in env vars
66 * CMD_ELF - Load ELF files
67 * CMD_NET - Networking/file download commands
68 * CMD_PIN - ICMP Echo Request command
69 * CMD_PCI - PCI Bus scanning command
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020070 */
71
Jon Loeligeraa2d2c22007-07-04 22:33:17 -050072/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -050073 * BOOTP options
74 */
75#define CONFIG_BOOTP_BOOTFILESIZE
76#define CONFIG_BOOTP_BOOTPATH
77#define CONFIG_BOOTP_GATEWAY
78#define CONFIG_BOOTP_HOSTNAME
79
80
81/*
Jon Loeligeraa2d2c22007-07-04 22:33:17 -050082 * Command line configuration.
83 */
84#include <config_cmd_default.h>
85
86#define CONFIG_CMD_FLASH
Mike Frysinger78dcaf42009-01-28 19:08:14 -050087#define CONFIG_CMD_SAVEENV
Jon Loeligeraa2d2c22007-07-04 22:33:17 -050088#define CONFIG_CMD_RUN
89#define CONFIG_CMD_ELF
90#define CONFIG_CMD_NET
91#define CONFIG_CMD_PING
92#define CONFIG_CMD_PCI
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020093
Jon Loeligeraa2d2c22007-07-04 22:33:17 -050094#undef CONFIG_CMD_KGDB
95
Heiko Schocherd7f77fb2006-06-19 11:02:41 +020096
97/*
98 * Serial configuration
99 *
100 * CONFIG_CONS_INDEX - Serial console port number (COM1)
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200101 * CONFIG_BAUDRATE - Serial speed
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200102 */
103
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200104#define CONFIG_CONS_INDEX 1
105#define CONFIG_BAUDRATE 9600
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200106
107
108/*
109 * PCI config
Wolfgang Denkba940932006-07-19 13:50:38 +0200110 *
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200111 * CONFIG_PCI - Enable PCI bus
112 * CONFIG_PCI_PNP - Enable Plug & Play support
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200113 * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
114 */
115
116#define CONFIG_PCI
117#define CONFIG_PCI_PNP
118#undef CONFIG_PCI_SCAN_SHOW
119
120
121/*
122 * Network config
Wolfgang Denkba940932006-07-19 13:50:38 +0200123 *
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200124 * CONFIG_NET_MULTI - Support for multiple network interfaces
125 * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
126 * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200127 */
128
129#define CONFIG_NET_MULTI
130#define CONFIG_EEPRO100
131#define CONFIG_EEPRO100_SROM_WRITE
132
133
134/*
135 * Enable extra init functions
Wolfgang Denkba940932006-07-19 13:50:38 +0200136 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200137 * CONFIG_MISC_INIT_F - Call pre-relocation init functions
138 * CONFIG_MISC_INIT_R - Call post relocation init functions
139 */
140
141#undef CONFIG_MISC_INIT_F
Wolfgang Denkba940932006-07-19 13:50:38 +0200142#define CONFIG_MISC_INIT_R
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200143
144
145/*
146 * Boot config
Wolfgang Denkba940932006-07-19 13:50:38 +0200147 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200148 * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200149 * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200150 */
151
152#define CONFIG_BOOTCOMMAND \
153 "bootp;" \
154 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
155 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
156 "bootm"
157#define CONFIG_BOOTDELAY 5
158
159
160/*===================================================================
Wolfgang Denkba940932006-07-19 13:50:38 +0200161 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200162 * Board configuration settings - You should not need to modify these
Wolfgang Denkba940932006-07-19 13:50:38 +0200163 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200164 *===================================================================
165 */
166
167
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200168/*
169 * Memory map
Wolfgang Denkba940932006-07-19 13:50:38 +0200170 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200171 * This board runs in a standard CHRP (Map-B) configuration.
Wolfgang Denkba940932006-07-19 13:50:38 +0200172 *
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200173 * Type Start End Size Width Chip Sel
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200174 * ----------- ----------- ----------- ------- ------- --------
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200175 * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
176 * User LED's 0x78000000 RCS3
177 * UART 0x7C000000 RCS2
178 * Mailbox 0xFF000000 RCS1
179 * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
Wolfgang Denkba940932006-07-19 13:50:38 +0200180 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200181 * Flash sectors are laid out as follows.
Wolfgang Denkba940932006-07-19 13:50:38 +0200182 *
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200183 * Sector Start End Size Comments
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200184 * ------- ----------- ----------- ------- -----------
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200185 * 0 0xFFC00000 0xFFC3FFFF 256KB
186 * 1 0xFFC40000 0xFFC7FFFF 256KB
187 * 2 0xFFC80000 0xFFCBFFFF 256KB
188 * 3 0xFFCC0000 0xFFCFFFFF 256KB
189 * 4 0xFFD00000 0xFFD3FFFF 256KB
190 * 5 0xFFD40000 0xFFD7FFFF 256KB
191 * 6 0xFFD80000 0xFFDBFFFF 256KB
192 * 7 0xFFDC0000 0xFFDFFFFF 256KB
193 * 8 0xFFE00000 0xFFE3FFFF 256KB
194 * 9 0xFFE40000 0xFFE7FFFF 256KB
195 * 10 0xFFE80000 0xFFEBFFFF 256KB
196 * 11 0xFFEC0000 0xFFEFFFFF 256KB
197 * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
198 * 13 0xFFF40000 0xFFF7FFFF 256KB
199 * 14 0xFFF80000 0xFFFBFFFF 256KB
200 * 15 0xFFFC0000 0xFFFDFFFF 128KB
201 * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
202 * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
203 * 18 0xFFFF0000 0xFFFFFFFF 64KB
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200204 */
205
206
207/*
208 * SDRAM config - see memory map details above.
Wolfgang Denkba940932006-07-19 13:50:38 +0200209 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210 * CONFIG_SYS_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
211 * CONFIG_SYS_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200212 */
213
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_SDRAM_BASE 0x00000000
215#define CONFIG_SYS_SDRAM_SIZE 0x04000000
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200216
217
Wolfgang Denkba940932006-07-19 13:50:38 +0200218/*
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200219 * Flash config - see memory map details above.
Wolfgang Denkba940932006-07-19 13:50:38 +0200220 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221 * CONFIG_SYS_FLASH_BASE - Start address of flash memory
222 * CONFIG_SYS_FLASH_SIZE - Total size of contiguous flash mem
223 * CONFIG_SYS_FLASH_ERASE_TOUT - Erase timeout in ms
224 * CONFIG_SYS_FLASH_WRITE_TOUT - Write timeout in ms
225 * CONFIG_SYS_MAX_FLASH_BANKS - Number of banks of flash on board
226 * CONFIG_SYS_MAX_FLASH_SECT - Number of sectors in a bank
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200227 */
228
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_BASE 0xFFC00000
230#define CONFIG_SYS_FLASH_SIZE 0x00400000
231#define CONFIG_SYS_FLASH_ERASE_TOUT 250000
232#define CONFIG_SYS_FLASH_WRITE_TOUT 5000
233#define CONFIG_SYS_MAX_FLASH_BANKS 1
234#define CONFIG_SYS_MAX_FLASH_SECT 19
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200235
236
237/*
238 * Monitor config - see memory map details above
Wolfgang Denkba940932006-07-19 13:50:38 +0200239 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240 * CONFIG_SYS_MONITOR_BASE - Base address of monitor code
241 * CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB)
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200242 */
243
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200244#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200245#define CONFIG_SYS_MALLOC_LEN 0x20000
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200246
247
248/*
249 * Command shell settings
Wolfgang Denkba940932006-07-19 13:50:38 +0200250 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251 * CONFIG_SYS_BARGSIZE - Boot Argument buffer size
252 * CONFIG_SYS_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
253 * CONFIG_SYS_CBSIZE - Console Buffer (input) size
254 * CONFIG_SYS_LOAD_ADDR - Default load address
255 * CONFIG_SYS_LONGHELP - Provide more detailed help
256 * CONFIG_SYS_MAXARGS - Number of args accepted by monitor commands
257 * CONFIG_SYS_MEMTEST_START - Start address of test to run on RAM
258 * CONFIG_SYS_MEMTEST_END - End address of RAM test
259 * CONFIG_SYS_PBSIZE - Print Buffer (output) size
260 * CONFIG_SYS_PROMPT - Prompt string
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200261 */
262
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200263#define CONFIG_SYS_BARGSIZE 1024
264#define CONFIG_SYS_BOOTMAPSZ 0x800000
265#define CONFIG_SYS_CBSIZE 1024
266#define CONFIG_SYS_LOAD_ADDR 0x100000
267#define CONFIG_SYS_LONGHELP
268#define CONFIG_SYS_MAXARGS 16
269#define CONFIG_SYS_MEMTEST_START 0x00040000
270#define CONFIG_SYS_MEMTEST_END 0x00040100
271#define CONFIG_SYS_PBSIZE 1024
272#define CONFIG_SYS_PROMPT "=> "
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200273
274
275/*
276 * Environment config - see memory map details above
Wolfgang Denkba940932006-07-19 13:50:38 +0200277 *
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200278 * CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200279 * CONFIG_ENV_ADDR - Address of the sector containing env vars
280 * CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
281 * CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200282 */
283
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200284#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200285#define CONFIG_ENV_ADDR 0xFFFE0000
286#define CONFIG_ENV_SIZE 0x1000
287#define CONFIG_ENV_ADDR_REDUND 0xFFFE8000
288#define CONFIG_ENV_SIZE_REDUND 0x1000
289#define CONFIG_ENV_SECT_SIZE 0x8000
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200290
291
292/*
293 * Initial RAM config
294 *
295 * Since the main system RAM is initialised very early, we place the INIT_RAM
296 * in the main system RAM just above the exception vectors. The contents are
297 * copied to top of RAM by the init code.
Wolfgang Denkba940932006-07-19 13:50:38 +0200298 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299 * CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect
300 * CONFIG_SYS_INIT_RAM_END - Size of Init RAM
301 * CONFIG_SYS_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
302 * CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200303 */
304
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000)
306#define CONFIG_SYS_INIT_RAM_END 0x4000
307#define CONFIG_SYS_GBL_DATA_SIZE 128
308#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200309
310
311/*
312 * Initial BAT config
Wolfgang Denkba940932006-07-19 13:50:38 +0200313 *
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200314 * BAT0 - System SDRAM
315 * BAT1 - LED's and Serial Port
316 * BAT2 - PCI Memory
317 * BAT3 - PCI I/O including Flash Memory
318 */
319
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200320#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
321#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
322#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
323#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200324
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200325#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
326#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
327#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
328#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200329
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200330#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
331#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
332#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
333#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200334
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200335#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
336#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
337#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
338#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200339
340
341/*
342 * Cache config
Wolfgang Denkba940932006-07-19 13:50:38 +0200343 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200344 * CONFIG_SYS_CACHELINE_SIZE - Size of a cache line (CPU specific)
345 * CONFIG_SYS_L2 - L2 cache enabled if defined
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200346 * L2_INIT - L2 cache init flags
347 * L2_ENABLE - L2 cache enable flags
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200348 */
349
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200350#define CONFIG_SYS_CACHELINE_SIZE 32
351#undef CONFIG_SYS_L2
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200352#define L2_INIT 0
353#define L2_ENABLE 0
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200354
355
356/*
357 * Clocks config
Wolfgang Denkba940932006-07-19 13:50:38 +0200358 *
Wolfgang Denk7329f252010-06-13 18:38:23 +0200359 * CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200360 * CONFIG_SYS_HZ - Decrementer freq in Hz
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200361 */
362
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200363#define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK
364#define CONFIG_SYS_HZ 1000
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200365
366
367/*
368 * Serial port config
Wolfgang Denkba940932006-07-19 13:50:38 +0200369 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200370 * CONFIG_SYS_BAUDRATE_TABLE - List of valid baud rates
371 * CONFIG_SYS_NS16550 - Include the NS16550 driver
372 * CONFIG_SYS_NS16550_SERIAL - Include the serial (wrapper) driver
373 * CONFIG_SYS_NS16550_CLK - Frequency of reference clock
374 * CONFIG_SYS_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
375 * CONFIG_SYS_NS16550_COM1 - Base address of 1st serial port
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200376 */
377
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200378#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
379#define CONFIG_SYS_NS16550
380#define CONFIG_SYS_NS16550_SERIAL
381#define CONFIG_SYS_NS16550_CLK 3686400
382#define CONFIG_SYS_NS16550_REG_SIZE -8
383#define CONFIG_SYS_NS16550_COM1 0x7C000000
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200384
385
386/*
387 * PCI Config - Address Map B (CHRP)
388 */
389
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200390#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
391#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
392#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
393#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
394#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
395#define CONFIG_SYS_PCI_MEM_SIZE 0x7D000000
396#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
397#define CONFIG_SYS_ISA_MEM_PHYS 0xFD000000
398#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
399#define CONFIG_SYS_PCI_IO_BUS 0x00800000
400#define CONFIG_SYS_PCI_IO_PHYS 0xFE800000
401#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
402#define CONFIG_SYS_ISA_IO_BUS 0x00000000
403#define CONFIG_SYS_ISA_IO_PHYS 0xFE000000
404#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
405#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
406#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
407#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200408
409
410/*
411 * Extra init functions
Wolfgang Denkba940932006-07-19 13:50:38 +0200412 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200413 * CONFIG_SYS_BOARD_ASM_INIT - Call assembly init code
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200414 */
415
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200416#define CONFIG_SYS_BOARD_ASM_INIT
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200417
418
419/*
420 * Boot flags
Wolfgang Denkba940932006-07-19 13:50:38 +0200421 *
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200422 * BOOTFLAG_COLD - Indicates a power-on boot
423 * BOOTFLAG_WARM - Indicates a software reset
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200424 */
Wolfgang Denkba940932006-07-19 13:50:38 +0200425
Wolfgang Denk4d5a8e32007-08-02 00:48:45 +0200426#define BOOTFLAG_COLD 0x01
427#define BOOTFLAG_WARM 0x02
Heiko Schocherd7f77fb2006-06-19 11:02:41 +0200428
429
430#endif /* __CONFIG_H */