wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 1 | /* |
Detlev Zundel | 98f1908 | 2010-04-01 14:16:41 +0200 | [diff] [blame] | 2 | * (C) Copyright 2003-2010 |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * This file is based on mpc4200fec.c, |
| 6 | * (C) Copyright Motorola, Inc., 2000 |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <mpc5xxx.h> |
Ben Warren | b5a7f8f | 2008-08-28 23:58:29 -0700 | [diff] [blame] | 11 | #include <mpc5xxx_sdma.h> |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 12 | #include <malloc.h> |
| 13 | #include <net.h> |
Ben Warren | cba8851 | 2008-08-31 10:39:12 -0700 | [diff] [blame] | 14 | #include <netdev.h> |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 15 | #include <miiphy.h> |
Ben Warren | b5a7f8f | 2008-08-28 23:58:29 -0700 | [diff] [blame] | 16 | #include "mpc5xxx_fec.h" |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 17 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 20 | /* #define DEBUG 0x28 */ |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 21 | |
Jon Loeliger | 526e5ce | 2007-07-09 19:06:00 -0500 | [diff] [blame] | 22 | #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 23 | #error "CONFIG_MII has to be defined!" |
| 24 | #endif |
| 25 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 26 | #if (DEBUG & 0x60) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 27 | static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec); |
| 28 | static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 29 | #endif /* DEBUG */ |
| 30 | |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 31 | typedef struct { |
| 32 | uint8 data[1500]; /* actual data */ |
| 33 | int length; /* actual length */ |
| 34 | int used; /* buffer in use or not */ |
| 35 | uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ |
| 36 | } NBUF; |
| 37 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 38 | int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal); |
| 39 | int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); |
| 40 | |
Sascha Hauer | 3986bfa | 2009-03-21 09:38:46 -0400 | [diff] [blame] | 41 | static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis); |
| 42 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 43 | /********************************************************************/ |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 44 | #if (DEBUG & 0x2) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 45 | static void mpc5xxx_fec_phydump (char *devname) |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 46 | { |
| 47 | uint16 phyStatus, i; |
| 48 | uint8 phyAddr = CONFIG_PHY_ADDR; |
| 49 | uint8 reg_mask[] = { |
| 50 | #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */ |
| 51 | /* regs to print: 0...7, 16...19, 21, 23, 24 */ |
| 52 | 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, |
| 53 | 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, |
| 54 | #else |
| 55 | /* regs to print: 0...8, 16...20 */ |
| 56 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, |
| 57 | 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 58 | #endif |
| 59 | }; |
| 60 | |
| 61 | for (i = 0; i < 32; i++) { |
| 62 | if (reg_mask[i]) { |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 63 | miiphy_read(devname, phyAddr, i, &phyStatus); |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 64 | printf("Mii reg %d: 0x%04x\n", i, phyStatus); |
| 65 | } |
| 66 | } |
| 67 | } |
| 68 | #endif |
| 69 | |
| 70 | /********************************************************************/ |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 71 | static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec) |
| 72 | { |
| 73 | int ix; |
| 74 | char *data; |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 75 | static int once = 0; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 76 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 77 | for (ix = 0; ix < FEC_RBD_NUM; ix++) { |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 78 | if (!once) { |
| 79 | data = (char *)malloc(FEC_MAX_PKT_SIZE); |
| 80 | if (data == NULL) { |
| 81 | printf ("RBD INIT FAILED\n"); |
| 82 | return -1; |
| 83 | } |
| 84 | fec->rbdBase[ix].dataPointer = (uint32)data; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 85 | } |
| 86 | fec->rbdBase[ix].status = FEC_RBD_EMPTY; |
| 87 | fec->rbdBase[ix].dataLength = 0; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 88 | } |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 89 | once ++; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 90 | |
| 91 | /* |
| 92 | * have the last RBD to close the ring |
| 93 | */ |
| 94 | fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP; |
| 95 | fec->rbdIndex = 0; |
| 96 | |
| 97 | return 0; |
| 98 | } |
| 99 | |
| 100 | /********************************************************************/ |
| 101 | static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec) |
| 102 | { |
| 103 | int ix; |
| 104 | |
| 105 | for (ix = 0; ix < FEC_TBD_NUM; ix++) { |
| 106 | fec->tbdBase[ix].status = 0; |
| 107 | } |
| 108 | |
| 109 | /* |
| 110 | * Have the last TBD to close the ring |
| 111 | */ |
| 112 | fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP; |
| 113 | |
| 114 | /* |
| 115 | * Initialize some indices |
| 116 | */ |
| 117 | fec->tbdIndex = 0; |
| 118 | fec->usedTbdIndex = 0; |
| 119 | fec->cleanTbdNum = FEC_TBD_NUM; |
| 120 | } |
| 121 | |
| 122 | /********************************************************************/ |
wdenk | 99408ba | 2005-02-24 22:44:16 +0000 | [diff] [blame] | 123 | static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd) |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 124 | { |
| 125 | /* |
| 126 | * Reset buffer descriptor as empty |
| 127 | */ |
| 128 | if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) |
| 129 | pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); |
| 130 | else |
| 131 | pRbd->status = FEC_RBD_EMPTY; |
| 132 | |
| 133 | pRbd->dataLength = 0; |
| 134 | |
| 135 | /* |
| 136 | * Now, we have an empty RxBD, restart the SmartDMA receive task |
| 137 | */ |
| 138 | SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); |
| 139 | |
| 140 | /* |
| 141 | * Increment BD count |
| 142 | */ |
| 143 | fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; |
| 144 | } |
| 145 | |
| 146 | /********************************************************************/ |
| 147 | static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec) |
| 148 | { |
wdenk | 99408ba | 2005-02-24 22:44:16 +0000 | [diff] [blame] | 149 | volatile FEC_TBD *pUsedTbd; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 150 | |
| 151 | #if (DEBUG & 0x1) |
| 152 | printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", |
| 153 | fec->cleanTbdNum, fec->usedTbdIndex); |
| 154 | #endif |
| 155 | |
| 156 | /* |
| 157 | * process all the consumed TBDs |
| 158 | */ |
| 159 | while (fec->cleanTbdNum < FEC_TBD_NUM) { |
| 160 | pUsedTbd = &fec->tbdBase[fec->usedTbdIndex]; |
| 161 | if (pUsedTbd->status & FEC_TBD_READY) { |
| 162 | #if (DEBUG & 0x20) |
| 163 | printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum); |
| 164 | #endif |
| 165 | return; |
| 166 | } |
| 167 | |
| 168 | /* |
| 169 | * clean this buffer descriptor |
| 170 | */ |
| 171 | if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) |
| 172 | pUsedTbd->status = FEC_TBD_WRAP; |
| 173 | else |
| 174 | pUsedTbd->status = 0; |
| 175 | |
| 176 | /* |
| 177 | * update some indeces for a correct handling of the TBD ring |
| 178 | */ |
| 179 | fec->cleanTbdNum++; |
| 180 | fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; |
| 181 | } |
| 182 | } |
| 183 | |
| 184 | /********************************************************************/ |
| 185 | static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac) |
| 186 | { |
| 187 | uint8 currByte; /* byte for which to compute the CRC */ |
| 188 | int byte; /* loop - counter */ |
| 189 | int bit; /* loop - counter */ |
| 190 | uint32 crc = 0xffffffff; /* initial value */ |
| 191 | |
| 192 | /* |
| 193 | * The algorithm used is the following: |
| 194 | * we loop on each of the six bytes of the provided address, |
| 195 | * and we compute the CRC by left-shifting the previous |
| 196 | * value by one position, so that each bit in the current |
| 197 | * byte of the address may contribute the calculation. If |
| 198 | * the latter and the MSB in the CRC are different, then |
| 199 | * the CRC value so computed is also ex-ored with the |
| 200 | * "polynomium generator". The current byte of the address |
| 201 | * is also shifted right by one bit at each iteration. |
| 202 | * This is because the CRC generatore in hardware is implemented |
| 203 | * as a shift-register with as many ex-ores as the radixes |
| 204 | * in the polynomium. This suggests that we represent the |
| 205 | * polynomiumm itself as a 32-bit constant. |
| 206 | */ |
| 207 | for (byte = 0; byte < 6; byte++) { |
| 208 | currByte = mac[byte]; |
| 209 | for (bit = 0; bit < 8; bit++) { |
| 210 | if ((currByte & 0x01) ^ (crc & 0x01)) { |
| 211 | crc >>= 1; |
| 212 | crc = crc ^ 0xedb88320; |
| 213 | } else { |
| 214 | crc >>= 1; |
| 215 | } |
| 216 | currByte >>= 1; |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | crc = crc >> 26; |
| 221 | |
| 222 | /* |
| 223 | * Set individual hash table register |
| 224 | */ |
| 225 | if (crc >= 32) { |
| 226 | fec->eth->iaddr1 = (1 << (crc - 32)); |
| 227 | fec->eth->iaddr2 = 0; |
| 228 | } else { |
| 229 | fec->eth->iaddr1 = 0; |
| 230 | fec->eth->iaddr2 = (1 << crc); |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * Set physical address |
| 235 | */ |
| 236 | fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; |
| 237 | fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808; |
| 238 | } |
| 239 | |
| 240 | /********************************************************************/ |
| 241 | static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) |
| 242 | { |
| 243 | mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; |
| 244 | struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 245 | |
| 246 | #if (DEBUG & 0x1) |
| 247 | printf ("mpc5xxx_fec_init... Begin\n"); |
| 248 | #endif |
| 249 | |
Sascha Hauer | 3986bfa | 2009-03-21 09:38:46 -0400 | [diff] [blame] | 250 | mpc5xxx_fec_init_phy(dev, bis); |
| 251 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 252 | /* |
| 253 | * Initialize RxBD/TxBD rings |
| 254 | */ |
| 255 | mpc5xxx_fec_rbd_init(fec); |
| 256 | mpc5xxx_fec_tbd_init(fec); |
| 257 | |
| 258 | /* |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 259 | * Clear FEC-Lite interrupt event register(IEVENT) |
| 260 | */ |
| 261 | fec->eth->ievent = 0xffffffff; |
| 262 | |
| 263 | /* |
| 264 | * Set interrupt mask register |
| 265 | */ |
| 266 | fec->eth->imask = 0x00000000; |
| 267 | |
| 268 | /* |
| 269 | * Set FEC-Lite receive control register(R_CNTRL): |
| 270 | */ |
| 271 | if (fec->xcv_type == SEVENWIRE) { |
| 272 | /* |
| 273 | * Frame length=1518; 7-wire mode |
| 274 | */ |
| 275 | fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */ |
| 276 | } else { |
| 277 | /* |
| 278 | * Frame length=1518; MII mode; |
| 279 | */ |
| 280 | fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */ |
| 281 | } |
| 282 | |
wdenk | a09491a | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 283 | fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */ |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 284 | |
| 285 | /* |
| 286 | * Set Opcode/Pause Duration Register |
| 287 | */ |
Heiko Schocher | 23cd0b1 | 2008-01-11 15:15:14 +0100 | [diff] [blame] | 288 | fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */ |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 289 | |
| 290 | /* |
| 291 | * Set Rx FIFO alarm and granularity value |
| 292 | */ |
Wolfgang Denk | 08cb2d6 | 2005-09-04 23:19:41 +0200 | [diff] [blame] | 293 | fec->eth->rfifo_cntrl = 0x0c000000 |
| 294 | | (fec->eth->rfifo_cntrl & ~0x0f000000); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 295 | fec->eth->rfifo_alarm = 0x0000030c; |
| 296 | #if (DEBUG & 0x22) |
| 297 | if (fec->eth->rfifo_status & 0x00700000 ) { |
| 298 | printf("mpc5xxx_fec_init() RFIFO error\n"); |
| 299 | } |
| 300 | #endif |
| 301 | |
| 302 | /* |
| 303 | * Set Tx FIFO granularity value |
| 304 | */ |
Wolfgang Denk | 08cb2d6 | 2005-09-04 23:19:41 +0200 | [diff] [blame] | 305 | fec->eth->tfifo_cntrl = 0x0c000000 |
| 306 | | (fec->eth->tfifo_cntrl & ~0x0f000000); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 307 | #if (DEBUG & 0x2) |
| 308 | printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status); |
| 309 | printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm); |
| 310 | #endif |
| 311 | |
| 312 | /* |
| 313 | * Set transmit fifo watermark register(X_WMRK), default = 64 |
| 314 | */ |
| 315 | fec->eth->tfifo_alarm = 0x00000080; |
| 316 | fec->eth->x_wmrk = 0x2; |
| 317 | |
| 318 | /* |
| 319 | * Set individual address filter for unicast address |
| 320 | * and set physical address registers. |
| 321 | */ |
Wolfgang Denk | 7fb5266 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 322 | mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 323 | |
| 324 | /* |
| 325 | * Set multicast address filter |
| 326 | */ |
| 327 | fec->eth->gaddr1 = 0x00000000; |
| 328 | fec->eth->gaddr2 = 0x00000000; |
| 329 | |
| 330 | /* |
| 331 | * Turn ON cheater FSM: ???? |
| 332 | */ |
| 333 | fec->eth->xmit_fsm = 0x03000000; |
| 334 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 335 | /* |
Detlev Zundel | a414c7a | 2010-03-12 10:01:12 +0100 | [diff] [blame] | 336 | * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 337 | * work w/ the current receive task. |
| 338 | */ |
| 339 | sdma->PtdCntrl |= 0x00000001; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 340 | |
| 341 | /* |
| 342 | * Set priority of different initiators |
| 343 | */ |
| 344 | sdma->IPR0 = 7; /* always */ |
| 345 | sdma->IPR3 = 6; /* Eth RX */ |
| 346 | sdma->IPR4 = 5; /* Eth Tx */ |
| 347 | |
| 348 | /* |
| 349 | * Clear SmartDMA task interrupt pending bits |
| 350 | */ |
| 351 | SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO); |
| 352 | |
| 353 | /* |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 354 | * Initialize SmartDMA parameters stored in SRAM |
| 355 | */ |
wdenk | 99408ba | 2005-02-24 22:44:16 +0000 | [diff] [blame] | 356 | *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase; |
| 357 | *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase; |
| 358 | *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase; |
| 359 | *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 360 | |
wdenk | af14383 | 2004-05-12 22:18:31 +0000 | [diff] [blame] | 361 | /* |
| 362 | * Enable FEC-Lite controller |
| 363 | */ |
| 364 | fec->eth->ecntrl |= 0x00000006; |
| 365 | |
| 366 | #if (DEBUG & 0x2) |
| 367 | if (fec->xcv_type != SEVENWIRE) |
Heiko Schocher | acb4f4a | 2006-12-21 16:14:48 +0100 | [diff] [blame] | 368 | mpc5xxx_fec_phydump (dev->name); |
wdenk | af14383 | 2004-05-12 22:18:31 +0000 | [diff] [blame] | 369 | #endif |
| 370 | |
| 371 | /* |
| 372 | * Enable SmartDMA receive task |
| 373 | */ |
| 374 | SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); |
| 375 | |
| 376 | #if (DEBUG & 0x1) |
| 377 | printf("mpc5xxx_fec_init... Done \n"); |
| 378 | #endif |
| 379 | |
| 380 | return 1; |
| 381 | } |
| 382 | |
| 383 | /********************************************************************/ |
| 384 | static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) |
| 385 | { |
wdenk | af14383 | 2004-05-12 22:18:31 +0000 | [diff] [blame] | 386 | mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; |
| 387 | const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ |
Sascha Hauer | 3986bfa | 2009-03-21 09:38:46 -0400 | [diff] [blame] | 388 | static int initialized = 0; |
| 389 | |
| 390 | if(initialized) |
| 391 | return 0; |
| 392 | initialized = 1; |
wdenk | af14383 | 2004-05-12 22:18:31 +0000 | [diff] [blame] | 393 | |
| 394 | #if (DEBUG & 0x1) |
| 395 | printf ("mpc5xxx_fec_init_phy... Begin\n"); |
| 396 | #endif |
| 397 | |
| 398 | /* |
| 399 | * Initialize GPIO pins |
| 400 | */ |
| 401 | if (fec->xcv_type == SEVENWIRE) { |
| 402 | /* 10MBit with 7-wire operation */ |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 403 | #if defined(CONFIG_TOTAL5200) |
| 404 | /* 7-wire and USB2 on Ethernet */ |
| 405 | *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000; |
| 406 | #else /* !CONFIG_TOTAL5200 */ |
| 407 | /* 7-wire only */ |
wdenk | af14383 | 2004-05-12 22:18:31 +0000 | [diff] [blame] | 408 | *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000; |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 409 | #endif /* CONFIG_TOTAL5200 */ |
wdenk | af14383 | 2004-05-12 22:18:31 +0000 | [diff] [blame] | 410 | } else { |
| 411 | /* 100MBit with MD operation */ |
| 412 | *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000; |
| 413 | } |
| 414 | |
| 415 | /* |
| 416 | * Clear FEC-Lite interrupt event register(IEVENT) |
| 417 | */ |
| 418 | fec->eth->ievent = 0xffffffff; |
| 419 | |
| 420 | /* |
| 421 | * Set interrupt mask register |
| 422 | */ |
| 423 | fec->eth->imask = 0x00000000; |
| 424 | |
Bartlomiej Sieka | 68a0af4 | 2007-05-07 22:36:15 +0200 | [diff] [blame] | 425 | /* |
| 426 | * In original Promess-provided code PHY initialization is disabled with the |
| 427 | * following comment: "Phy initialization is DISABLED for now. There was a |
| 428 | * problem with running 100 Mbps on PRO board". Thus we temporarily disable |
| 429 | * PHY initialization for the Motion-PRO board, until a proper fix is found. |
| 430 | */ |
| 431 | |
wdenk | af14383 | 2004-05-12 22:18:31 +0000 | [diff] [blame] | 432 | if (fec->xcv_type != SEVENWIRE) { |
| 433 | /* |
| 434 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock |
| 435 | * and do not drop the Preamble. |
| 436 | */ |
| 437 | fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ |
| 438 | } |
| 439 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 440 | if (fec->xcv_type != SEVENWIRE) { |
| 441 | /* |
| 442 | * Initialize PHY(LXT971A): |
| 443 | * |
| 444 | * Generally, on power up, the LXT971A reads its configuration |
| 445 | * pins to check for forced operation, If not cofigured for |
| 446 | * forced operation, it uses auto-negotiation/parallel detection |
| 447 | * to automatically determine line operating conditions. |
| 448 | * If the PHY device on the other side of the link supports |
| 449 | * auto-negotiation, the LXT971A auto-negotiates with it |
| 450 | * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not |
| 451 | * support auto-negotiation, the LXT971A automatically detects |
| 452 | * the presence of either link pulses(10Mbps PHY) or Idle |
| 453 | * symbols(100Mbps) and sets its operating conditions accordingly. |
| 454 | * |
| 455 | * When auto-negotiation is controlled by software, the following |
| 456 | * steps are recommended. |
| 457 | * |
| 458 | * Note: |
| 459 | * The physical address is dependent on hardware configuration. |
| 460 | * |
| 461 | */ |
| 462 | int timeout = 1; |
| 463 | uint16 phyStatus; |
| 464 | |
| 465 | /* |
| 466 | * Reset PHY, then delay 300ns |
| 467 | */ |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 468 | miiphy_write(dev->name, phyAddr, 0x0, 0x8000); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 469 | udelay(1000); |
| 470 | |
Heiko Schocher | 4e5781b | 2008-08-21 20:44:49 +0200 | [diff] [blame] | 471 | #if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52) |
| 472 | /* Set the LED configuration Register for the UC101 |
| 473 | and MUCMC52 Board */ |
Heiko Schocher | 71400bf | 2007-04-14 05:26:48 +0200 | [diff] [blame] | 474 | miiphy_write(dev->name, phyAddr, 0x14, 0x4122); |
| 475 | #endif |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 476 | if (fec->xcv_type == MII10) { |
| 477 | /* |
| 478 | * Force 10Base-T, FDX operation |
| 479 | */ |
wdenk | 56bb535 | 2003-09-16 17:29:31 +0000 | [diff] [blame] | 480 | #if (DEBUG & 0x2) |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 481 | printf("Forcing 10 Mbps ethernet link... "); |
wdenk | 56bb535 | 2003-09-16 17:29:31 +0000 | [diff] [blame] | 482 | #endif |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 483 | miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 484 | /* |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 485 | miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 486 | */ |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 487 | miiphy_write(dev->name, phyAddr, 0x0, 0x0180); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 488 | |
| 489 | timeout = 20; |
| 490 | do { /* wait for link status to go down */ |
| 491 | udelay(10000); |
| 492 | if ((timeout--) == 0) { |
| 493 | #if (DEBUG & 0x2) |
| 494 | printf("hmmm, should not have waited..."); |
| 495 | #endif |
| 496 | break; |
| 497 | } |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 498 | miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 499 | #if (DEBUG & 0x2) |
| 500 | printf("="); |
| 501 | #endif |
| 502 | } while ((phyStatus & 0x0004)); /* !link up */ |
| 503 | |
| 504 | timeout = 1000; |
| 505 | do { /* wait for link status to come back up */ |
| 506 | udelay(10000); |
| 507 | if ((timeout--) == 0) { |
| 508 | printf("failed. Link is down.\n"); |
| 509 | break; |
| 510 | } |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 511 | miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 512 | #if (DEBUG & 0x2) |
| 513 | printf("+"); |
| 514 | #endif |
| 515 | } while (!(phyStatus & 0x0004)); /* !link up */ |
| 516 | |
dzu | 6217792 | 2003-09-30 14:08:43 +0000 | [diff] [blame] | 517 | #if (DEBUG & 0x2) |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 518 | printf ("done.\n"); |
dzu | 6217792 | 2003-09-30 14:08:43 +0000 | [diff] [blame] | 519 | #endif |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 520 | } else { /* MII100 */ |
| 521 | /* |
| 522 | * Set the auto-negotiation advertisement register bits |
| 523 | */ |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 524 | miiphy_write(dev->name, phyAddr, 0x4, 0x01e1); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 525 | |
| 526 | /* |
| 527 | * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation |
| 528 | */ |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 529 | miiphy_write(dev->name, phyAddr, 0x0, 0x1200); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 530 | |
| 531 | /* |
| 532 | * Wait for AN completion |
| 533 | */ |
| 534 | timeout = 5000; |
| 535 | do { |
| 536 | udelay(1000); |
| 537 | |
| 538 | if ((timeout--) == 0) { |
| 539 | #if (DEBUG & 0x2) |
| 540 | printf("PHY auto neg 0 failed...\n"); |
| 541 | #endif |
| 542 | return -1; |
| 543 | } |
| 544 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 545 | if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) { |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 546 | #if (DEBUG & 0x2) |
| 547 | printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus); |
| 548 | #endif |
| 549 | return -1; |
| 550 | } |
wdenk | a09491a | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 551 | } while (!(phyStatus & 0x0004)); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 552 | |
| 553 | #if (DEBUG & 0x2) |
| 554 | printf("PHY auto neg complete! \n"); |
| 555 | #endif |
| 556 | } |
| 557 | |
| 558 | } |
| 559 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 560 | #if (DEBUG & 0x2) |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 561 | if (fec->xcv_type != SEVENWIRE) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 562 | mpc5xxx_fec_phydump (dev->name); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 563 | #endif |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 564 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 565 | |
| 566 | #if (DEBUG & 0x1) |
wdenk | af14383 | 2004-05-12 22:18:31 +0000 | [diff] [blame] | 567 | printf("mpc5xxx_fec_init_phy... Done \n"); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 568 | #endif |
| 569 | |
wdenk | 3f08e20 | 2003-08-07 14:52:18 +0000 | [diff] [blame] | 570 | return 1; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 571 | } |
| 572 | |
| 573 | /********************************************************************/ |
| 574 | static void mpc5xxx_fec_halt(struct eth_device *dev) |
| 575 | { |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 576 | struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 577 | mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 578 | int counter = 0xffff; |
| 579 | |
| 580 | #if (DEBUG & 0x2) |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 581 | if (fec->xcv_type != SEVENWIRE) |
Heiko Schocher | acb4f4a | 2006-12-21 16:14:48 +0100 | [diff] [blame] | 582 | mpc5xxx_fec_phydump (dev->name); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 583 | #endif |
| 584 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 585 | /* |
| 586 | * mask FEC chip interrupts |
| 587 | */ |
| 588 | fec->eth->imask = 0; |
| 589 | |
| 590 | /* |
| 591 | * issue graceful stop command to the FEC transmitter if necessary |
| 592 | */ |
| 593 | fec->eth->x_cntrl |= 0x00000001; |
| 594 | |
| 595 | /* |
| 596 | * wait for graceful stop to register |
| 597 | */ |
| 598 | while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ; |
| 599 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 600 | /* |
| 601 | * Disable SmartDMA tasks |
| 602 | */ |
| 603 | SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO); |
| 604 | SDMA_TASK_DISABLE (FEC_RECV_TASK_NO); |
| 605 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 606 | /* |
Detlev Zundel | a414c7a | 2010-03-12 10:01:12 +0100 | [diff] [blame] | 607 | * Turn on COMM bus prefetch in the MPC5200 BestComm after we're |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 608 | * done. It doesn't work w/ the current receive task. |
| 609 | */ |
| 610 | sdma->PtdCntrl &= ~0x00000001; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 611 | |
| 612 | /* |
| 613 | * Disable the Ethernet Controller |
| 614 | */ |
| 615 | fec->eth->ecntrl &= 0xfffffffd; |
| 616 | |
| 617 | /* |
| 618 | * Clear FIFO status registers |
| 619 | */ |
| 620 | fec->eth->rfifo_status &= 0x00700000; |
| 621 | fec->eth->tfifo_status &= 0x00700000; |
| 622 | |
| 623 | fec->eth->reset_cntrl = 0x01000000; |
| 624 | |
| 625 | /* |
| 626 | * Issue a reset command to the FEC chip |
| 627 | */ |
| 628 | fec->eth->ecntrl |= 0x1; |
| 629 | |
| 630 | /* |
| 631 | * wait at least 16 clock cycles |
| 632 | */ |
| 633 | udelay(10); |
| 634 | |
Jon Smirl | bc99a36 | 2009-03-11 15:08:56 -0400 | [diff] [blame] | 635 | /* don't leave the MII speed set to zero */ |
| 636 | if (fec->xcv_type != SEVENWIRE) { |
| 637 | /* |
| 638 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock |
| 639 | * and do not drop the Preamble. |
| 640 | */ |
| 641 | fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ |
| 642 | } |
| 643 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 644 | #if (DEBUG & 0x3) |
| 645 | printf("Ethernet task stopped\n"); |
| 646 | #endif |
| 647 | } |
| 648 | |
| 649 | #if (DEBUG & 0x60) |
| 650 | /********************************************************************/ |
| 651 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 652 | static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec) |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 653 | { |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 654 | uint16 phyAddr = CONFIG_PHY_ADDR; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 655 | uint16 phyStatus; |
| 656 | |
| 657 | if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr) |
| 658 | || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) { |
| 659 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 660 | miiphy_read(devname, phyAddr, 0x1, &phyStatus); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 661 | printf("\nphyStatus: 0x%04x\n", phyStatus); |
| 662 | printf("ecntrl: 0x%08x\n", fec->eth->ecntrl); |
| 663 | printf("ievent: 0x%08x\n", fec->eth->ievent); |
| 664 | printf("x_status: 0x%08x\n", fec->eth->x_status); |
| 665 | printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status); |
| 666 | |
| 667 | printf(" control 0x%08x\n", fec->eth->tfifo_cntrl); |
| 668 | printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr); |
| 669 | printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr); |
| 670 | printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm); |
| 671 | printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr); |
| 672 | printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr); |
| 673 | } |
| 674 | } |
| 675 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 676 | static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec) |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 677 | { |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 678 | uint16 phyAddr = CONFIG_PHY_ADDR; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 679 | uint16 phyStatus; |
| 680 | |
| 681 | if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr) |
| 682 | || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) { |
| 683 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 684 | miiphy_read(devname, phyAddr, 0x1, &phyStatus); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 685 | printf("\nphyStatus: 0x%04x\n", phyStatus); |
| 686 | printf("ecntrl: 0x%08x\n", fec->eth->ecntrl); |
| 687 | printf("ievent: 0x%08x\n", fec->eth->ievent); |
| 688 | printf("x_status: 0x%08x\n", fec->eth->x_status); |
| 689 | printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status); |
| 690 | |
| 691 | printf(" control 0x%08x\n", fec->eth->rfifo_cntrl); |
| 692 | printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr); |
| 693 | printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr); |
| 694 | printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm); |
| 695 | printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr); |
| 696 | printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr); |
| 697 | } |
| 698 | } |
| 699 | #endif /* DEBUG */ |
| 700 | |
| 701 | /********************************************************************/ |
| 702 | |
| 703 | static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data, |
| 704 | int data_length) |
| 705 | { |
| 706 | /* |
| 707 | * This routine transmits one frame. This routine only accepts |
| 708 | * 6-byte Ethernet addresses. |
| 709 | */ |
| 710 | mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; |
wdenk | 99408ba | 2005-02-24 22:44:16 +0000 | [diff] [blame] | 711 | volatile FEC_TBD *pTbd; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 712 | |
| 713 | #if (DEBUG & 0x20) |
| 714 | printf("tbd status: 0x%04x\n", fec->tbdBase[0].status); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 715 | tfifo_print(dev->name, fec); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 716 | #endif |
| 717 | |
| 718 | /* |
| 719 | * Clear Tx BD ring at first |
| 720 | */ |
| 721 | mpc5xxx_fec_tbd_scrub(fec); |
| 722 | |
| 723 | /* |
| 724 | * Check for valid length of data. |
| 725 | */ |
| 726 | if ((data_length > 1500) || (data_length <= 0)) { |
| 727 | return -1; |
| 728 | } |
| 729 | |
| 730 | /* |
| 731 | * Check the number of vacant TxBDs. |
| 732 | */ |
| 733 | if (fec->cleanTbdNum < 1) { |
| 734 | #if (DEBUG & 0x20) |
| 735 | printf("No available TxBDs ...\n"); |
| 736 | #endif |
| 737 | return -1; |
| 738 | } |
| 739 | |
| 740 | /* |
| 741 | * Get the first TxBD to send the mac header |
| 742 | */ |
| 743 | pTbd = &fec->tbdBase[fec->tbdIndex]; |
| 744 | pTbd->dataLength = data_length; |
| 745 | pTbd->dataPointer = (uint32)eth_data; |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 746 | pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 747 | fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; |
| 748 | |
| 749 | #if (DEBUG & 0x100) |
| 750 | printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex); |
| 751 | #endif |
| 752 | |
| 753 | /* |
| 754 | * Kick the MII i/f |
| 755 | */ |
| 756 | if (fec->xcv_type != SEVENWIRE) { |
| 757 | uint16 phyStatus; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 758 | miiphy_read(dev->name, 0, 0x1, &phyStatus); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 759 | } |
| 760 | |
| 761 | /* |
| 762 | * Enable SmartDMA transmit task |
| 763 | */ |
| 764 | |
| 765 | #if (DEBUG & 0x20) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 766 | tfifo_print(dev->name, fec); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 767 | #endif |
| 768 | SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO); |
| 769 | #if (DEBUG & 0x20) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 770 | tfifo_print(dev->name, fec); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 771 | #endif |
| 772 | #if (DEBUG & 0x8) |
| 773 | printf( "+" ); |
| 774 | #endif |
| 775 | |
| 776 | fec->cleanTbdNum -= 1; |
| 777 | |
| 778 | #if (DEBUG & 0x129) && (DEBUG & 0x80000000) |
| 779 | printf ("smartDMA ethernet Tx task enabled\n"); |
| 780 | #endif |
| 781 | /* |
| 782 | * wait until frame is sent . |
| 783 | */ |
| 784 | while (pTbd->status & FEC_TBD_READY) { |
| 785 | udelay(10); |
| 786 | #if (DEBUG & 0x8) |
| 787 | printf ("TDB status = %04x\n", pTbd->status); |
| 788 | #endif |
| 789 | } |
| 790 | |
| 791 | return 0; |
| 792 | } |
| 793 | |
| 794 | |
| 795 | /********************************************************************/ |
| 796 | static int mpc5xxx_fec_recv(struct eth_device *dev) |
| 797 | { |
| 798 | /* |
| 799 | * This command pulls one frame from the card |
| 800 | */ |
| 801 | mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; |
wdenk | 99408ba | 2005-02-24 22:44:16 +0000 | [diff] [blame] | 802 | volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex]; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 803 | unsigned long ievent; |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 804 | int frame_length, len = 0; |
| 805 | NBUF *frame; |
Wolfgang Denk | 7fb5266 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 806 | uchar buff[FEC_MAX_PKT_SIZE]; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 807 | |
| 808 | #if (DEBUG & 0x1) |
| 809 | printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex); |
| 810 | #endif |
| 811 | #if (DEBUG & 0x8) |
| 812 | printf( "-" ); |
| 813 | #endif |
| 814 | |
| 815 | /* |
| 816 | * Check if any critical events have happened |
| 817 | */ |
| 818 | ievent = fec->eth->ievent; |
| 819 | fec->eth->ievent = ievent; |
| 820 | if (ievent & 0x20060000) { |
| 821 | /* BABT, Rx/Tx FIFO errors */ |
| 822 | mpc5xxx_fec_halt(dev); |
| 823 | mpc5xxx_fec_init(dev, NULL); |
| 824 | return 0; |
| 825 | } |
| 826 | if (ievent & 0x80000000) { |
| 827 | /* Heartbeat error */ |
| 828 | fec->eth->x_cntrl |= 0x00000001; |
| 829 | } |
| 830 | if (ievent & 0x10000000) { |
| 831 | /* Graceful stop complete */ |
| 832 | if (fec->eth->x_cntrl & 0x00000001) { |
| 833 | mpc5xxx_fec_halt(dev); |
| 834 | fec->eth->x_cntrl &= ~0x00000001; |
| 835 | mpc5xxx_fec_init(dev, NULL); |
| 836 | } |
| 837 | } |
| 838 | |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 839 | if (!(pRbd->status & FEC_RBD_EMPTY)) { |
| 840 | if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) && |
| 841 | ((pRbd->dataLength - 4) > 14)) { |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 842 | |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 843 | /* |
| 844 | * Get buffer address and size |
| 845 | */ |
| 846 | frame = (NBUF *)pRbd->dataPointer; |
| 847 | frame_length = pRbd->dataLength - 4; |
| 848 | |
| 849 | #if (DEBUG & 0x20) |
| 850 | { |
| 851 | int i; |
| 852 | printf("recv data hdr:"); |
| 853 | for (i = 0; i < 14; i++) |
| 854 | printf("%x ", *(frame->head + i)); |
| 855 | printf("\n"); |
| 856 | } |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 857 | #endif |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 858 | /* |
| 859 | * Fill the buffer and pass it to upper layers |
| 860 | */ |
| 861 | memcpy(buff, frame->head, 14); |
| 862 | memcpy(buff + 14, frame->data, frame_length); |
| 863 | NetReceive(buff, frame_length); |
| 864 | len = frame_length; |
| 865 | } |
| 866 | /* |
| 867 | * Reset buffer descriptor as empty |
| 868 | */ |
| 869 | mpc5xxx_fec_rbd_clean(fec, pRbd); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 870 | } |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 871 | SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); |
| 872 | return len; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 873 | } |
| 874 | |
| 875 | |
| 876 | /********************************************************************/ |
| 877 | int mpc5xxx_fec_initialize(bd_t * bis) |
| 878 | { |
| 879 | mpc5xxx_fec_priv *fec; |
| 880 | struct eth_device *dev; |
wdenk | 232fe0b | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 881 | char *tmp, *end; |
| 882 | char env_enetaddr[6]; |
| 883 | int i; |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 884 | |
| 885 | fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec)); |
| 886 | dev = (struct eth_device *)malloc(sizeof(*dev)); |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 887 | memset(dev, 0, sizeof *dev); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 888 | |
| 889 | fec->eth = (ethernet_regs *)MPC5XXX_FEC; |
| 890 | fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; |
| 891 | fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); |
Ben Warren | bc1b917 | 2009-02-05 23:58:25 -0800 | [diff] [blame] | 892 | #if defined(CONFIG_MPC5xxx_FEC_MII100) |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 893 | fec->xcv_type = MII100; |
Ben Warren | bc1b917 | 2009-02-05 23:58:25 -0800 | [diff] [blame] | 894 | #elif defined(CONFIG_MPC5xxx_FEC_MII10) |
wdenk | 56bb535 | 2003-09-16 17:29:31 +0000 | [diff] [blame] | 895 | fec->xcv_type = MII10; |
Ben Warren | bc1b917 | 2009-02-05 23:58:25 -0800 | [diff] [blame] | 896 | #elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE) |
wdenk | cc3f8a9 | 2004-07-11 19:17:20 +0000 | [diff] [blame] | 897 | fec->xcv_type = SEVENWIRE; |
wdenk | 56bb535 | 2003-09-16 17:29:31 +0000 | [diff] [blame] | 898 | #else |
| 899 | #error fec->xcv_type not initialized. |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 900 | #endif |
Jon Smirl | bc99a36 | 2009-03-11 15:08:56 -0400 | [diff] [blame] | 901 | if (fec->xcv_type != SEVENWIRE) { |
| 902 | /* |
| 903 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock |
| 904 | * and do not drop the Preamble. |
| 905 | */ |
| 906 | fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ |
| 907 | } |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 908 | |
| 909 | dev->priv = (void *)fec; |
| 910 | dev->iobase = MPC5XXX_FEC; |
| 911 | dev->init = mpc5xxx_fec_init; |
| 912 | dev->halt = mpc5xxx_fec_halt; |
| 913 | dev->send = mpc5xxx_fec_send; |
| 914 | dev->recv = mpc5xxx_fec_recv; |
| 915 | |
wdenk | b846356 | 2003-07-26 08:08:08 +0000 | [diff] [blame] | 916 | sprintf(dev->name, "FEC ETHERNET"); |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 917 | eth_register(dev); |
| 918 | |
Jon Loeliger | 526e5ce | 2007-07-09 19:06:00 -0500 | [diff] [blame] | 919 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 920 | miiphy_register (dev->name, |
| 921 | fec5xxx_miiphy_read, fec5xxx_miiphy_write); |
| 922 | #endif |
| 923 | |
wdenk | 232fe0b | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 924 | /* |
| 925 | * Try to set the mac address now. The fec mac address is |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 926 | * a garbage after reset. When not using fec for booting |
wdenk | 232fe0b | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 927 | * the Linux fec driver will try to work with this garbage. |
| 928 | */ |
| 929 | tmp = getenv("ethaddr"); |
| 930 | if (tmp) { |
| 931 | for (i=0; i<6; i++) { |
| 932 | env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; |
| 933 | if (tmp) |
| 934 | tmp = (*end) ? end+1 : end; |
| 935 | } |
| 936 | mpc5xxx_fec_set_hwaddr(fec, env_enetaddr); |
| 937 | } |
| 938 | |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 939 | return 1; |
| 940 | } |
| 941 | |
| 942 | /* MII-interface related functions */ |
| 943 | /********************************************************************/ |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 944 | int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal) |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 945 | { |
| 946 | ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; |
| 947 | uint32 reg; /* convenient holder for the PHY register */ |
| 948 | uint32 phy; /* convenient holder for the PHY */ |
| 949 | int timeout = 0xffff; |
| 950 | |
| 951 | /* |
| 952 | * reading from any PHY's register is done by properly |
| 953 | * programming the FEC's MII data register. |
| 954 | */ |
| 955 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
| 956 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; |
| 957 | |
| 958 | eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg); |
| 959 | |
| 960 | /* |
| 961 | * wait for the related interrupt |
| 962 | */ |
| 963 | while ((timeout--) && (!(eth->ievent & 0x00800000))) ; |
| 964 | |
| 965 | if (timeout == 0) { |
| 966 | #if (DEBUG & 0x2) |
| 967 | printf ("Read MDIO failed...\n"); |
| 968 | #endif |
| 969 | return -1; |
| 970 | } |
| 971 | |
| 972 | /* |
| 973 | * clear mii interrupt bit |
| 974 | */ |
| 975 | eth->ievent = 0x00800000; |
| 976 | |
| 977 | /* |
| 978 | * it's now safe to read the PHY's register |
| 979 | */ |
| 980 | *retVal = (uint16) eth->mii_data; |
| 981 | |
| 982 | return 0; |
| 983 | } |
| 984 | |
| 985 | /********************************************************************/ |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 986 | int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data) |
wdenk | 21136db | 2003-07-16 21:53:01 +0000 | [diff] [blame] | 987 | { |
| 988 | ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; |
| 989 | uint32 reg; /* convenient holder for the PHY register */ |
| 990 | uint32 phy; /* convenient holder for the PHY */ |
| 991 | int timeout = 0xffff; |
| 992 | |
| 993 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
| 994 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; |
| 995 | |
| 996 | eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | |
| 997 | FEC_MII_DATA_TA | phy | reg | data); |
| 998 | |
| 999 | /* |
| 1000 | * wait for the MII interrupt |
| 1001 | */ |
| 1002 | while ((timeout--) && (!(eth->ievent & 0x00800000))) ; |
| 1003 | |
| 1004 | if (timeout == 0) { |
| 1005 | #if (DEBUG & 0x2) |
| 1006 | printf ("Write MDIO failed...\n"); |
| 1007 | #endif |
| 1008 | return -1; |
| 1009 | } |
| 1010 | |
| 1011 | /* |
| 1012 | * clear MII interrupt bit |
| 1013 | */ |
| 1014 | eth->ievent = 0x00800000; |
| 1015 | |
| 1016 | return 0; |
| 1017 | } |