wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 3 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 4 | Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms of the GNU General Public License as published by the Free |
| 8 | Software Foundation; either version 2 of the License, or (at your option) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 9 | any later version. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 10 | |
| 11 | This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 14 | more details. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 15 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 16 | You should have received a copy of the GNU General Public License along with |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 17 | this program; if not, write to the Free Software Foundation, Inc., 59 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 18 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 19 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 20 | The full GNU General Public License is included in this distribution in the |
| 21 | file called LICENSE. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 22 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 23 | Contact Information: |
| 24 | Linux NICS <linux.nics@intel.com> |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | |
| 27 | *******************************************************************************/ |
| 28 | |
| 29 | /* e1000_hw.h |
| 30 | * Structures, enums, and macros for the MAC |
| 31 | */ |
| 32 | |
| 33 | #ifndef _E1000_HW_H_ |
| 34 | #define _E1000_HW_H_ |
| 35 | |
| 36 | #include <common.h> |
| 37 | #include <malloc.h> |
| 38 | #include <net.h> |
Ben Warren | 050019d | 2008-08-31 10:44:19 -0700 | [diff] [blame] | 39 | #include <netdev.h> |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 40 | #include <asm/io.h> |
| 41 | #include <pci.h> |
| 42 | |
| 43 | #define E1000_ERR(args...) printf("e1000: " args) |
| 44 | |
| 45 | #ifdef E1000_DEBUG |
| 46 | #define E1000_DBG(args...) printf("e1000: " args) |
| 47 | #define DEBUGOUT(fmt,args...) printf(fmt ,##args) |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 48 | #define DEBUGFUNC() printf("%s\n", __FUNCTION__); |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 49 | #else |
| 50 | #define E1000_DBG(args...) |
| 51 | #define DEBUGFUNC() |
| 52 | #define DEBUGOUT(fmt,args...) |
| 53 | #endif |
| 54 | |
| 55 | /* Forward declarations of structures used by the shared code */ |
| 56 | struct e1000_hw; |
| 57 | struct e1000_hw_stats; |
| 58 | |
| 59 | typedef enum { |
| 60 | FALSE = 0, |
| 61 | TRUE = 1 |
| 62 | } boolean_t; |
| 63 | |
| 64 | /* Enumerated types specific to the e1000 hardware */ |
| 65 | /* Media Access Controlers */ |
| 66 | typedef enum { |
| 67 | e1000_undefined = 0, |
| 68 | e1000_82542_rev2_0, |
| 69 | e1000_82542_rev2_1, |
| 70 | e1000_82543, |
| 71 | e1000_82544, |
| 72 | e1000_82540, |
| 73 | e1000_82545, |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 74 | e1000_82545_rev_3, |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 75 | e1000_82546, |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 76 | e1000_82546_rev_3, |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 77 | e1000_82541, |
| 78 | e1000_82541_rev_2, |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 79 | e1000_82547, |
| 80 | e1000_82547_rev_2, |
| 81 | e1000_82571, |
| 82 | e1000_82572, |
| 83 | e1000_82573, |
| 84 | e1000_80003es2lan, |
| 85 | e1000_ich8lan, |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 86 | e1000_num_macs |
| 87 | } e1000_mac_type; |
| 88 | |
| 89 | /* Media Types */ |
| 90 | typedef enum { |
| 91 | e1000_media_type_copper = 0, |
| 92 | e1000_media_type_fiber = 1, |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 93 | e1000_media_type_internal_serdes = 2, |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 94 | e1000_num_media_types |
| 95 | } e1000_media_type; |
| 96 | |
| 97 | typedef enum { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 98 | e1000_eeprom_uninitialized = 0, |
| 99 | e1000_eeprom_spi, |
| 100 | e1000_eeprom_microwire, |
| 101 | e1000_eeprom_flash, |
| 102 | e1000_eeprom_ich8, |
| 103 | e1000_eeprom_none, /* No NVM support */ |
| 104 | e1000_num_eeprom_types |
| 105 | } e1000_eeprom_type; |
| 106 | |
| 107 | typedef enum { |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 108 | e1000_10_half = 0, |
| 109 | e1000_10_full = 1, |
| 110 | e1000_100_half = 2, |
| 111 | e1000_100_full = 3 |
| 112 | } e1000_speed_duplex_type; |
| 113 | |
| 114 | typedef enum { |
| 115 | e1000_lan_a = 0, |
| 116 | e1000_lan_b = 1 |
| 117 | } e1000_lan_loc; |
| 118 | |
| 119 | /* Flow Control Settings */ |
| 120 | typedef enum { |
| 121 | e1000_fc_none = 0, |
| 122 | e1000_fc_rx_pause = 1, |
| 123 | e1000_fc_tx_pause = 2, |
| 124 | e1000_fc_full = 3, |
| 125 | e1000_fc_default = 0xFF |
| 126 | } e1000_fc_type; |
| 127 | |
| 128 | /* PCI bus types */ |
| 129 | typedef enum { |
| 130 | e1000_bus_type_unknown = 0, |
| 131 | e1000_bus_type_pci, |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 132 | e1000_bus_type_pcix, |
| 133 | e1000_bus_type_pci_express, |
| 134 | e1000_bus_type_reserved |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 135 | } e1000_bus_type; |
| 136 | |
| 137 | /* PCI bus speeds */ |
| 138 | typedef enum { |
| 139 | e1000_bus_speed_unknown = 0, |
| 140 | e1000_bus_speed_33, |
| 141 | e1000_bus_speed_66, |
| 142 | e1000_bus_speed_100, |
| 143 | e1000_bus_speed_133, |
| 144 | e1000_bus_speed_reserved |
| 145 | } e1000_bus_speed; |
| 146 | |
| 147 | /* PCI bus widths */ |
| 148 | typedef enum { |
| 149 | e1000_bus_width_unknown = 0, |
| 150 | e1000_bus_width_32, |
| 151 | e1000_bus_width_64 |
| 152 | } e1000_bus_width; |
| 153 | |
| 154 | /* PHY status info structure and supporting enums */ |
| 155 | typedef enum { |
| 156 | e1000_cable_length_50 = 0, |
| 157 | e1000_cable_length_50_80, |
| 158 | e1000_cable_length_80_110, |
| 159 | e1000_cable_length_110_140, |
| 160 | e1000_cable_length_140, |
| 161 | e1000_cable_length_undefined = 0xFF |
| 162 | } e1000_cable_length; |
| 163 | |
| 164 | typedef enum { |
| 165 | e1000_10bt_ext_dist_enable_normal = 0, |
| 166 | e1000_10bt_ext_dist_enable_lower, |
| 167 | e1000_10bt_ext_dist_enable_undefined = 0xFF |
| 168 | } e1000_10bt_ext_dist_enable; |
| 169 | |
| 170 | typedef enum { |
| 171 | e1000_rev_polarity_normal = 0, |
| 172 | e1000_rev_polarity_reversed, |
| 173 | e1000_rev_polarity_undefined = 0xFF |
| 174 | } e1000_rev_polarity; |
| 175 | |
| 176 | typedef enum { |
| 177 | e1000_polarity_reversal_enabled = 0, |
| 178 | e1000_polarity_reversal_disabled, |
| 179 | e1000_polarity_reversal_undefined = 0xFF |
| 180 | } e1000_polarity_reversal; |
| 181 | |
| 182 | typedef enum { |
| 183 | e1000_auto_x_mode_manual_mdi = 0, |
| 184 | e1000_auto_x_mode_manual_mdix, |
| 185 | e1000_auto_x_mode_auto1, |
| 186 | e1000_auto_x_mode_auto2, |
| 187 | e1000_auto_x_mode_undefined = 0xFF |
| 188 | } e1000_auto_x_mode; |
| 189 | |
| 190 | typedef enum { |
| 191 | e1000_1000t_rx_status_not_ok = 0, |
| 192 | e1000_1000t_rx_status_ok, |
| 193 | e1000_1000t_rx_status_undefined = 0xFF |
| 194 | } e1000_1000t_rx_status; |
| 195 | |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 196 | typedef enum { |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 197 | e1000_phy_m88 = 0, |
| 198 | e1000_phy_igp, |
| 199 | e1000_phy_igp_2, |
| 200 | e1000_phy_gg82563, |
| 201 | e1000_phy_igp_3, |
| 202 | e1000_phy_ife, |
| 203 | e1000_phy_undefined = 0xFF |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 204 | } e1000_phy_type; |
| 205 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 206 | struct e1000_phy_info { |
| 207 | e1000_cable_length cable_length; |
| 208 | e1000_10bt_ext_dist_enable extended_10bt_distance; |
| 209 | e1000_rev_polarity cable_polarity; |
| 210 | e1000_polarity_reversal polarity_correction; |
| 211 | e1000_auto_x_mode mdix_mode; |
| 212 | e1000_1000t_rx_status local_rx; |
| 213 | e1000_1000t_rx_status remote_rx; |
| 214 | }; |
| 215 | |
| 216 | struct e1000_phy_stats { |
| 217 | uint32_t idle_errors; |
| 218 | uint32_t receive_errors; |
| 219 | }; |
| 220 | |
| 221 | /* Error Codes */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 222 | #define E1000_SUCCESS 0 |
| 223 | #define E1000_ERR_EEPROM 1 |
| 224 | #define E1000_ERR_PHY 2 |
| 225 | #define E1000_ERR_CONFIG 3 |
| 226 | #define E1000_ERR_PARAM 4 |
| 227 | #define E1000_ERR_MAC_TYPE 5 |
| 228 | #define E1000_ERR_PHY_TYPE 6 |
| 229 | #define E1000_ERR_NOLINK 7 |
| 230 | #define E1000_ERR_TIMEOUT 8 |
| 231 | #define E1000_ERR_RESET 9 |
| 232 | #define E1000_ERR_MASTER_REQUESTS_PENDING 10 |
| 233 | #define E1000_ERR_HOST_INTERFACE_COMMAND 11 |
| 234 | #define E1000_BLK_PHY_RESET 12 |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 235 | #define E1000_ERR_SWFW_SYNC 13 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 236 | |
| 237 | /* PCI Device IDs */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 238 | #define E1000_DEV_ID_82542 0x1000 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 239 | #define E1000_DEV_ID_82543GC_FIBER 0x1001 |
| 240 | #define E1000_DEV_ID_82543GC_COPPER 0x1004 |
| 241 | #define E1000_DEV_ID_82544EI_COPPER 0x1008 |
| 242 | #define E1000_DEV_ID_82544EI_FIBER 0x1009 |
| 243 | #define E1000_DEV_ID_82544GC_COPPER 0x100C |
| 244 | #define E1000_DEV_ID_82544GC_LOM 0x100D |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 245 | #define E1000_DEV_ID_82540EM 0x100E |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 246 | #define E1000_DEV_ID_82540EM_LOM 0x1015 |
| 247 | #define E1000_DEV_ID_82540EP_LOM 0x1016 |
| 248 | #define E1000_DEV_ID_82540EP 0x1017 |
| 249 | #define E1000_DEV_ID_82540EP_LP 0x101E |
| 250 | #define E1000_DEV_ID_82545EM_COPPER 0x100F |
| 251 | #define E1000_DEV_ID_82545EM_FIBER 0x1011 |
| 252 | #define E1000_DEV_ID_82545GM_COPPER 0x1026 |
| 253 | #define E1000_DEV_ID_82545GM_FIBER 0x1027 |
| 254 | #define E1000_DEV_ID_82545GM_SERDES 0x1028 |
| 255 | #define E1000_DEV_ID_82546EB_COPPER 0x1010 |
| 256 | #define E1000_DEV_ID_82546EB_FIBER 0x1012 |
| 257 | #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D |
| 258 | #define E1000_DEV_ID_82541EI 0x1013 |
| 259 | #define E1000_DEV_ID_82541EI_MOBILE 0x1018 |
| 260 | #define E1000_DEV_ID_82541ER_LOM 0x1014 |
| 261 | #define E1000_DEV_ID_82541ER 0x1078 |
| 262 | #define E1000_DEV_ID_82547GI 0x1075 |
| 263 | #define E1000_DEV_ID_82541GI 0x1076 |
| 264 | #define E1000_DEV_ID_82541GI_MOBILE 0x1077 |
| 265 | #define E1000_DEV_ID_82541GI_LF 0x107C |
| 266 | #define E1000_DEV_ID_82546GB_COPPER 0x1079 |
| 267 | #define E1000_DEV_ID_82546GB_FIBER 0x107A |
| 268 | #define E1000_DEV_ID_82546GB_SERDES 0x107B |
| 269 | #define E1000_DEV_ID_82546GB_PCIE 0x108A |
| 270 | #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 |
| 271 | #define E1000_DEV_ID_82547EI 0x1019 |
| 272 | #define E1000_DEV_ID_82547EI_MOBILE 0x101A |
| 273 | #define E1000_DEV_ID_82571EB_COPPER 0x105E |
| 274 | #define E1000_DEV_ID_82571EB_FIBER 0x105F |
| 275 | #define E1000_DEV_ID_82571EB_SERDES 0x1060 |
| 276 | #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 |
| 277 | #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 |
| 278 | #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 |
| 279 | #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC |
| 280 | #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 |
| 281 | #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA |
| 282 | #define E1000_DEV_ID_82572EI_COPPER 0x107D |
| 283 | #define E1000_DEV_ID_82572EI_FIBER 0x107E |
| 284 | #define E1000_DEV_ID_82572EI_SERDES 0x107F |
| 285 | #define E1000_DEV_ID_82572EI 0x10B9 |
| 286 | #define E1000_DEV_ID_82573E 0x108B |
| 287 | #define E1000_DEV_ID_82573E_IAMT 0x108C |
| 288 | #define E1000_DEV_ID_82573L 0x109A |
| 289 | #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 |
| 290 | #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 |
| 291 | #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 |
| 292 | #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA |
| 293 | #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB |
| 294 | |
| 295 | #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 |
| 296 | #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A |
| 297 | #define E1000_DEV_ID_ICH8_IGP_C 0x104B |
| 298 | #define E1000_DEV_ID_ICH8_IFE 0x104C |
| 299 | #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 |
| 300 | #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 |
| 301 | #define E1000_DEV_ID_ICH8_IGP_M 0x104D |
| 302 | |
| 303 | #define IGP03E1000_E_PHY_ID 0x02A80390 |
| 304 | #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ |
| 305 | #define IFE_PLUS_E_PHY_ID 0x02A80320 |
| 306 | #define IFE_C_E_PHY_ID 0x02A80310 |
| 307 | |
| 308 | #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, |
| 309 | Control and Address */ |
| 310 | #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special |
| 311 | control register */ |
| 312 | #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False |
| 313 | Carrier Counter */ |
| 314 | #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet |
| 315 | Counter */ |
| 316 | #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error |
| 317 | Frame Counter */ |
| 318 | #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error |
| 319 | Counter */ |
| 320 | #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive |
| 321 | Premature End Of Frame |
| 322 | Error Counter */ |
| 323 | #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of |
| 324 | Frame Error Counter */ |
| 325 | #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber |
| 326 | Detect Counter */ |
| 327 | #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and |
| 328 | Status */ |
| 329 | #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and |
| 330 | LED configuration */ |
| 331 | #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ |
| 332 | #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control |
| 333 | (HWI) */ |
| 334 | |
| 335 | #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto |
| 336 | reduced power down */ |
| 337 | #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power |
| 338 | state of 100BASE-TX */ |
| 339 | #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power |
| 340 | state of 10BASE-T */ |
| 341 | #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T |
| 342 | polarity */ |
| 343 | #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY |
| 344 | address */ |
| 345 | #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed |
| 346 | result 1=100Mbs, 0=10Mbs */ |
| 347 | #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation |
| 348 | duplex result 1=Full, 0=Half */ |
| 349 | #define IFE_PESC_POLARITY_REVERSED_SHIFT 8 |
| 350 | |
| 351 | #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down |
| 352 | disabled */ |
| 353 | #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, |
| 354 | 0=Normal */ |
| 355 | #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity |
| 356 | Disabled, 0=Enabled */ |
| 357 | #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, |
| 358 | 0=Normal Jabber Operation */ |
| 359 | #define IFE_PSC_FORCE_POLARITY_SHIFT 5 |
| 360 | #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 |
| 361 | |
| 362 | #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X |
| 363 | feature, default 0=disabled */ |
| 364 | #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, |
| 365 | 0=force MDI */ |
| 366 | #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ |
| 367 | #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm |
| 368 | is completed */ |
| 369 | #define IFE_PMC_MDIX_MODE_SHIFT 6 |
| 370 | #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ |
| 371 | |
| 372 | #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI |
| 373 | feature */ |
| 374 | #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, |
| 375 | 0=failed */ |
| 376 | #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses |
| 377 | on the wire */ |
| 378 | #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ |
| 379 | #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ |
| 380 | #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication |
| 381 | type of problem on the line */ |
| 382 | #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to |
| 383 | the cable problem, in 80cm granularity */ |
| 384 | #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ |
| 385 | #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ |
| 386 | #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 |
| 387 | off */ |
| 388 | #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ |
| 389 | |
| 390 | |
Paul Gortmaker | 7d13b8d | 2008-07-09 17:50:45 -0400 | [diff] [blame] | 391 | #define NUM_DEV_IDS 16 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 392 | |
| 393 | #define NODE_ADDRESS_SIZE 6 |
| 394 | #define ETH_LENGTH_OF_ADDRESS 6 |
| 395 | |
| 396 | /* MAC decode size is 128K - This is the size of BAR0 */ |
| 397 | #define MAC_DECODE_SIZE (128 * 1024) |
| 398 | |
| 399 | #define E1000_82542_2_0_REV_ID 2 |
| 400 | #define E1000_82542_2_1_REV_ID 3 |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 401 | #define E1000_REVISION_0 0 |
| 402 | #define E1000_REVISION_1 1 |
| 403 | #define E1000_REVISION_2 2 |
| 404 | #define E1000_REVISION_3 3 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 405 | |
| 406 | #define SPEED_10 10 |
| 407 | #define SPEED_100 100 |
| 408 | #define SPEED_1000 1000 |
| 409 | #define HALF_DUPLEX 1 |
| 410 | #define FULL_DUPLEX 2 |
| 411 | |
| 412 | /* The sizes (in bytes) of a ethernet packet */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 413 | #define ENET_HEADER_SIZE 14 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 414 | #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ |
| 415 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 416 | #define ETHERNET_FCS_SIZE 4 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 417 | #define MAXIMUM_ETHERNET_PACKET_SIZE \ |
| 418 | (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) |
| 419 | #define MINIMUM_ETHERNET_PACKET_SIZE \ |
| 420 | (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 421 | #define CRC_LENGTH ETHERNET_FCS_SIZE |
| 422 | #define MAX_JUMBO_FRAME_SIZE 0x3F00 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 423 | |
| 424 | /* 802.1q VLAN Packet Sizes */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 425 | #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 426 | |
| 427 | /* Ethertype field values */ |
| 428 | #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 429 | #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ |
| 430 | #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 431 | |
| 432 | /* Packet Header defines */ |
| 433 | #define IP_PROTOCOL_TCP 6 |
| 434 | #define IP_PROTOCOL_UDP 0x11 |
| 435 | |
| 436 | /* This defines the bits that are set in the Interrupt Mask |
| 437 | * Set/Read Register. Each bit is documented below: |
| 438 | * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 439 | * o RXSEQ = Receive Sequence Error |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 440 | */ |
| 441 | #define POLL_IMS_ENABLE_MASK ( \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 442 | E1000_IMS_RXDMT0 | \ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 443 | E1000_IMS_RXSEQ) |
| 444 | |
| 445 | /* This defines the bits that are set in the Interrupt Mask |
| 446 | * Set/Read Register. Each bit is documented below: |
| 447 | * o RXT0 = Receiver Timer Interrupt (ring 0) |
| 448 | * o TXDW = Transmit Descriptor Written Back |
| 449 | * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) |
| 450 | * o RXSEQ = Receive Sequence Error |
| 451 | * o LSC = Link Status Change |
| 452 | */ |
| 453 | #define IMS_ENABLE_MASK ( \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 454 | E1000_IMS_RXT0 | \ |
| 455 | E1000_IMS_TXDW | \ |
| 456 | E1000_IMS_RXDMT0 | \ |
| 457 | E1000_IMS_RXSEQ | \ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 458 | E1000_IMS_LSC) |
| 459 | |
| 460 | /* The number of high/low register pairs in the RAR. The RAR (Receive Address |
| 461 | * Registers) holds the directed and multicast addresses that we monitor. We |
| 462 | * reserve one of these spots for our directed address, allowing us room for |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 463 | * E1000_RAR_ENTRIES - 1 multicast addresses. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 464 | */ |
| 465 | #define E1000_RAR_ENTRIES 16 |
| 466 | |
| 467 | #define MIN_NUMBER_OF_DESCRIPTORS 8 |
| 468 | #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 |
| 469 | |
| 470 | /* Receive Descriptor */ |
| 471 | struct e1000_rx_desc { |
| 472 | uint64_t buffer_addr; /* Address of the descriptor's data buffer */ |
| 473 | uint16_t length; /* Length of data DMAed into data buffer */ |
| 474 | uint16_t csum; /* Packet checksum */ |
| 475 | uint8_t status; /* Descriptor status */ |
| 476 | uint8_t errors; /* Descriptor Errors */ |
| 477 | uint16_t special; |
| 478 | }; |
| 479 | |
| 480 | /* Receive Decriptor bit definitions */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 481 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
| 482 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ |
| 483 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ |
| 484 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
| 485 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
| 486 | #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ |
| 487 | #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ |
| 488 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ |
| 489 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ |
| 490 | #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ |
| 491 | #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ |
| 492 | #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ |
| 493 | #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ |
| 494 | #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 495 | #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 496 | #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 497 | #define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 498 | #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 499 | #define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ |
| 500 | |
| 501 | /* mask to determine if packets should be dropped due to frame errors */ |
| 502 | #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 503 | E1000_RXD_ERR_CE | \ |
| 504 | E1000_RXD_ERR_SE | \ |
| 505 | E1000_RXD_ERR_SEQ | \ |
| 506 | E1000_RXD_ERR_CXE | \ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 507 | E1000_RXD_ERR_RXE) |
| 508 | |
| 509 | /* Transmit Descriptor */ |
| 510 | struct e1000_tx_desc { |
| 511 | uint64_t buffer_addr; /* Address of the descriptor's data buffer */ |
| 512 | union { |
| 513 | uint32_t data; |
| 514 | struct { |
| 515 | uint16_t length; /* Data buffer length */ |
| 516 | uint8_t cso; /* Checksum offset */ |
| 517 | uint8_t cmd; /* Descriptor control */ |
| 518 | } flags; |
| 519 | } lower; |
| 520 | union { |
| 521 | uint32_t data; |
| 522 | struct { |
| 523 | uint8_t status; /* Descriptor status */ |
| 524 | uint8_t css; /* Checksum start */ |
| 525 | uint16_t special; |
| 526 | } fields; |
| 527 | } upper; |
| 528 | }; |
| 529 | |
| 530 | /* Transmit Descriptor bit definitions */ |
| 531 | #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ |
| 532 | #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ |
| 533 | #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ |
| 534 | #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ |
| 535 | #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ |
| 536 | #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ |
| 537 | #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ |
| 538 | #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ |
| 539 | #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ |
| 540 | #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ |
| 541 | #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ |
| 542 | #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ |
| 543 | #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ |
| 544 | #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ |
| 545 | #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ |
| 546 | #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ |
| 547 | #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ |
| 548 | #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ |
| 549 | #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ |
| 550 | #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ |
| 551 | |
| 552 | /* Offload Context Descriptor */ |
| 553 | struct e1000_context_desc { |
| 554 | union { |
| 555 | uint32_t ip_config; |
| 556 | struct { |
| 557 | uint8_t ipcss; /* IP checksum start */ |
| 558 | uint8_t ipcso; /* IP checksum offset */ |
| 559 | uint16_t ipcse; /* IP checksum end */ |
| 560 | } ip_fields; |
| 561 | } lower_setup; |
| 562 | union { |
| 563 | uint32_t tcp_config; |
| 564 | struct { |
| 565 | uint8_t tucss; /* TCP checksum start */ |
| 566 | uint8_t tucso; /* TCP checksum offset */ |
| 567 | uint16_t tucse; /* TCP checksum end */ |
| 568 | } tcp_fields; |
| 569 | } upper_setup; |
| 570 | uint32_t cmd_and_length; /* */ |
| 571 | union { |
| 572 | uint32_t data; |
| 573 | struct { |
| 574 | uint8_t status; /* Descriptor status */ |
| 575 | uint8_t hdr_len; /* Header length */ |
| 576 | uint16_t mss; /* Maximum segment size */ |
| 577 | } fields; |
| 578 | } tcp_seg_setup; |
| 579 | }; |
| 580 | |
| 581 | /* Offload data descriptor */ |
| 582 | struct e1000_data_desc { |
| 583 | uint64_t buffer_addr; /* Address of the descriptor's buffer address */ |
| 584 | union { |
| 585 | uint32_t data; |
| 586 | struct { |
| 587 | uint16_t length; /* Data buffer length */ |
| 588 | uint8_t typ_len_ext; /* */ |
| 589 | uint8_t cmd; /* */ |
| 590 | } flags; |
| 591 | } lower; |
| 592 | union { |
| 593 | uint32_t data; |
| 594 | struct { |
| 595 | uint8_t status; /* Descriptor status */ |
| 596 | uint8_t popts; /* Packet Options */ |
| 597 | uint16_t special; /* */ |
| 598 | } fields; |
| 599 | } upper; |
| 600 | }; |
| 601 | |
| 602 | /* Filters */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 603 | #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ |
| 604 | #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 605 | #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ |
| 606 | |
| 607 | /* Receive Address Register */ |
| 608 | struct e1000_rar { |
| 609 | volatile uint32_t low; /* receive address low */ |
| 610 | volatile uint32_t high; /* receive address high */ |
| 611 | }; |
| 612 | |
| 613 | /* The number of entries in the Multicast Table Array (MTA). */ |
| 614 | #define E1000_NUM_MTA_REGISTERS 128 |
| 615 | |
| 616 | /* IPv4 Address Table Entry */ |
| 617 | struct e1000_ipv4_at_entry { |
| 618 | volatile uint32_t ipv4_addr; /* IP Address (RW) */ |
| 619 | volatile uint32_t reserved; |
| 620 | }; |
| 621 | |
| 622 | /* Four wakeup IP addresses are supported */ |
| 623 | #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 624 | #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX |
| 625 | #define E1000_IP6AT_SIZE 1 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 626 | |
| 627 | /* IPv6 Address Table Entry */ |
| 628 | struct e1000_ipv6_at_entry { |
| 629 | volatile uint8_t ipv6_addr[16]; |
| 630 | }; |
| 631 | |
| 632 | /* Flexible Filter Length Table Entry */ |
| 633 | struct e1000_fflt_entry { |
| 634 | volatile uint32_t length; /* Flexible Filter Length (RW) */ |
| 635 | volatile uint32_t reserved; |
| 636 | }; |
| 637 | |
| 638 | /* Flexible Filter Mask Table Entry */ |
| 639 | struct e1000_ffmt_entry { |
| 640 | volatile uint32_t mask; /* Flexible Filter Mask (RW) */ |
| 641 | volatile uint32_t reserved; |
| 642 | }; |
| 643 | |
| 644 | /* Flexible Filter Value Table Entry */ |
| 645 | struct e1000_ffvt_entry { |
| 646 | volatile uint32_t value; /* Flexible Filter Value (RW) */ |
| 647 | volatile uint32_t reserved; |
| 648 | }; |
| 649 | |
| 650 | /* Four Flexible Filters are supported */ |
| 651 | #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 |
| 652 | |
| 653 | /* Each Flexible Filter is at most 128 (0x80) bytes in length */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 654 | #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 655 | |
| 656 | #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX |
| 657 | #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX |
| 658 | #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX |
| 659 | |
| 660 | /* Register Set. (82543, 82544) |
| 661 | * |
| 662 | * Registers are defined to be 32 bits and should be accessed as 32 bit values. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 663 | * These registers are physically located on the NIC, but are mapped into the |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 664 | * host memory address space. |
| 665 | * |
| 666 | * RW - register is both readable and writable |
| 667 | * RO - register is read only |
| 668 | * WO - register is write only |
| 669 | * R/clr - register is read only and is cleared when read |
| 670 | * A - register array |
| 671 | */ |
| 672 | #define E1000_CTRL 0x00000 /* Device Control - RW */ |
| 673 | #define E1000_STATUS 0x00008 /* Device Status - RO */ |
| 674 | #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ |
| 675 | #define E1000_EERD 0x00014 /* EEPROM Read - RW */ |
| 676 | #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ |
| 677 | #define E1000_MDIC 0x00020 /* MDI Control - RW */ |
| 678 | #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ |
| 679 | #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ |
| 680 | #define E1000_FCT 0x00030 /* Flow Control Type - RW */ |
| 681 | #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ |
| 682 | #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ |
| 683 | #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ |
| 684 | #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ |
| 685 | #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ |
| 686 | #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ |
| 687 | #define E1000_RCTL 0x00100 /* RX Control - RW */ |
| 688 | #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ |
| 689 | #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ |
| 690 | #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ |
| 691 | #define E1000_TCTL 0x00400 /* TX Control - RW */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 692 | #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 693 | #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ |
| 694 | #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ |
| 695 | #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ |
| 696 | #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 697 | #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ |
| 698 | #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ |
| 699 | #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ |
| 700 | #define FEXTNVM_SW_CONFIG 0x0001 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 701 | #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 702 | #define E1000_PBS 0x01008 /* Packet Buffer Size */ |
| 703 | #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ |
| 704 | #define E1000_FLASH_UPDATES 1000 |
| 705 | #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ |
| 706 | #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ |
| 707 | #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ |
| 708 | #define E1000_FLSWCTL 0x01030 /* FLASH control register */ |
| 709 | #define E1000_FLSWDATA 0x01034 /* FLASH data register */ |
| 710 | #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ |
| 711 | #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ |
| 712 | #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 713 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ |
| 714 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ |
| 715 | #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ |
| 716 | #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ |
| 717 | #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ |
| 718 | #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ |
| 719 | #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ |
| 720 | #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ |
| 721 | #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ |
| 722 | #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ |
| 723 | #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ |
| 724 | #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 725 | #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ |
| 726 | #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ |
| 727 | #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ |
| 728 | #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ |
| 729 | #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 730 | #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ |
| 731 | #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ |
| 732 | #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ |
| 733 | #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ |
| 734 | #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ |
| 735 | #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ |
| 736 | #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ |
| 737 | #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ |
| 738 | #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 739 | #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ |
| 740 | #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ |
| 741 | #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ |
| 742 | #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ |
| 743 | #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ |
| 744 | #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ |
| 745 | #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ |
| 746 | #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 747 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ |
| 748 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ |
| 749 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ |
| 750 | #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ |
| 751 | #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ |
| 752 | #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ |
| 753 | #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ |
| 754 | #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ |
| 755 | #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ |
| 756 | #define E1000_COLC 0x04028 /* Collision Count - R/clr */ |
| 757 | #define E1000_DC 0x04030 /* Defer Count - R/clr */ |
| 758 | #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ |
| 759 | #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ |
| 760 | #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ |
| 761 | #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ |
| 762 | #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ |
| 763 | #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ |
| 764 | #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ |
| 765 | #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ |
| 766 | #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ |
| 767 | #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ |
| 768 | #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ |
| 769 | #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ |
| 770 | #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ |
| 771 | #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ |
| 772 | #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ |
| 773 | #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ |
| 774 | #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ |
| 775 | #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ |
| 776 | #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ |
| 777 | #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ |
| 778 | #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ |
| 779 | #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ |
| 780 | #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ |
| 781 | #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ |
| 782 | #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ |
| 783 | #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ |
| 784 | #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ |
| 785 | #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ |
| 786 | #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ |
| 787 | #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ |
| 788 | #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ |
| 789 | #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ |
| 790 | #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ |
| 791 | #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ |
| 792 | #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ |
| 793 | #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ |
| 794 | #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ |
| 795 | #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ |
| 796 | #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ |
| 797 | #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ |
| 798 | #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ |
| 799 | #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ |
| 800 | #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ |
| 801 | #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ |
| 802 | #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ |
| 803 | #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ |
| 804 | #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ |
| 805 | #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ |
| 806 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ |
| 807 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ |
| 808 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ |
| 809 | #define E1000_WUC 0x05800 /* Wakeup Control - RW */ |
| 810 | #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ |
| 811 | #define E1000_WUS 0x05810 /* Wakeup Status - RO */ |
| 812 | #define E1000_MANC 0x05820 /* Management Control - RW */ |
| 813 | #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ |
| 814 | #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ |
| 815 | #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ |
| 816 | #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ |
| 817 | #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ |
| 818 | #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ |
| 819 | #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ |
| 820 | #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ |
| 821 | |
| 822 | /* Register Set (82542) |
| 823 | * |
| 824 | * Some of the 82542 registers are located at different offsets than they are |
| 825 | * in more current versions of the 8254x. Despite the difference in location, |
| 826 | * the registers function in the same manner. |
| 827 | */ |
| 828 | #define E1000_82542_CTRL E1000_CTRL |
| 829 | #define E1000_82542_STATUS E1000_STATUS |
| 830 | #define E1000_82542_EECD E1000_EECD |
| 831 | #define E1000_82542_EERD E1000_EERD |
| 832 | #define E1000_82542_CTRL_EXT E1000_CTRL_EXT |
| 833 | #define E1000_82542_MDIC E1000_MDIC |
| 834 | #define E1000_82542_FCAL E1000_FCAL |
| 835 | #define E1000_82542_FCAH E1000_FCAH |
| 836 | #define E1000_82542_FCT E1000_FCT |
| 837 | #define E1000_82542_VET E1000_VET |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 838 | #define E1000_82542_RA 0x00040 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 839 | #define E1000_82542_ICR E1000_ICR |
| 840 | #define E1000_82542_ITR E1000_ITR |
| 841 | #define E1000_82542_ICS E1000_ICS |
| 842 | #define E1000_82542_IMS E1000_IMS |
| 843 | #define E1000_82542_IMC E1000_IMC |
| 844 | #define E1000_82542_RCTL E1000_RCTL |
| 845 | #define E1000_82542_RDTR 0x00108 |
| 846 | #define E1000_82542_RDBAL 0x00110 |
| 847 | #define E1000_82542_RDBAH 0x00114 |
| 848 | #define E1000_82542_RDLEN 0x00118 |
| 849 | #define E1000_82542_RDH 0x00120 |
| 850 | #define E1000_82542_RDT 0x00128 |
| 851 | #define E1000_82542_FCRTH 0x00160 |
| 852 | #define E1000_82542_FCRTL 0x00168 |
| 853 | #define E1000_82542_FCTTV E1000_FCTTV |
| 854 | #define E1000_82542_TXCW E1000_TXCW |
| 855 | #define E1000_82542_RXCW E1000_RXCW |
| 856 | #define E1000_82542_MTA 0x00200 |
| 857 | #define E1000_82542_TCTL E1000_TCTL |
| 858 | #define E1000_82542_TIPG E1000_TIPG |
| 859 | #define E1000_82542_TDBAL 0x00420 |
| 860 | #define E1000_82542_TDBAH 0x00424 |
| 861 | #define E1000_82542_TDLEN 0x00428 |
| 862 | #define E1000_82542_TDH 0x00430 |
| 863 | #define E1000_82542_TDT 0x00438 |
| 864 | #define E1000_82542_TIDV 0x00440 |
| 865 | #define E1000_82542_TBT E1000_TBT |
| 866 | #define E1000_82542_AIT E1000_AIT |
| 867 | #define E1000_82542_VFTA 0x00600 |
| 868 | #define E1000_82542_LEDCTL E1000_LEDCTL |
| 869 | #define E1000_82542_PBA E1000_PBA |
| 870 | #define E1000_82542_RXDCTL E1000_RXDCTL |
| 871 | #define E1000_82542_RADV E1000_RADV |
| 872 | #define E1000_82542_RSRPD E1000_RSRPD |
| 873 | #define E1000_82542_TXDMAC E1000_TXDMAC |
| 874 | #define E1000_82542_TXDCTL E1000_TXDCTL |
| 875 | #define E1000_82542_TADV E1000_TADV |
| 876 | #define E1000_82542_TSPMT E1000_TSPMT |
| 877 | #define E1000_82542_CRCERRS E1000_CRCERRS |
| 878 | #define E1000_82542_ALGNERRC E1000_ALGNERRC |
| 879 | #define E1000_82542_SYMERRS E1000_SYMERRS |
| 880 | #define E1000_82542_RXERRC E1000_RXERRC |
| 881 | #define E1000_82542_MPC E1000_MPC |
| 882 | #define E1000_82542_SCC E1000_SCC |
| 883 | #define E1000_82542_ECOL E1000_ECOL |
| 884 | #define E1000_82542_MCC E1000_MCC |
| 885 | #define E1000_82542_LATECOL E1000_LATECOL |
| 886 | #define E1000_82542_COLC E1000_COLC |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 887 | #define E1000_82542_DC E1000_DC |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 888 | #define E1000_82542_TNCRS E1000_TNCRS |
| 889 | #define E1000_82542_SEC E1000_SEC |
| 890 | #define E1000_82542_CEXTERR E1000_CEXTERR |
| 891 | #define E1000_82542_RLEC E1000_RLEC |
| 892 | #define E1000_82542_XONRXC E1000_XONRXC |
| 893 | #define E1000_82542_XONTXC E1000_XONTXC |
| 894 | #define E1000_82542_XOFFRXC E1000_XOFFRXC |
| 895 | #define E1000_82542_XOFFTXC E1000_XOFFTXC |
| 896 | #define E1000_82542_FCRUC E1000_FCRUC |
| 897 | #define E1000_82542_PRC64 E1000_PRC64 |
| 898 | #define E1000_82542_PRC127 E1000_PRC127 |
| 899 | #define E1000_82542_PRC255 E1000_PRC255 |
| 900 | #define E1000_82542_PRC511 E1000_PRC511 |
| 901 | #define E1000_82542_PRC1023 E1000_PRC1023 |
| 902 | #define E1000_82542_PRC1522 E1000_PRC1522 |
| 903 | #define E1000_82542_GPRC E1000_GPRC |
| 904 | #define E1000_82542_BPRC E1000_BPRC |
| 905 | #define E1000_82542_MPRC E1000_MPRC |
| 906 | #define E1000_82542_GPTC E1000_GPTC |
| 907 | #define E1000_82542_GORCL E1000_GORCL |
| 908 | #define E1000_82542_GORCH E1000_GORCH |
| 909 | #define E1000_82542_GOTCL E1000_GOTCL |
| 910 | #define E1000_82542_GOTCH E1000_GOTCH |
| 911 | #define E1000_82542_RNBC E1000_RNBC |
| 912 | #define E1000_82542_RUC E1000_RUC |
| 913 | #define E1000_82542_RFC E1000_RFC |
| 914 | #define E1000_82542_ROC E1000_ROC |
| 915 | #define E1000_82542_RJC E1000_RJC |
| 916 | #define E1000_82542_MGTPRC E1000_MGTPRC |
| 917 | #define E1000_82542_MGTPDC E1000_MGTPDC |
| 918 | #define E1000_82542_MGTPTC E1000_MGTPTC |
| 919 | #define E1000_82542_TORL E1000_TORL |
| 920 | #define E1000_82542_TORH E1000_TORH |
| 921 | #define E1000_82542_TOTL E1000_TOTL |
| 922 | #define E1000_82542_TOTH E1000_TOTH |
| 923 | #define E1000_82542_TPR E1000_TPR |
| 924 | #define E1000_82542_TPT E1000_TPT |
| 925 | #define E1000_82542_PTC64 E1000_PTC64 |
| 926 | #define E1000_82542_PTC127 E1000_PTC127 |
| 927 | #define E1000_82542_PTC255 E1000_PTC255 |
| 928 | #define E1000_82542_PTC511 E1000_PTC511 |
| 929 | #define E1000_82542_PTC1023 E1000_PTC1023 |
| 930 | #define E1000_82542_PTC1522 E1000_PTC1522 |
| 931 | #define E1000_82542_MPTC E1000_MPTC |
| 932 | #define E1000_82542_BPTC E1000_BPTC |
| 933 | #define E1000_82542_TSCTC E1000_TSCTC |
| 934 | #define E1000_82542_TSCTFC E1000_TSCTFC |
| 935 | #define E1000_82542_RXCSUM E1000_RXCSUM |
| 936 | #define E1000_82542_WUC E1000_WUC |
| 937 | #define E1000_82542_WUFC E1000_WUFC |
| 938 | #define E1000_82542_WUS E1000_WUS |
| 939 | #define E1000_82542_MANC E1000_MANC |
| 940 | #define E1000_82542_IPAV E1000_IPAV |
| 941 | #define E1000_82542_IP4AT E1000_IP4AT |
| 942 | #define E1000_82542_IP6AT E1000_IP6AT |
| 943 | #define E1000_82542_WUPL E1000_WUPL |
| 944 | #define E1000_82542_WUPM E1000_WUPM |
| 945 | #define E1000_82542_FFLT E1000_FFLT |
| 946 | #define E1000_82542_FFMT E1000_FFMT |
| 947 | #define E1000_82542_FFVT E1000_FFVT |
| 948 | |
| 949 | /* Statistics counters collected by the MAC */ |
| 950 | struct e1000_hw_stats { |
| 951 | uint64_t crcerrs; |
| 952 | uint64_t algnerrc; |
| 953 | uint64_t symerrs; |
| 954 | uint64_t rxerrc; |
| 955 | uint64_t mpc; |
| 956 | uint64_t scc; |
| 957 | uint64_t ecol; |
| 958 | uint64_t mcc; |
| 959 | uint64_t latecol; |
| 960 | uint64_t colc; |
| 961 | uint64_t dc; |
| 962 | uint64_t tncrs; |
| 963 | uint64_t sec; |
| 964 | uint64_t cexterr; |
| 965 | uint64_t rlec; |
| 966 | uint64_t xonrxc; |
| 967 | uint64_t xontxc; |
| 968 | uint64_t xoffrxc; |
| 969 | uint64_t xofftxc; |
| 970 | uint64_t fcruc; |
| 971 | uint64_t prc64; |
| 972 | uint64_t prc127; |
| 973 | uint64_t prc255; |
| 974 | uint64_t prc511; |
| 975 | uint64_t prc1023; |
| 976 | uint64_t prc1522; |
| 977 | uint64_t gprc; |
| 978 | uint64_t bprc; |
| 979 | uint64_t mprc; |
| 980 | uint64_t gptc; |
| 981 | uint64_t gorcl; |
| 982 | uint64_t gorch; |
| 983 | uint64_t gotcl; |
| 984 | uint64_t gotch; |
| 985 | uint64_t rnbc; |
| 986 | uint64_t ruc; |
| 987 | uint64_t rfc; |
| 988 | uint64_t roc; |
| 989 | uint64_t rjc; |
| 990 | uint64_t mgprc; |
| 991 | uint64_t mgpdc; |
| 992 | uint64_t mgptc; |
| 993 | uint64_t torl; |
| 994 | uint64_t torh; |
| 995 | uint64_t totl; |
| 996 | uint64_t toth; |
| 997 | uint64_t tpr; |
| 998 | uint64_t tpt; |
| 999 | uint64_t ptc64; |
| 1000 | uint64_t ptc127; |
| 1001 | uint64_t ptc255; |
| 1002 | uint64_t ptc511; |
| 1003 | uint64_t ptc1023; |
| 1004 | uint64_t ptc1522; |
| 1005 | uint64_t mptc; |
| 1006 | uint64_t bptc; |
| 1007 | uint64_t tsctc; |
| 1008 | uint64_t tsctfc; |
| 1009 | }; |
| 1010 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1011 | struct e1000_eeprom_info { |
| 1012 | e1000_eeprom_type type; |
| 1013 | uint16_t word_size; |
| 1014 | uint16_t opcode_bits; |
| 1015 | uint16_t address_bits; |
| 1016 | uint16_t delay_usec; |
| 1017 | uint16_t page_size; |
| 1018 | boolean_t use_eerd; |
| 1019 | boolean_t use_eewr; |
| 1020 | }; |
| 1021 | |
| 1022 | typedef enum { |
| 1023 | e1000_smart_speed_default = 0, |
| 1024 | e1000_smart_speed_on, |
| 1025 | e1000_smart_speed_off |
| 1026 | } e1000_smart_speed; |
| 1027 | |
| 1028 | typedef enum { |
| 1029 | e1000_dsp_config_disabled = 0, |
| 1030 | e1000_dsp_config_enabled, |
| 1031 | e1000_dsp_config_activated, |
| 1032 | e1000_dsp_config_undefined = 0xFF |
| 1033 | } e1000_dsp_config; |
| 1034 | |
| 1035 | typedef enum { |
| 1036 | e1000_ms_hw_default = 0, |
| 1037 | e1000_ms_force_master, |
| 1038 | e1000_ms_force_slave, |
| 1039 | e1000_ms_auto |
| 1040 | } e1000_ms_type; |
| 1041 | |
| 1042 | typedef enum { |
| 1043 | e1000_ffe_config_enabled = 0, |
| 1044 | e1000_ffe_config_active, |
| 1045 | e1000_ffe_config_blocked |
| 1046 | } e1000_ffe_config; |
| 1047 | |
| 1048 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1049 | /* Structure containing variables used by the shared code (e1000_hw.c) */ |
| 1050 | struct e1000_hw { |
| 1051 | pci_dev_t pdev; |
| 1052 | uint8_t *hw_addr; |
| 1053 | e1000_mac_type mac_type; |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 1054 | e1000_phy_type phy_type; |
| 1055 | uint32_t phy_init_script; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1056 | uint32_t txd_cmd; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1057 | e1000_media_type media_type; |
| 1058 | e1000_lan_loc lan_loc; |
| 1059 | e1000_fc_type fc; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1060 | e1000_bus_type bus_type; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1061 | #if 0 |
| 1062 | e1000_bus_speed bus_speed; |
| 1063 | e1000_bus_width bus_width; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1064 | uint32_t io_base; |
| 1065 | #endif |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1066 | uint32_t asf_firmware_present; |
| 1067 | uint32_t eeprom_semaphore_present; |
| 1068 | uint32_t swfw_sync_present; |
| 1069 | uint32_t swfwhw_semaphore_present; |
| 1070 | struct e1000_eeprom_info eeprom; |
| 1071 | e1000_ms_type master_slave; |
| 1072 | e1000_ms_type original_master_slave; |
| 1073 | e1000_ffe_config ffe_config_state; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1074 | uint32_t phy_id; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1075 | uint32_t phy_revision; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1076 | uint32_t phy_addr; |
| 1077 | uint32_t original_fc; |
| 1078 | uint32_t txcw; |
| 1079 | uint32_t autoneg_failed; |
| 1080 | #if 0 |
| 1081 | uint32_t max_frame_size; |
| 1082 | uint32_t min_frame_size; |
| 1083 | uint32_t mc_filter_type; |
| 1084 | uint32_t num_mc_addrs; |
| 1085 | uint32_t collision_delta; |
| 1086 | uint32_t tx_packet_delta; |
| 1087 | uint32_t ledctl_default; |
| 1088 | uint32_t ledctl_mode1; |
| 1089 | uint32_t ledctl_mode2; |
| 1090 | #endif |
| 1091 | uint16_t autoneg_advertised; |
| 1092 | uint16_t pci_cmd_word; |
| 1093 | uint16_t fc_high_water; |
| 1094 | uint16_t fc_low_water; |
| 1095 | uint16_t fc_pause_time; |
| 1096 | #if 0 |
| 1097 | uint16_t current_ifs_val; |
| 1098 | uint16_t ifs_min_val; |
| 1099 | uint16_t ifs_max_val; |
| 1100 | uint16_t ifs_step_size; |
| 1101 | uint16_t ifs_ratio; |
| 1102 | #endif |
| 1103 | uint16_t device_id; |
| 1104 | uint16_t vendor_id; |
| 1105 | uint16_t subsystem_id; |
| 1106 | uint16_t subsystem_vendor_id; |
| 1107 | uint8_t revision_id; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1108 | uint8_t autoneg; |
| 1109 | uint8_t mdix; |
| 1110 | uint8_t forced_speed_duplex; |
| 1111 | uint8_t wait_autoneg_complete; |
| 1112 | uint8_t dma_fairness; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1113 | #if 0 |
| 1114 | uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1115 | #endif |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1116 | boolean_t disable_polarity_correction; |
| 1117 | boolean_t speed_downgraded; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1118 | boolean_t get_link_status; |
| 1119 | boolean_t tbi_compatibility_en; |
| 1120 | boolean_t tbi_compatibility_on; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1121 | boolean_t fc_strict_ieee; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1122 | boolean_t fc_send_xon; |
| 1123 | boolean_t report_tx_early; |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1124 | boolean_t phy_reset_disable; |
| 1125 | boolean_t initialize_hw_bits_disable; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1126 | #if 0 |
| 1127 | boolean_t adaptive_ifs; |
| 1128 | boolean_t ifs_params_forced; |
| 1129 | boolean_t in_ifs_mode; |
| 1130 | #endif |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1131 | e1000_smart_speed smart_speed; |
| 1132 | e1000_dsp_config dsp_config_state; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1133 | }; |
| 1134 | |
| 1135 | #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ |
| 1136 | #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1137 | #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM |
| 1138 | read/write registers */ |
| 1139 | #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ |
| 1140 | #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start |
| 1141 | operation */ |
| 1142 | #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ |
| 1143 | #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write |
| 1144 | complete */ |
| 1145 | #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ |
| 1146 | #define EEPROM_RESERVED_WORD 0xFFFF |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1147 | |
| 1148 | /* Register Bit Masks */ |
| 1149 | /* Device Control */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1150 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ |
| 1151 | #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1152 | #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ |
| 1153 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1154 | #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ |
| 1155 | #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1156 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1157 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1158 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ |
| 1159 | #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ |
| 1160 | #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ |
| 1161 | #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ |
| 1162 | #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ |
| 1163 | #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ |
| 1164 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ |
| 1165 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ |
| 1166 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ |
| 1167 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ |
| 1168 | #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ |
| 1169 | #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ |
| 1170 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ |
| 1171 | #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ |
| 1172 | #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ |
| 1173 | #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1174 | #define E1000_CTRL_RST 0x04000000 /* Global reset */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1175 | #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ |
| 1176 | #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1177 | #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ |
| 1178 | #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1179 | #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ |
| 1180 | |
| 1181 | /* Device Status */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1182 | #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ |
| 1183 | #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ |
| 1184 | #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ |
| 1185 | #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ |
| 1186 | #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ |
| 1187 | #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ |
| 1188 | #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1189 | #define E1000_STATUS_SPEED_MASK 0x000000C0 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1190 | #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ |
| 1191 | #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1192 | #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1193 | #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ |
| 1194 | #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ |
| 1195 | #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ |
| 1196 | #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ |
| 1197 | #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1198 | #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ |
| 1199 | |
| 1200 | /* Constants used to intrepret the masked PCI-X bus speed. */ |
| 1201 | #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ |
| 1202 | #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ |
| 1203 | #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ |
| 1204 | |
| 1205 | /* EEPROM/Flash Control */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1206 | #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ |
| 1207 | #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ |
| 1208 | #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ |
| 1209 | #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1210 | #define E1000_EECD_FWE_MASK 0x00000030 |
| 1211 | #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ |
| 1212 | #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ |
| 1213 | #define E1000_EECD_FWE_SHIFT 4 |
| 1214 | #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1215 | #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ |
| 1216 | #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1217 | #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1218 | #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type |
| 1219 | * (0-small, 1-large) */ |
| 1220 | |
| 1221 | #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ |
| 1222 | #ifndef E1000_EEPROM_GRANT_ATTEMPTS |
| 1223 | #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ |
| 1224 | #endif |
| 1225 | #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ |
| 1226 | #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ |
| 1227 | #define E1000_EECD_SIZE_EX_SHIFT 11 |
| 1228 | #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ |
| 1229 | #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ |
| 1230 | #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ |
| 1231 | #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ |
| 1232 | #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ |
| 1233 | #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ |
| 1234 | #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ |
| 1235 | #define E1000_EECD_SECVAL_SHIFT 22 |
| 1236 | #define E1000_STM_OPCODE 0xDB00 |
| 1237 | #define E1000_HICR_FW_RESET 0xC0 |
| 1238 | |
| 1239 | #define E1000_SHADOW_RAM_WORDS 2048 |
| 1240 | #define E1000_ICH_NVM_SIG_WORD 0x13 |
| 1241 | #define E1000_ICH_NVM_SIG_MASK 0xC0 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1242 | |
| 1243 | /* EEPROM Read */ |
| 1244 | #define E1000_EERD_START 0x00000001 /* Start Read */ |
| 1245 | #define E1000_EERD_DONE 0x00000010 /* Read Done */ |
| 1246 | #define E1000_EERD_ADDR_SHIFT 8 |
| 1247 | #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ |
| 1248 | #define E1000_EERD_DATA_SHIFT 16 |
| 1249 | #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ |
| 1250 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1251 | /* EEPROM Commands - Microwire */ |
| 1252 | #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ |
| 1253 | #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ |
| 1254 | #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ |
| 1255 | #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ |
| 1256 | #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ |
| 1257 | |
| 1258 | /* EEPROM Commands - SPI */ |
| 1259 | #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ |
| 1260 | #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ |
| 1261 | #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ |
| 1262 | #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ |
| 1263 | #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ |
| 1264 | #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ |
| 1265 | #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ |
| 1266 | #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ |
| 1267 | #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ |
| 1268 | #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ |
| 1269 | #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ |
| 1270 | |
| 1271 | /* EEPROM Size definitions */ |
| 1272 | #define EEPROM_WORD_SIZE_SHIFT 6 |
| 1273 | #define EEPROM_SIZE_SHIFT 10 |
| 1274 | #define EEPROM_SIZE_MASK 0x1C00 |
| 1275 | |
| 1276 | /* EEPROM Word Offsets */ |
| 1277 | #define EEPROM_COMPAT 0x0003 |
| 1278 | #define EEPROM_ID_LED_SETTINGS 0x0004 |
| 1279 | #define EEPROM_VERSION 0x0005 |
| 1280 | #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude |
| 1281 | adjustment. */ |
| 1282 | #define EEPROM_PHY_CLASS_WORD 0x0007 |
| 1283 | #define EEPROM_INIT_CONTROL1_REG 0x000A |
| 1284 | #define EEPROM_INIT_CONTROL2_REG 0x000F |
| 1285 | #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 |
| 1286 | #define EEPROM_INIT_CONTROL3_PORT_B 0x0014 |
| 1287 | #define EEPROM_INIT_3GIO_3 0x001A |
| 1288 | #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 |
| 1289 | #define EEPROM_INIT_CONTROL3_PORT_A 0x0024 |
| 1290 | #define EEPROM_CFG 0x0012 |
| 1291 | #define EEPROM_FLASH_VERSION 0x0032 |
| 1292 | #define EEPROM_CHECKSUM_REG 0x003F |
| 1293 | |
| 1294 | #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ |
| 1295 | #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ |
| 1296 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1297 | /* Extended Device Control */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1298 | #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ |
| 1299 | #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1300 | #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1301 | #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ |
| 1302 | #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1303 | #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable |
| 1304 | Pin 4 */ |
| 1305 | #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable |
| 1306 | Pin 5 */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1307 | #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1308 | #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1309 | #define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1310 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1311 | #define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1312 | #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ |
| 1313 | #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ |
| 1314 | #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1315 | #define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1316 | #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1317 | #define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */ |
| 1318 | #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ |
| 1319 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ |
| 1320 | #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1321 | #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1322 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1323 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
| 1324 | #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 |
| 1325 | #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 |
| 1326 | #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 |
| 1327 | #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 |
| 1328 | #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 |
| 1329 | #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 |
| 1330 | #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 |
| 1331 | |
| 1332 | /* MDI Control */ |
| 1333 | #define E1000_MDIC_DATA_MASK 0x0000FFFF |
| 1334 | #define E1000_MDIC_REG_MASK 0x001F0000 |
| 1335 | #define E1000_MDIC_REG_SHIFT 16 |
| 1336 | #define E1000_MDIC_PHY_MASK 0x03E00000 |
| 1337 | #define E1000_MDIC_PHY_SHIFT 21 |
| 1338 | #define E1000_MDIC_OP_WRITE 0x04000000 |
| 1339 | #define E1000_MDIC_OP_READ 0x08000000 |
| 1340 | #define E1000_MDIC_READY 0x10000000 |
| 1341 | #define E1000_MDIC_INT_EN 0x20000000 |
| 1342 | #define E1000_MDIC_ERROR 0x40000000 |
| 1343 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1344 | #define E1000_PHY_CTRL_SPD_EN 0x00000001 |
| 1345 | #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 |
| 1346 | #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 |
| 1347 | #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 |
| 1348 | #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 |
| 1349 | #define E1000_PHY_CTRL_B2B_EN 0x00000080 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1350 | /* LED Control */ |
| 1351 | #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F |
| 1352 | #define E1000_LEDCTL_LED0_MODE_SHIFT 0 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1353 | #define E1000_LEDCTL_LED0_IVRT 0x00000040 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1354 | #define E1000_LEDCTL_LED0_BLINK 0x00000080 |
| 1355 | #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 |
| 1356 | #define E1000_LEDCTL_LED1_MODE_SHIFT 8 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1357 | #define E1000_LEDCTL_LED1_IVRT 0x00004000 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1358 | #define E1000_LEDCTL_LED1_BLINK 0x00008000 |
| 1359 | #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 |
| 1360 | #define E1000_LEDCTL_LED2_MODE_SHIFT 16 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1361 | #define E1000_LEDCTL_LED2_IVRT 0x00400000 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1362 | #define E1000_LEDCTL_LED2_BLINK 0x00800000 |
| 1363 | #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 |
| 1364 | #define E1000_LEDCTL_LED3_MODE_SHIFT 24 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1365 | #define E1000_LEDCTL_LED3_IVRT 0x40000000 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1366 | #define E1000_LEDCTL_LED3_BLINK 0x80000000 |
| 1367 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1368 | #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1369 | #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1370 | #define E1000_LEDCTL_MODE_LINK_UP 0x2 |
| 1371 | #define E1000_LEDCTL_MODE_ACTIVITY 0x3 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1372 | #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1373 | #define E1000_LEDCTL_MODE_LINK_10 0x5 |
| 1374 | #define E1000_LEDCTL_MODE_LINK_100 0x6 |
| 1375 | #define E1000_LEDCTL_MODE_LINK_1000 0x7 |
| 1376 | #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 |
| 1377 | #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 |
| 1378 | #define E1000_LEDCTL_MODE_COLLISION 0xA |
| 1379 | #define E1000_LEDCTL_MODE_BUS_SPEED 0xB |
| 1380 | #define E1000_LEDCTL_MODE_BUS_SIZE 0xC |
| 1381 | #define E1000_LEDCTL_MODE_PAUSED 0xD |
| 1382 | #define E1000_LEDCTL_MODE_LED_ON 0xE |
| 1383 | #define E1000_LEDCTL_MODE_LED_OFF 0xF |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1384 | |
| 1385 | /* Receive Address */ |
| 1386 | #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ |
| 1387 | |
| 1388 | /* Interrupt Cause Read */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1389 | #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ |
| 1390 | #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ |
| 1391 | #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1392 | #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ |
| 1393 | #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1394 | #define E1000_ICR_RXO 0x00000040 /* rx overrun */ |
| 1395 | #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ |
| 1396 | #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1397 | #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ |
| 1398 | #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ |
| 1399 | #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ |
| 1400 | #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ |
| 1401 | #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ |
| 1402 | #define E1000_ICR_TXD_LOW 0x00008000 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1403 | #define E1000_ICR_SRPD 0x00010000 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1404 | |
| 1405 | /* Interrupt Cause Set */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1406 | #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
| 1407 | #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ |
| 1408 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1409 | #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ |
| 1410 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1411 | #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ |
| 1412 | #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ |
| 1413 | #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1414 | #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ |
| 1415 | #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ |
| 1416 | #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ |
| 1417 | #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ |
| 1418 | #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ |
| 1419 | #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1420 | #define E1000_ICS_SRPD E1000_ICR_SRPD |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1421 | |
| 1422 | /* Interrupt Mask Set */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1423 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
| 1424 | #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ |
| 1425 | #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1426 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ |
| 1427 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1428 | #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ |
| 1429 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ |
| 1430 | #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1431 | #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ |
| 1432 | #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ |
| 1433 | #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ |
| 1434 | #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ |
| 1435 | #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ |
| 1436 | #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1437 | #define E1000_IMS_SRPD E1000_ICR_SRPD |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1438 | |
| 1439 | /* Interrupt Mask Clear */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1440 | #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
| 1441 | #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ |
| 1442 | #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1443 | #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ |
| 1444 | #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1445 | #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ |
| 1446 | #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ |
| 1447 | #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1448 | #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ |
| 1449 | #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ |
| 1450 | #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ |
| 1451 | #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ |
| 1452 | #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ |
| 1453 | #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1454 | #define E1000_IMC_SRPD E1000_ICR_SRPD |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1455 | |
| 1456 | /* Receive Control */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1457 | #define E1000_RCTL_RST 0x00000001 /* Software reset */ |
| 1458 | #define E1000_RCTL_EN 0x00000002 /* enable */ |
| 1459 | #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ |
| 1460 | #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ |
| 1461 | #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ |
| 1462 | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ |
| 1463 | #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ |
| 1464 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ |
| 1465 | #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ |
| 1466 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ |
| 1467 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ |
| 1468 | #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ |
| 1469 | #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ |
| 1470 | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ |
| 1471 | #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ |
| 1472 | #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ |
| 1473 | #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ |
| 1474 | #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ |
| 1475 | #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ |
| 1476 | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1477 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1478 | #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ |
| 1479 | #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ |
| 1480 | #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ |
| 1481 | #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1482 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1483 | #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ |
| 1484 | #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ |
| 1485 | #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ |
| 1486 | #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ |
| 1487 | #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ |
| 1488 | #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ |
| 1489 | #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ |
| 1490 | #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ |
| 1491 | #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1492 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1493 | /* SW_W_SYNC definitions */ |
| 1494 | #define E1000_SWFW_EEP_SM 0x0001 |
| 1495 | #define E1000_SWFW_PHY0_SM 0x0002 |
| 1496 | #define E1000_SWFW_PHY1_SM 0x0004 |
| 1497 | #define E1000_SWFW_MAC_CSR_SM 0x0008 |
| 1498 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1499 | /* Receive Descriptor */ |
| 1500 | #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1501 | #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1502 | #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1503 | #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ |
| 1504 | #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1505 | |
| 1506 | /* Flow Control */ |
| 1507 | #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ |
| 1508 | #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ |
| 1509 | #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ |
| 1510 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ |
| 1511 | |
| 1512 | /* Receive Descriptor Control */ |
| 1513 | #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ |
| 1514 | #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ |
| 1515 | #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ |
| 1516 | #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ |
| 1517 | |
| 1518 | /* Transmit Descriptor Control */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1519 | #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ |
| 1520 | #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ |
| 1521 | #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1522 | #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ |
| 1523 | #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ |
| 1524 | #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1525 | #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. |
| 1526 | still to be processed. */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1527 | |
| 1528 | /* Transmit Configuration Word */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1529 | #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ |
| 1530 | #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1531 | #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ |
| 1532 | #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ |
| 1533 | #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1534 | #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ |
| 1535 | #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ |
| 1536 | #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ |
| 1537 | #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ |
| 1538 | #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1539 | |
| 1540 | /* Receive Configuration Word */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1541 | #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ |
| 1542 | #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ |
| 1543 | #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ |
| 1544 | #define E1000_RXCW_CC 0x10000000 /* Receive config change */ |
| 1545 | #define E1000_RXCW_C 0x20000000 /* Receive config */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1546 | #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1547 | #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1548 | |
| 1549 | /* Transmit Control */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1550 | #define E1000_TCTL_RST 0x00000001 /* software reset */ |
| 1551 | #define E1000_TCTL_EN 0x00000002 /* enable tx */ |
| 1552 | #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ |
| 1553 | #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ |
| 1554 | #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1555 | #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ |
| 1556 | #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1557 | #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1558 | #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ |
| 1559 | #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1560 | #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1561 | |
| 1562 | /* Receive Checksum Control */ |
| 1563 | #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ |
| 1564 | #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ |
| 1565 | #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ |
| 1566 | #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ |
| 1567 | |
| 1568 | /* Definitions for power management and wakeup registers */ |
| 1569 | /* Wake Up Control */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1570 | #define E1000_WUC_APME 0x00000001 /* APM Enable */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1571 | #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ |
| 1572 | #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ |
| 1573 | #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ |
| 1574 | |
| 1575 | /* Wake Up Filter Control */ |
| 1576 | #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1577 | #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
| 1578 | #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
| 1579 | #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ |
| 1580 | #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
| 1581 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1582 | #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ |
| 1583 | #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ |
| 1584 | #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ |
| 1585 | #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ |
| 1586 | #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ |
| 1587 | #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ |
| 1588 | #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ |
| 1589 | #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ |
| 1590 | #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ |
| 1591 | |
| 1592 | /* Wake Up Status */ |
| 1593 | #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ |
| 1594 | #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ |
| 1595 | #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ |
| 1596 | #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ |
| 1597 | #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ |
| 1598 | #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ |
| 1599 | #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ |
| 1600 | #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ |
| 1601 | #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ |
| 1602 | #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ |
| 1603 | #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ |
| 1604 | #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ |
| 1605 | #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ |
| 1606 | |
| 1607 | /* Management Control */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1608 | #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ |
| 1609 | #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ |
| 1610 | #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ |
| 1611 | #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ |
| 1612 | #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ |
| 1613 | #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ |
| 1614 | #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ |
| 1615 | #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ |
| 1616 | #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ |
| 1617 | #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1618 | * Filtering */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1619 | #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ |
| 1620 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1621 | #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1622 | #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ |
| 1623 | #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ |
| 1624 | #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ |
| 1625 | #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1626 | #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1627 | #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1628 | |
| 1629 | #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ |
| 1630 | #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ |
| 1631 | |
| 1632 | /* Wake Up Packet Length */ |
| 1633 | #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ |
| 1634 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1635 | #define E1000_MDALIGN 4096 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1636 | |
| 1637 | /* EEPROM Commands */ |
| 1638 | #define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */ |
| 1639 | #define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */ |
| 1640 | #define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */ |
| 1641 | #define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */ |
| 1642 | #define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */ |
| 1643 | |
| 1644 | /* EEPROM Word Offsets */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1645 | #define EEPROM_COMPAT 0x0003 |
| 1646 | #define EEPROM_ID_LED_SETTINGS 0x0004 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1647 | #define EEPROM_INIT_CONTROL1_REG 0x000A |
| 1648 | #define EEPROM_INIT_CONTROL2_REG 0x000F |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1649 | #define EEPROM_FLASH_VERSION 0x0032 |
| 1650 | #define EEPROM_CHECKSUM_REG 0x003F |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1651 | |
| 1652 | /* Word definitions for ID LED Settings */ |
| 1653 | #define ID_LED_RESERVED_0000 0x0000 |
| 1654 | #define ID_LED_RESERVED_FFFF 0xFFFF |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1655 | #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1656 | (ID_LED_OFF1_OFF2 << 8) | \ |
| 1657 | (ID_LED_DEF1_DEF2 << 4) | \ |
| 1658 | (ID_LED_DEF1_DEF2)) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1659 | #define ID_LED_DEF1_DEF2 0x1 |
| 1660 | #define ID_LED_DEF1_ON2 0x2 |
| 1661 | #define ID_LED_DEF1_OFF2 0x3 |
| 1662 | #define ID_LED_ON1_DEF2 0x4 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1663 | #define ID_LED_ON1_ON2 0x5 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1664 | #define ID_LED_ON1_OFF2 0x6 |
| 1665 | #define ID_LED_OFF1_DEF2 0x7 |
| 1666 | #define ID_LED_OFF1_ON2 0x8 |
| 1667 | #define ID_LED_OFF1_OFF2 0x9 |
| 1668 | |
| 1669 | /* Mask bits for fields in Word 0x03 of the EEPROM */ |
| 1670 | #define EEPROM_COMPAT_SERVER 0x0400 |
| 1671 | #define EEPROM_COMPAT_CLIENT 0x0200 |
| 1672 | |
| 1673 | /* Mask bits for fields in Word 0x0a of the EEPROM */ |
| 1674 | #define EEPROM_WORD0A_ILOS 0x0010 |
| 1675 | #define EEPROM_WORD0A_SWDPIO 0x01E0 |
| 1676 | #define EEPROM_WORD0A_LRST 0x0200 |
| 1677 | #define EEPROM_WORD0A_FD 0x0400 |
| 1678 | #define EEPROM_WORD0A_66MHZ 0x0800 |
| 1679 | |
| 1680 | /* Mask bits for fields in Word 0x0f of the EEPROM */ |
| 1681 | #define EEPROM_WORD0F_PAUSE_MASK 0x3000 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1682 | #define EEPROM_WORD0F_PAUSE 0x1000 |
| 1683 | #define EEPROM_WORD0F_ASM_DIR 0x2000 |
| 1684 | #define EEPROM_WORD0F_ANE 0x0800 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1685 | #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 |
| 1686 | |
| 1687 | /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ |
| 1688 | #define EEPROM_SUM 0xBABA |
| 1689 | |
| 1690 | /* EEPROM Map defines (WORD OFFSETS)*/ |
| 1691 | #define EEPROM_NODE_ADDRESS_BYTE_0 0 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1692 | #define EEPROM_PBA_BYTE_1 8 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1693 | |
| 1694 | /* EEPROM Map Sizes (Byte Counts) */ |
| 1695 | #define PBA_SIZE 4 |
| 1696 | |
| 1697 | /* Collision related configuration parameters */ |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1698 | #define E1000_COLLISION_THRESHOLD 0xF |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1699 | #define E1000_CT_SHIFT 4 |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1700 | #define E1000_COLLISION_DISTANCE 63 |
| 1701 | #define E1000_COLLISION_DISTANCE_82542 64 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1702 | #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE |
| 1703 | #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1704 | #define E1000_GB_HDX_COLLISION_DISTANCE 512 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1705 | #define E1000_COLD_SHIFT 12 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1706 | |
| 1707 | /* The number of Transmit and Receive Descriptors must be a multiple of 8 */ |
| 1708 | #define REQ_TX_DESCRIPTOR_MULTIPLE 8 |
| 1709 | #define REQ_RX_DESCRIPTOR_MULTIPLE 8 |
| 1710 | |
| 1711 | /* Default values for the transmit IPG register */ |
| 1712 | #define DEFAULT_82542_TIPG_IPGT 10 |
| 1713 | #define DEFAULT_82543_TIPG_IPGT_FIBER 9 |
| 1714 | #define DEFAULT_82543_TIPG_IPGT_COPPER 8 |
| 1715 | |
| 1716 | #define E1000_TIPG_IPGT_MASK 0x000003FF |
| 1717 | #define E1000_TIPG_IPGR1_MASK 0x000FFC00 |
| 1718 | #define E1000_TIPG_IPGR2_MASK 0x3FF00000 |
| 1719 | |
| 1720 | #define DEFAULT_82542_TIPG_IPGR1 2 |
| 1721 | #define DEFAULT_82543_TIPG_IPGR1 8 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1722 | #define E1000_TIPG_IPGR1_SHIFT 10 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1723 | |
| 1724 | #define DEFAULT_82542_TIPG_IPGR2 10 |
| 1725 | #define DEFAULT_82543_TIPG_IPGR2 6 |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1726 | #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1727 | #define E1000_TIPG_IPGR2_SHIFT 20 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1728 | |
| 1729 | #define E1000_TXDMAC_DPP 0x00000001 |
| 1730 | |
| 1731 | /* Adaptive IFS defines */ |
| 1732 | #define TX_THRESHOLD_START 8 |
| 1733 | #define TX_THRESHOLD_INCREMENT 10 |
| 1734 | #define TX_THRESHOLD_DECREMENT 1 |
| 1735 | #define TX_THRESHOLD_STOP 190 |
| 1736 | #define TX_THRESHOLD_DISABLE 0 |
| 1737 | #define TX_THRESHOLD_TIMER_MS 10000 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1738 | #define MIN_NUM_XMITS 1000 |
| 1739 | #define IFS_MAX 80 |
| 1740 | #define IFS_STEP 10 |
| 1741 | #define IFS_MIN 40 |
| 1742 | #define IFS_RATIO 4 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1743 | |
| 1744 | /* PBA constants */ |
| 1745 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ |
| 1746 | #define E1000_PBA_24K 0x0018 |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1747 | #define E1000_PBA_38K 0x0026 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1748 | #define E1000_PBA_40K 0x0028 |
| 1749 | #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ |
| 1750 | |
| 1751 | /* Flow Control Constants */ |
| 1752 | #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 |
| 1753 | #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1754 | #define FLOW_CONTROL_TYPE 0x8808 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1755 | |
| 1756 | /* The historical defaults for the flow control values are given below. */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1757 | #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ |
| 1758 | #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ |
| 1759 | #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1760 | |
| 1761 | /* Flow Control High-Watermark: 43464 bytes */ |
| 1762 | #define E1000_FC_HIGH_THRESH 0xA9C8 |
| 1763 | /* Flow Control Low-Watermark: 43456 bytes */ |
| 1764 | #define E1000_FC_LOW_THRESH 0xA9C0 |
| 1765 | /* Flow Control Pause Time: 858 usec */ |
| 1766 | #define E1000_FC_PAUSE_TIME 0x0680 |
| 1767 | |
| 1768 | /* PCIX Config space */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1769 | #define PCIX_COMMAND_REGISTER 0xE6 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1770 | #define PCIX_STATUS_REGISTER_LO 0xE8 |
| 1771 | #define PCIX_STATUS_REGISTER_HI 0xEA |
| 1772 | |
| 1773 | #define PCIX_COMMAND_MMRBC_MASK 0x000C |
| 1774 | #define PCIX_COMMAND_MMRBC_SHIFT 0x2 |
| 1775 | #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 |
| 1776 | #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 |
| 1777 | #define PCIX_STATUS_HI_MMRBC_4K 0x3 |
| 1778 | #define PCIX_STATUS_HI_MMRBC_2K 0x2 |
| 1779 | |
| 1780 | /* The number of bits that we need to shift right to move the "pause" |
| 1781 | * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1782 | * in the TXCW register |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1783 | */ |
| 1784 | #define PAUSE_SHIFT 5 |
| 1785 | |
| 1786 | /* The number of bits that we need to shift left to move the "SWDPIO" |
| 1787 | * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1788 | * in the CTRL register |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1789 | */ |
| 1790 | #define SWDPIO_SHIFT 17 |
| 1791 | |
| 1792 | /* The number of bits that we need to shift left to move the "SWDPIO_EXT" |
| 1793 | * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The |
| 1794 | * Extended CTRL register. |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1795 | * in the CTRL register |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1796 | */ |
| 1797 | #define SWDPIO__EXT_SHIFT 4 |
| 1798 | |
| 1799 | /* The number of bits that we need to shift left to move the "ILOS" |
| 1800 | * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1801 | * in the CTRL register |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1802 | */ |
| 1803 | #define ILOS_SHIFT 3 |
| 1804 | |
| 1805 | #define RECEIVE_BUFFER_ALIGN_SIZE (256) |
| 1806 | |
| 1807 | /* The number of milliseconds we wait for auto-negotiation to complete */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1808 | #define LINK_UP_TIMEOUT 500 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1809 | |
| 1810 | #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) |
| 1811 | |
| 1812 | /* The carrier extension symbol, as received by the NIC. */ |
| 1813 | #define CARRIER_EXTENSION 0x0F |
| 1814 | |
| 1815 | /* TBI_ACCEPT macro definition: |
| 1816 | * |
| 1817 | * This macro requires: |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1818 | * adapter = a pointer to struct e1000_hw |
| 1819 | * status = the 8 bit status field of the RX descriptor with EOP set |
| 1820 | * error = the 8 bit error field of the RX descriptor with EOP set |
| 1821 | * length = the sum of all the length fields of the RX descriptors that |
| 1822 | * make up the current frame |
| 1823 | * last_byte = the last byte of the frame DMAed by the hardware |
| 1824 | * max_frame_length = the maximum frame length we want to accept. |
| 1825 | * min_frame_length = the minimum frame length we want to accept. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1826 | * |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1827 | * This macro is a conditional that should be used in the interrupt |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1828 | * handler's Rx processing routine when RxErrors have been detected. |
| 1829 | * |
| 1830 | * Typical use: |
| 1831 | * ... |
| 1832 | * if (TBI_ACCEPT) { |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1833 | * accept_frame = TRUE; |
| 1834 | * e1000_tbi_adjust_stats(adapter, MacAddress); |
| 1835 | * frame_length--; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1836 | * } else { |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1837 | * accept_frame = FALSE; |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1838 | * } |
| 1839 | * ... |
| 1840 | */ |
| 1841 | |
| 1842 | #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ |
| 1843 | ((adapter)->tbi_compatibility_on && \ |
| 1844 | (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ |
| 1845 | ((last_byte) == CARRIER_EXTENSION) && \ |
| 1846 | (((status) & E1000_RXD_STAT_VP) ? \ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1847 | (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ |
| 1848 | ((length) <= ((adapter)->max_frame_size + 1))) : \ |
| 1849 | (((length) > (adapter)->min_frame_size) && \ |
| 1850 | ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1851 | |
| 1852 | /* Structures, enums, and macros for the PHY */ |
| 1853 | |
| 1854 | /* Bit definitions for the Management Data IO (MDIO) and Management Data |
| 1855 | * Clock (MDC) pins in the Device Control Register. |
| 1856 | */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1857 | #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 |
| 1858 | #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 |
| 1859 | #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 |
| 1860 | #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 |
| 1861 | #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 |
| 1862 | #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 |
| 1863 | #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR |
| 1864 | #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1865 | |
| 1866 | /* PHY 1000 MII Register/Bit Definitions */ |
| 1867 | /* PHY Registers defined by IEEE */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1868 | #define PHY_CTRL 0x00 /* Control Register */ |
| 1869 | #define PHY_STATUS 0x01 /* Status Regiser */ |
| 1870 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ |
| 1871 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ |
| 1872 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ |
| 1873 | #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ |
| 1874 | #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ |
| 1875 | #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ |
| 1876 | #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ |
| 1877 | #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ |
| 1878 | #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ |
| 1879 | #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1880 | |
| 1881 | /* M88E1000 Specific Registers */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1882 | #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ |
| 1883 | #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ |
| 1884 | #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ |
| 1885 | #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ |
| 1886 | #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ |
| 1887 | #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1888 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1889 | #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ |
| 1890 | #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ |
| 1891 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1892 | #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 1893 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1894 | /* M88EC018 Rev 2 specific DownShift settings */ |
| 1895 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 |
| 1896 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 |
| 1897 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 |
| 1898 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 |
| 1899 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 |
| 1900 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 |
| 1901 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 |
| 1902 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 |
| 1903 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 |
| 1904 | |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 1905 | /* IGP01E1000 specifics */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1906 | #define IGP01E1000_IEEE_REGS_PAGE 0x0000 |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 1907 | #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1908 | #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 |
Andre Schwarz | 68c2a30 | 2008-03-06 16:45:44 +0100 | [diff] [blame] | 1909 | |
| 1910 | /* IGP01E1000 Specific Registers */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 1911 | #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ |
| 1912 | #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ |
| 1913 | #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ |
| 1914 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ |
| 1915 | #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ |
| 1916 | #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ |
| 1917 | #define IGP02E1000_PHY_POWER_MGMT 0x19 |
| 1918 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 1919 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 1920 | /* IGP01E1000 AGC Registers - stores the cable length values*/ |
| 1921 | #define IGP01E1000_PHY_AGC_A 0x1172 |
| 1922 | #define IGP01E1000_PHY_AGC_B 0x1272 |
| 1923 | #define IGP01E1000_PHY_AGC_C 0x1472 |
| 1924 | #define IGP01E1000_PHY_AGC_D 0x1872 |
| 1925 | |
| 1926 | /* IGP01E1000 Specific Port Config Register - R/W */ |
| 1927 | #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 |
| 1928 | #define IGP01E1000_PSCFR_PRE_EN 0x0020 |
| 1929 | #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 |
| 1930 | #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 |
| 1931 | #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 |
| 1932 | #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 |
| 1933 | /* IGP02E1000 AGC Registers for cable length values */ |
| 1934 | #define IGP02E1000_PHY_AGC_A 0x11B1 |
| 1935 | #define IGP02E1000_PHY_AGC_B 0x12B1 |
| 1936 | #define IGP02E1000_PHY_AGC_C 0x14B1 |
| 1937 | #define IGP02E1000_PHY_AGC_D 0x18B1 |
| 1938 | |
| 1939 | #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ |
| 1940 | #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in |
| 1941 | non-D0a modes */ |
| 1942 | #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in |
| 1943 | D0a mode */ |
| 1944 | |
| 1945 | /* IGP01E1000 DSP Reset Register */ |
| 1946 | #define IGP01E1000_PHY_DSP_RESET 0x1F33 |
| 1947 | #define IGP01E1000_PHY_DSP_SET 0x1F71 |
| 1948 | #define IGP01E1000_PHY_DSP_FFE 0x1F35 |
| 1949 | |
| 1950 | #define IGP01E1000_PHY_CHANNEL_NUM 4 |
| 1951 | #define IGP02E1000_PHY_CHANNEL_NUM 4 |
| 1952 | |
| 1953 | #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 |
| 1954 | #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 |
| 1955 | #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 |
| 1956 | #define IGP01E1000_PHY_AGC_PARAM_D 0x1871 |
| 1957 | |
| 1958 | #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 |
| 1959 | #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 |
| 1960 | |
| 1961 | #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 |
| 1962 | #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 |
| 1963 | #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 |
| 1964 | #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 |
| 1965 | |
| 1966 | #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A |
| 1967 | /* IGP01E1000 PCS Initialization register - stores the polarity status when |
| 1968 | * speed = 1000 Mbps. */ |
| 1969 | #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 |
| 1970 | #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 |
| 1971 | |
| 1972 | #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 |
| 1973 | |
| 1974 | /* IGP01E1000 GMII FIFO Register */ |
| 1975 | #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed |
| 1976 | * on Link-Up */ |
| 1977 | #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ |
| 1978 | |
| 1979 | /* IGP01E1000 Analog Register */ |
| 1980 | #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 |
| 1981 | #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 |
| 1982 | #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC |
| 1983 | #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE |
| 1984 | |
| 1985 | #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 |
| 1986 | #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 |
| 1987 | #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 |
| 1988 | #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 |
| 1989 | #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 |
| 1990 | |
| 1991 | #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 |
| 1992 | #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 |
| 1993 | #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 |
| 1994 | #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 |
| 1995 | |
| 1996 | /* IGP01E1000 Specific Port Control Register - R/W */ |
| 1997 | #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 |
| 1998 | #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 |
| 1999 | #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 |
| 2000 | #define IGP01E1000_PSCR_FLIP_CHIP 0x0800 |
| 2001 | #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 |
| 2002 | #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ |
| 2003 | /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ |
| 2004 | #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ |
| 2005 | #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal |
| 2006 | Disabled */ |
| 2007 | #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ |
| 2008 | #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter |
| 2009 | Disabled */ |
| 2010 | #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 |
| 2011 | #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI |
| 2012 | configuration */ |
| 2013 | #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX |
| 2014 | configuration */ |
| 2015 | #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic |
| 2016 | crossover */ |
| 2017 | #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended |
| 2018 | Distance */ |
| 2019 | #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300 |
| 2020 | #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ |
| 2021 | #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only |
| 2022 | (Energy Detect) */ |
| 2023 | #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ |
| 2024 | #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ |
| 2025 | #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ |
| 2026 | #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 |
| 2027 | #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 |
| 2028 | |
| 2029 | /* PHY Specific Status Register (Page 0, Register 17) */ |
| 2030 | #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */ |
| 2031 | #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */ |
| 2032 | #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */ |
| 2033 | #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */ |
| 2034 | #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */ |
| 2035 | #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */ |
| 2036 | #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */ |
| 2037 | #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */ |
| 2038 | #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */ |
| 2039 | #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */ |
| 2040 | #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */ |
| 2041 | #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */ |
| 2042 | #define GG82563_PSSR_SPEED_MASK 0xC000 |
| 2043 | #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */ |
| 2044 | #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */ |
| 2045 | #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */ |
| 2046 | |
| 2047 | /* PHY Specific Status Register 2 (Page 0, Register 19) */ |
| 2048 | #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */ |
| 2049 | #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */ |
| 2050 | #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ |
| 2051 | #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ |
| 2052 | #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ |
| 2053 | #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */ |
| 2054 | #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ |
| 2055 | #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ |
| 2056 | #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ |
| 2057 | #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */ |
| 2058 | #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */ |
| 2059 | #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */ |
| 2060 | #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */ |
| 2061 | |
| 2062 | /* PHY Specific Control Register 2 (Page 0, Register 26) */ |
| 2063 | #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative |
| 2064 | Polarity */ |
| 2065 | #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C |
| 2066 | #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal |
| 2067 | Operation */ |
| 2068 | #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns |
| 2069 | Sequence */ |
| 2070 | #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns |
| 2071 | Sequence */ |
| 2072 | #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse |
| 2073 | Auto-Negotiation */ |
| 2074 | #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable |
| 2075 | 1000BASE-T */ |
| 2076 | #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000 |
| 2077 | #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */ |
| 2078 | #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */ |
| 2079 | |
| 2080 | /* MAC Specific Control Register (Page 2, Register 21) */ |
| 2081 | /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ |
| 2082 | #define GG82563_MSCR_TX_CLK_MASK 0x0007 |
| 2083 | #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004 |
| 2084 | #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005 |
| 2085 | #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006 |
| 2086 | #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007 |
| 2087 | |
| 2088 | #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ |
| 2089 | |
| 2090 | /* DSP Distance Register (Page 5, Register 26) */ |
| 2091 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; |
| 2092 | 1 = 50-80M; |
| 2093 | 2 = 80-110M; |
| 2094 | 3 = 110-140M; |
| 2095 | 4 = >140M */ |
| 2096 | |
| 2097 | /* Kumeran Mode Control Register (Page 193, Register 16) */ |
| 2098 | #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, |
| 2099 | 0=Kumeran Inband LEDs */ |
| 2100 | #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */ |
| 2101 | #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080 |
| 2102 | #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400 |
| 2103 | #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, |
| 2104 | 0=0.8MHz */ |
| 2105 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 |
| 2106 | |
| 2107 | /* Power Management Control Register (Page 193, Register 20) */ |
| 2108 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES |
| 2109 | Electrical Idle */ |
| 2110 | #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */ |
| 2111 | #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */ |
| 2112 | #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse |
| 2113 | Auto-Negotiation */ |
| 2114 | #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps |
| 2115 | Auto-Neg in non D0 */ |
| 2116 | #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps |
| 2117 | Auto-Neg Always */ |
| 2118 | #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a |
| 2119 | Reverse Auto-Negotiation */ |
| 2120 | #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */ |
| 2121 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300 |
| 2122 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */ |
| 2123 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */ |
| 2124 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */ |
| 2125 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */ |
| 2126 | |
| 2127 | /* In-Band Control Register (Page 194, Register 18) */ |
| 2128 | #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ |
| 2129 | |
| 2130 | |
| 2131 | /* Bits... |
| 2132 | * 15-5: page |
| 2133 | * 4-0: register offset |
| 2134 | */ |
| 2135 | #define GG82563_PAGE_SHIFT 5 |
| 2136 | #define GG82563_REG(page, reg) \ |
| 2137 | (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) |
| 2138 | #define GG82563_MIN_ALT_REG 30 |
| 2139 | |
| 2140 | /* GG82563 Specific Registers */ |
| 2141 | #define GG82563_PHY_SPEC_CTRL \ |
| 2142 | GG82563_REG(0, 16) /* PHY Specific Control */ |
| 2143 | #define GG82563_PHY_SPEC_STATUS \ |
| 2144 | GG82563_REG(0, 17) /* PHY Specific Status */ |
| 2145 | #define GG82563_PHY_INT_ENABLE \ |
| 2146 | GG82563_REG(0, 18) /* Interrupt Enable */ |
| 2147 | #define GG82563_PHY_SPEC_STATUS_2 \ |
| 2148 | GG82563_REG(0, 19) /* PHY Specific Status 2 */ |
| 2149 | #define GG82563_PHY_RX_ERR_CNTR \ |
| 2150 | GG82563_REG(0, 21) /* Receive Error Counter */ |
| 2151 | #define GG82563_PHY_PAGE_SELECT \ |
| 2152 | GG82563_REG(0, 22) /* Page Select */ |
| 2153 | #define GG82563_PHY_SPEC_CTRL_2 \ |
| 2154 | GG82563_REG(0, 26) /* PHY Specific Control 2 */ |
| 2155 | #define GG82563_PHY_PAGE_SELECT_ALT \ |
| 2156 | GG82563_REG(0, 29) /* Alternate Page Select */ |
| 2157 | #define GG82563_PHY_TEST_CLK_CTRL \ |
| 2158 | GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ |
| 2159 | |
| 2160 | #define GG82563_PHY_MAC_SPEC_CTRL \ |
| 2161 | GG82563_REG(2, 21) /* MAC Specific Control Register */ |
| 2162 | #define GG82563_PHY_MAC_SPEC_CTRL_2 \ |
| 2163 | GG82563_REG(2, 26) /* MAC Specific Control 2 */ |
| 2164 | |
| 2165 | #define GG82563_PHY_DSP_DISTANCE \ |
| 2166 | GG82563_REG(5, 26) /* DSP Distance */ |
| 2167 | |
| 2168 | /* Page 193 - Port Control Registers */ |
| 2169 | #define GG82563_PHY_KMRN_MODE_CTRL \ |
| 2170 | GG82563_REG(193, 16) /* Kumeran Mode Control */ |
| 2171 | #define GG82563_PHY_PORT_RESET \ |
| 2172 | GG82563_REG(193, 17) /* Port Reset */ |
| 2173 | #define GG82563_PHY_REVISION_ID \ |
| 2174 | GG82563_REG(193, 18) /* Revision ID */ |
| 2175 | #define GG82563_PHY_DEVICE_ID \ |
| 2176 | GG82563_REG(193, 19) /* Device ID */ |
| 2177 | #define GG82563_PHY_PWR_MGMT_CTRL \ |
| 2178 | GG82563_REG(193, 20) /* Power Management Control */ |
| 2179 | #define GG82563_PHY_RATE_ADAPT_CTRL \ |
| 2180 | GG82563_REG(193, 25) /* Rate Adaptation Control */ |
| 2181 | |
| 2182 | /* Page 194 - KMRN Registers */ |
| 2183 | #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ |
| 2184 | GG82563_REG(194, 16) /* FIFO's Control/Status */ |
| 2185 | #define GG82563_PHY_KMRN_CTRL \ |
| 2186 | GG82563_REG(194, 17) /* Control */ |
| 2187 | #define GG82563_PHY_INBAND_CTRL \ |
| 2188 | GG82563_REG(194, 18) /* Inband Control */ |
| 2189 | #define GG82563_PHY_KMRN_DIAGNOSTIC \ |
| 2190 | GG82563_REG(194, 19) /* Diagnostic */ |
| 2191 | #define GG82563_PHY_ACK_TIMEOUTS \ |
| 2192 | GG82563_REG(194, 20) /* Acknowledge Timeouts */ |
| 2193 | #define GG82563_PHY_ADV_ABILITY \ |
| 2194 | GG82563_REG(194, 21) /* Advertised Ability */ |
| 2195 | #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ |
| 2196 | GG82563_REG(194, 23) /* Link Partner Advertised Ability */ |
| 2197 | #define GG82563_PHY_ADV_NEXT_PAGE \ |
| 2198 | GG82563_REG(194, 24) /* Advertised Next Page */ |
| 2199 | #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ |
| 2200 | GG82563_REG(194, 25) /* Link Partner Advertised Next page */ |
| 2201 | #define GG82563_PHY_KMRN_MISC \ |
| 2202 | GG82563_REG(194, 26) /* Misc. */ |
| 2203 | |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2204 | /* PHY Control Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2205 | #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ |
| 2206 | #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ |
| 2207 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
| 2208 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
| 2209 | #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ |
| 2210 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ |
| 2211 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
| 2212 | #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ |
| 2213 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
| 2214 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2215 | |
| 2216 | /* PHY Status Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2217 | #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ |
| 2218 | #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ |
| 2219 | #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ |
| 2220 | #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ |
| 2221 | #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ |
| 2222 | #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ |
| 2223 | #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ |
| 2224 | #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ |
| 2225 | #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ |
| 2226 | #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ |
| 2227 | #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ |
| 2228 | #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ |
| 2229 | #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ |
| 2230 | #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ |
| 2231 | #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2232 | |
| 2233 | /* Autoneg Advertisement Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2234 | #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ |
| 2235 | #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ |
| 2236 | #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ |
| 2237 | #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ |
| 2238 | #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ |
| 2239 | #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ |
| 2240 | #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ |
| 2241 | #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ |
| 2242 | #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ |
| 2243 | #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2244 | |
| 2245 | /* Link Partner Ability Register (Base Page) */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2246 | #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ |
| 2247 | #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ |
| 2248 | #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ |
| 2249 | #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ |
| 2250 | #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ |
| 2251 | #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ |
| 2252 | #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ |
| 2253 | #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ |
| 2254 | #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ |
| 2255 | #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ |
| 2256 | #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2257 | |
| 2258 | /* Autoneg Expansion Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2259 | #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ |
| 2260 | #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ |
| 2261 | #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ |
| 2262 | #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ |
| 2263 | #define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2264 | |
| 2265 | /* Next Page TX Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2266 | #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ |
| 2267 | #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges |
| 2268 | * of different NP |
| 2269 | */ |
| 2270 | #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg |
| 2271 | * 0 = cannot comply with msg |
| 2272 | */ |
| 2273 | #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ |
| 2274 | #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow |
| 2275 | * 0 = sending last NP |
| 2276 | */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2277 | |
| 2278 | /* Link Partner Next Page Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2279 | #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ |
| 2280 | #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges |
| 2281 | * of different NP |
| 2282 | */ |
| 2283 | #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg |
| 2284 | * 0 = cannot comply with msg |
| 2285 | */ |
| 2286 | #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ |
| 2287 | #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ |
| 2288 | #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow |
| 2289 | * 0 = sending last NP |
| 2290 | */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2291 | |
| 2292 | /* 1000BASE-T Control Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2293 | #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ |
| 2294 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ |
| 2295 | #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ |
| 2296 | #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ |
| 2297 | /* 0=DTE device */ |
| 2298 | #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ |
| 2299 | /* 0=Configure PHY as Slave */ |
| 2300 | #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ |
| 2301 | /* 0=Automatic Master/Slave config */ |
| 2302 | #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ |
| 2303 | #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ |
| 2304 | #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ |
| 2305 | #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ |
| 2306 | #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2307 | |
| 2308 | /* 1000BASE-T Status Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2309 | #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ |
| 2310 | #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ |
| 2311 | #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ |
| 2312 | #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ |
| 2313 | #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ |
| 2314 | #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ |
| 2315 | #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ |
| 2316 | #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2317 | #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2318 | #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2319 | |
| 2320 | /* Extended Status Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2321 | #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ |
| 2322 | #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ |
| 2323 | #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ |
| 2324 | #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2325 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2326 | #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ |
| 2327 | #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2328 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2329 | #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ |
| 2330 | /* (0=enable, 1=disable) */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2331 | |
| 2332 | /* M88E1000 PHY Specific Control Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2333 | #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2334 | #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2335 | #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ |
| 2336 | #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2337 | * 0=CLK125 toggling |
| 2338 | */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2339 | #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ |
| 2340 | /* Manual MDI configuration */ |
| 2341 | #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ |
| 2342 | #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2343 | * 100BASE-TX/10BASE-T: |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2344 | * MDI Mode |
| 2345 | */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2346 | #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2347 | * all speeds. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2348 | */ |
| 2349 | #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2350 | /* 1=Enable Extended 10BASE-T distance |
| 2351 | * (Lower 10BASE-T RX Threshold) |
| 2352 | * 0=Normal 10BASE-T RX Threshold */ |
| 2353 | #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 |
| 2354 | /* 1=5-Bit interface in 100BASE-TX |
| 2355 | * 0=MII interface in 100BASE-TX */ |
| 2356 | #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ |
| 2357 | #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ |
| 2358 | #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2359 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2360 | #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 |
| 2361 | #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2362 | #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 |
| 2363 | |
| 2364 | /* M88E1000 PHY Specific Status Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2365 | #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ |
| 2366 | #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ |
| 2367 | #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ |
| 2368 | #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; |
| 2369 | * 3=110-140M;4=>140M */ |
| 2370 | #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ |
| 2371 | #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ |
| 2372 | #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ |
| 2373 | #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ |
| 2374 | #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ |
| 2375 | #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ |
| 2376 | #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ |
| 2377 | #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2378 | |
| 2379 | #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2380 | #define M88E1000_PSSR_MDIX_SHIFT 6 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2381 | #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 |
| 2382 | |
| 2383 | /* M88E1000 Extended PHY Specific Control Register */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2384 | #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ |
| 2385 | #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2386 | * Will assert lost lock and bring |
| 2387 | * link down if idle not seen |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 2388 | * within 1ms in 1000BASE-T |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2389 | */ |
| 2390 | /* Number of times we will attempt to autonegotiate before downshifting if we |
| 2391 | * are the master */ |
| 2392 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 |
| 2393 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 |
| 2394 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 |
| 2395 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 |
| 2396 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 |
| 2397 | /* Number of times we will attempt to autonegotiate before downshifting if we |
| 2398 | * are the slave */ |
| 2399 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 |
| 2400 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 |
| 2401 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 |
| 2402 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 |
| 2403 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2404 | #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ |
| 2405 | #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ |
| 2406 | #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2407 | |
| 2408 | /* Bit definitions for valid PHY IDs. */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2409 | #define M88E1000_E_PHY_ID 0x01410C50 |
| 2410 | #define M88E1000_I_PHY_ID 0x01410C30 |
| 2411 | #define M88E1011_I_PHY_ID 0x01410C20 |
| 2412 | #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID |
| 2413 | #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID |
| 2414 | #define IGP01E1000_I_PHY_ID 0x02A80380 |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2415 | #define M88E1011_I_REV_4 0x04 |
| 2416 | #define M88E1111_I_PHY_ID 0x01410CC0 |
| 2417 | #define L1LXT971A_PHY_ID 0x001378E0 |
| 2418 | #define GG82563_E_PHY_ID 0x01410CA0 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2419 | |
| 2420 | /* Miscellaneous PHY bit definitions. */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2421 | #define PHY_PREAMBLE 0xFFFFFFFF |
| 2422 | #define PHY_SOF 0x01 |
| 2423 | #define PHY_OP_READ 0x02 |
| 2424 | #define PHY_OP_WRITE 0x01 |
| 2425 | #define PHY_TURNAROUND 0x02 |
| 2426 | #define PHY_PREAMBLE_SIZE 32 |
| 2427 | #define MII_CR_SPEED_1000 0x0040 |
| 2428 | #define MII_CR_SPEED_100 0x2000 |
| 2429 | #define MII_CR_SPEED_10 0x0000 |
| 2430 | #define E1000_PHY_ADDRESS 0x01 |
| 2431 | #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ |
| 2432 | #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ |
| 2433 | #define PHY_REVISION_MASK 0xFFFFFFF0 |
| 2434 | #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ |
| 2435 | #define REG4_SPEED_MASK 0x01E0 |
| 2436 | #define REG9_SPEED_MASK 0x0300 |
| 2437 | #define ADVERTISE_10_HALF 0x0001 |
| 2438 | #define ADVERTISE_10_FULL 0x0002 |
| 2439 | #define ADVERTISE_100_HALF 0x0004 |
| 2440 | #define ADVERTISE_100_FULL 0x0008 |
| 2441 | #define ADVERTISE_1000_HALF 0x0010 |
| 2442 | #define ADVERTISE_1000_FULL 0x0020 |
wdenk | 4e112c1 | 2003-06-03 23:54:09 +0000 | [diff] [blame] | 2443 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ |
| 2444 | |
Roy Zang | 28f7a05 | 2009-07-31 13:34:02 +0800 | [diff] [blame] | 2445 | #define ICH_FLASH_GFPREG 0x0000 |
| 2446 | #define ICH_FLASH_HSFSTS 0x0004 |
| 2447 | #define ICH_FLASH_HSFCTL 0x0006 |
| 2448 | #define ICH_FLASH_FADDR 0x0008 |
| 2449 | #define ICH_FLASH_FDATA0 0x0010 |
| 2450 | #define ICH_FLASH_FRACC 0x0050 |
| 2451 | #define ICH_FLASH_FREG0 0x0054 |
| 2452 | #define ICH_FLASH_FREG1 0x0058 |
| 2453 | #define ICH_FLASH_FREG2 0x005C |
| 2454 | #define ICH_FLASH_FREG3 0x0060 |
| 2455 | #define ICH_FLASH_FPR0 0x0074 |
| 2456 | #define ICH_FLASH_FPR1 0x0078 |
| 2457 | #define ICH_FLASH_SSFSTS 0x0090 |
| 2458 | #define ICH_FLASH_SSFCTL 0x0092 |
| 2459 | #define ICH_FLASH_PREOP 0x0094 |
| 2460 | #define ICH_FLASH_OPTYPE 0x0096 |
| 2461 | #define ICH_FLASH_OPMENU 0x0098 |
| 2462 | |
| 2463 | #define ICH_FLASH_REG_MAPSIZE 0x00A0 |
| 2464 | #define ICH_FLASH_SECTOR_SIZE 4096 |
| 2465 | #define ICH_GFPREG_BASE_MASK 0x1FFF |
| 2466 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF |
| 2467 | |
| 2468 | #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ |
| 2469 | #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ |
| 2470 | |
| 2471 | /* SPI EEPROM Status Register */ |
| 2472 | #define EEPROM_STATUS_RDY_SPI 0x01 |
| 2473 | #define EEPROM_STATUS_WEN_SPI 0x02 |
| 2474 | #define EEPROM_STATUS_BP0_SPI 0x04 |
| 2475 | #define EEPROM_STATUS_BP1_SPI 0x08 |
| 2476 | #define EEPROM_STATUS_WPEN_SPI 0x80 |
| 2477 | |
| 2478 | /* SW Semaphore Register */ |
| 2479 | #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ |
| 2480 | #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ |
| 2481 | #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ |
| 2482 | #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ |
| 2483 | |
| 2484 | /* FW Semaphore Register */ |
| 2485 | #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ |
| 2486 | #define E1000_FWSM_MODE_SHIFT 1 |
| 2487 | #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ |
| 2488 | |
| 2489 | #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ |
| 2490 | #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ |
| 2491 | #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ |
| 2492 | #define E1000_FWSM_SKUEL_SHIFT 29 |
| 2493 | #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ |
| 2494 | #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ |
| 2495 | #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ |
| 2496 | #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ |
| 2497 | |
| 2498 | #define E1000_GCR 0x05B00 /* PCI-Ex Control */ |
| 2499 | #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ |
| 2500 | #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ |
| 2501 | #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ |
| 2502 | #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ |
| 2503 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ |
| 2504 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ |
| 2505 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ |
| 2506 | #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ |
| 2507 | #define E1000_HICR 0x08F00 /* Host Inteface Control */ |
| 2508 | |
| 2509 | #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF |
| 2510 | #define IGP_ACTIVITY_LED_ENABLE 0x0300 |
| 2511 | #define IGP_LED3_MODE 0x07000000 |
| 2512 | |
| 2513 | /* Mask bit for PHY class in Word 7 of the EEPROM */ |
| 2514 | #define EEPROM_PHY_CLASS_A 0x8000 |
| 2515 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ |
| 2516 | #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ |
| 2517 | #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ |
| 2518 | |
| 2519 | #define E1000_KUMCTRLSTA_MASK 0x0000FFFF |
| 2520 | #define E1000_KUMCTRLSTA_OFFSET 0x001F0000 |
| 2521 | #define E1000_KUMCTRLSTA_OFFSET_SHIFT 16 |
| 2522 | #define E1000_KUMCTRLSTA_REN 0x00200000 |
| 2523 | |
| 2524 | #define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 |
| 2525 | #define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001 |
| 2526 | #define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 |
| 2527 | #define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003 |
| 2528 | #define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 |
| 2529 | #define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 |
| 2530 | #define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 |
| 2531 | #define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E |
| 2532 | #define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F |
| 2533 | |
| 2534 | /* FIFO Control */ |
| 2535 | #define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 |
| 2536 | #define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 |
| 2537 | |
| 2538 | /* In-Band Control */ |
| 2539 | #define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500 |
| 2540 | #define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 |
| 2541 | |
| 2542 | /* Half-Duplex Control */ |
| 2543 | #define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 |
| 2544 | #define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 |
| 2545 | |
| 2546 | #define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E |
| 2547 | |
| 2548 | #define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000 |
| 2549 | #define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000 |
| 2550 | |
| 2551 | #define E1000_KUMCTRLSTA_K0S_100_EN 0x2000 |
| 2552 | #define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000 |
| 2553 | #define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003 |
| 2554 | |
| 2555 | #define E1000_MNG_ICH_IAMT_MODE 0x2 |
| 2556 | #define E1000_MNG_IAMT_MODE 0x3 |
| 2557 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ |
| 2558 | #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ |
| 2559 | /* Number of milliseconds we wait for PHY configuration done after MAC reset */ |
| 2560 | #define PHY_CFG_TIMEOUT 100 |
| 2561 | #define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009 |
| 2562 | #define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008 |
| 2563 | #define E1000_TXDMAC_DPP 0x00000001 |
| 2564 | #define AUTO_ALL_MODES 0 |
| 2565 | |
| 2566 | #ifndef E1000_MASTER_SLAVE |
| 2567 | /* Switch to override PHY master/slave setting */ |
| 2568 | #define E1000_MASTER_SLAVE e1000_ms_hw_default |
| 2569 | #endif |
| 2570 | /* Extended Transmit Control */ |
| 2571 | #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ |
| 2572 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ |
| 2573 | |
| 2574 | #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 |
| 2575 | |
| 2576 | #define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL |
| 2577 | |
| 2578 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 |
| 2579 | #define E1000_MC_TBL_SIZE_ICH8LAN 32 |
| 2580 | |
| 2581 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers |
| 2582 | after IMS clear */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 2583 | #endif /* _E1000_HW_H_ */ |