Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 1 | /* |
Mike Frysinger | b11eb3f | 2008-02-24 23:58:13 -0500 | [diff] [blame] | 2 | * Driver for Blackfin On-Chip MAC device |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 3 | * |
Mike Frysinger | b11eb3f | 2008-02-24 23:58:13 -0500 | [diff] [blame] | 4 | * Copyright (c) 2005-2008 Analog Device, Inc. |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 5 | * |
Mike Frysinger | b11eb3f | 2008-02-24 23:58:13 -0500 | [diff] [blame] | 6 | * Licensed under the GPL-2 or later. |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <config.h> |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 11 | #include <net.h> |
Ben Warren | 2f2b6b6 | 2008-08-31 22:22:04 -0700 | [diff] [blame] | 12 | #include <netdev.h> |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 13 | #include <command.h> |
| 14 | #include <malloc.h> |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 15 | #include <miiphy.h> |
| 16 | #include <linux/mii.h> |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 17 | |
Mike Frysinger | b11eb3f | 2008-02-24 23:58:13 -0500 | [diff] [blame] | 18 | #include <asm/blackfin.h> |
Mike Frysinger | eca7f57 | 2010-06-02 05:56:22 -0400 | [diff] [blame] | 19 | #include <asm/portmux.h> |
Mike Frysinger | 66c4cf4 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 20 | #include <asm/mach-common/bits/dma.h> |
| 21 | #include <asm/mach-common/bits/emac.h> |
| 22 | #include <asm/mach-common/bits/pll.h> |
| 23 | |
Mike Frysinger | b11eb3f | 2008-02-24 23:58:13 -0500 | [diff] [blame] | 24 | #include "bfin_mac.h" |
| 25 | |
Mike Frysinger | 65b7d93 | 2008-10-20 13:59:51 -0400 | [diff] [blame] | 26 | #ifndef CONFIG_PHY_ADDR |
| 27 | # define CONFIG_PHY_ADDR 1 |
| 28 | #endif |
| 29 | #ifndef CONFIG_PHY_CLOCK_FREQ |
| 30 | # define CONFIG_PHY_CLOCK_FREQ 2500000 |
| 31 | #endif |
| 32 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 33 | #ifdef CONFIG_POST |
| 34 | #include <post.h> |
| 35 | #endif |
| 36 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 37 | #define RXBUF_BASE_ADDR 0xFF900000 |
| 38 | #define TXBUF_BASE_ADDR 0xFF800000 |
| 39 | #define TX_BUF_CNT 1 |
| 40 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 41 | #define TOUT_LOOP 1000000 |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 42 | |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 43 | static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT]; |
| 44 | static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX]; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 45 | static u16 txIdx; /* index of the current RX buffer */ |
| 46 | static u16 rxIdx; /* index of the current TX buffer */ |
| 47 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 48 | /* DMAx_CONFIG values at DMA Restart */ |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 49 | static const union { |
| 50 | u16 data; |
| 51 | ADI_DMA_CONFIG_REG reg; |
| 52 | } txdmacfg = { |
| 53 | .reg = { |
| 54 | .b_DMA_EN = 1, /* enabled */ |
| 55 | .b_WNR = 0, /* read from memory */ |
| 56 | .b_WDSIZE = 2, /* wordsize is 32 bits */ |
| 57 | .b_DMA2D = 0, |
| 58 | .b_RESTART = 0, |
| 59 | .b_DI_SEL = 0, |
| 60 | .b_DI_EN = 0, /* no interrupt */ |
| 61 | .b_NDSIZE = 5, /* 5 half words is desc size */ |
| 62 | .b_FLOW = 7 /* large desc flow */ |
| 63 | }, |
Mike Frysinger | b11eb3f | 2008-02-24 23:58:13 -0500 | [diff] [blame] | 64 | }; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 65 | |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 66 | static int bfin_miiphy_wait(void) |
| 67 | { |
| 68 | /* poll the STABUSY bit */ |
| 69 | while (bfin_read_EMAC_STAADD() & STABUSY) |
| 70 | continue; |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | static int bfin_miiphy_read(char *devname, uchar addr, uchar reg, ushort *val) |
| 75 | { |
| 76 | if (bfin_miiphy_wait()) |
| 77 | return 1; |
| 78 | bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY); |
| 79 | if (bfin_miiphy_wait()) |
| 80 | return 1; |
| 81 | *val = bfin_read_EMAC_STADAT(); |
| 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | static int bfin_miiphy_write(char *devname, uchar addr, uchar reg, ushort val) |
| 86 | { |
| 87 | if (bfin_miiphy_wait()) |
| 88 | return 1; |
| 89 | bfin_write_EMAC_STADAT(val); |
| 90 | bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY); |
| 91 | return 0; |
| 92 | } |
| 93 | |
Mike Frysinger | b11eb3f | 2008-02-24 23:58:13 -0500 | [diff] [blame] | 94 | int bfin_EMAC_initialize(bd_t *bis) |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 95 | { |
| 96 | struct eth_device *dev; |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 97 | dev = malloc(sizeof(*dev)); |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 98 | if (dev == NULL) |
| 99 | hang(); |
| 100 | |
| 101 | memset(dev, 0, sizeof(*dev)); |
Mike Frysinger | 95d834a | 2010-06-09 21:50:48 -0400 | [diff] [blame] | 102 | strcpy(dev->name, "bfin_mac"); |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 103 | |
| 104 | dev->iobase = 0; |
| 105 | dev->priv = 0; |
| 106 | dev->init = bfin_EMAC_init; |
| 107 | dev->halt = bfin_EMAC_halt; |
| 108 | dev->send = bfin_EMAC_send; |
| 109 | dev->recv = bfin_EMAC_recv; |
Mike Frysinger | 35be872 | 2010-04-27 14:15:28 -0400 | [diff] [blame] | 110 | dev->write_hwaddr = bfin_EMAC_setup_addr; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 111 | |
| 112 | eth_register(dev); |
| 113 | |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 114 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
| 115 | miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write); |
| 116 | #endif |
| 117 | |
Ben Warren | 82c2c6a | 2008-07-11 23:15:28 -0700 | [diff] [blame] | 118 | return 0; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, |
| 122 | int length) |
| 123 | { |
| 124 | int i; |
| 125 | int result = 0; |
| 126 | unsigned int *buf; |
| 127 | buf = (unsigned int *)packet; |
| 128 | |
| 129 | if (length <= 0) { |
| 130 | printf("Ethernet: bad packet size: %d\n", length); |
| 131 | goto out; |
| 132 | } |
| 133 | |
| 134 | if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) { |
| 135 | printf("Ethernet: tx DMA error\n"); |
| 136 | goto out; |
| 137 | } |
| 138 | |
| 139 | for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) { |
| 140 | if (i > TOUT_LOOP) { |
| 141 | puts("Ethernet: tx time out\n"); |
| 142 | goto out; |
| 143 | } |
| 144 | } |
| 145 | txbuf[txIdx]->FrmData->NoBytes = length; |
| 146 | memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length); |
| 147 | txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData; |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 148 | *pDMA2_NEXT_DESC_PTR = txbuf[txIdx]->Dma; |
| 149 | *pDMA2_CONFIG = txdmacfg.data; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 150 | *pEMAC_OPMODE |= TE; |
| 151 | |
| 152 | for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) { |
| 153 | if (i > TOUT_LOOP) { |
| 154 | puts("Ethernet: tx error\n"); |
| 155 | goto out; |
| 156 | } |
| 157 | } |
| 158 | result = txbuf[txIdx]->StatusWord; |
| 159 | txbuf[txIdx]->StatusWord = 0; |
| 160 | if ((txIdx + 1) >= TX_BUF_CNT) |
| 161 | txIdx = 0; |
| 162 | else |
| 163 | txIdx++; |
Mike Frysinger | b11eb3f | 2008-02-24 23:58:13 -0500 | [diff] [blame] | 164 | out: |
Mike Frysinger | 3ac20c3 | 2008-11-05 06:36:15 -0500 | [diff] [blame] | 165 | debug("BFIN EMAC send: length = %d\n", length); |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 166 | return result; |
| 167 | } |
| 168 | |
| 169 | static int bfin_EMAC_recv(struct eth_device *dev) |
| 170 | { |
| 171 | int length = 0; |
| 172 | |
| 173 | for (;;) { |
| 174 | if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) { |
| 175 | length = -1; |
| 176 | break; |
| 177 | } |
| 178 | if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) { |
| 179 | printf("Ethernet: rx dma overrun\n"); |
| 180 | break; |
| 181 | } |
| 182 | if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) { |
| 183 | printf("Ethernet: rx error\n"); |
| 184 | break; |
| 185 | } |
| 186 | length = rxbuf[rxIdx]->StatusWord & 0x000007FF; |
| 187 | if (length <= 4) { |
| 188 | printf("Ethernet: bad frame\n"); |
| 189 | break; |
| 190 | } |
Robin Getz | b5edf81 | 2009-08-24 10:33:39 -0400 | [diff] [blame] | 191 | |
| 192 | debug("%s: len = %d\n", __func__, length - 4); |
| 193 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 194 | NetRxPackets[rxIdx] = |
| 195 | (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest); |
| 196 | NetReceive(NetRxPackets[rxIdx], length - 4); |
| 197 | *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR; |
| 198 | rxbuf[rxIdx]->StatusWord = 0x00000000; |
| 199 | if ((rxIdx + 1) >= PKTBUFSRX) |
| 200 | rxIdx = 0; |
| 201 | else |
| 202 | rxIdx++; |
| 203 | } |
| 204 | |
| 205 | return length; |
| 206 | } |
| 207 | |
| 208 | /************************************************************** |
| 209 | * |
| 210 | * Ethernet Initialization Routine |
| 211 | * |
| 212 | *************************************************************/ |
| 213 | |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 214 | /* MDC = SCLK / MDC_freq / 2 - 1 */ |
| 215 | #define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1) |
| 216 | |
Mike Frysinger | eca7f57 | 2010-06-02 05:56:22 -0400 | [diff] [blame] | 217 | #ifndef CONFIG_BFIN_MAC_PINS |
| 218 | # ifdef CONFIG_RMII |
| 219 | # define CONFIG_BFIN_MAC_PINS P_RMII0 |
| 220 | # else |
| 221 | # define CONFIG_BFIN_MAC_PINS P_MII0 |
| 222 | # endif |
| 223 | #endif |
| 224 | |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 225 | static int bfin_miiphy_init(struct eth_device *dev, int *opmode) |
| 226 | { |
Mike Frysinger | eca7f57 | 2010-06-02 05:56:22 -0400 | [diff] [blame] | 227 | const unsigned short pins[] = CONFIG_BFIN_MAC_PINS; |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 228 | u16 phydat; |
| 229 | size_t count; |
| 230 | |
| 231 | /* Enable PHY output */ |
| 232 | *pVR_CTL |= CLKBUFOE; |
| 233 | |
| 234 | /* Set all the pins to peripheral mode */ |
Mike Frysinger | eca7f57 | 2010-06-02 05:56:22 -0400 | [diff] [blame] | 235 | peripheral_request_list(pins, "bfin_mac"); |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 236 | |
| 237 | /* Odd word alignment for Receive Frame DMA word */ |
| 238 | /* Configure checksum support and rcve frame word alignment */ |
Mike Frysinger | 65b7d93 | 2008-10-20 13:59:51 -0400 | [diff] [blame] | 239 | bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 240 | |
| 241 | /* turn on auto-negotiation and wait for link to come up */ |
Mike Frysinger | 65b7d93 | 2008-10-20 13:59:51 -0400 | [diff] [blame] | 242 | bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE); |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 243 | count = 0; |
| 244 | while (1) { |
| 245 | ++count; |
Mike Frysinger | 65b7d93 | 2008-10-20 13:59:51 -0400 | [diff] [blame] | 246 | if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat)) |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 247 | return -1; |
| 248 | if (phydat & BMSR_LSTATUS) |
| 249 | break; |
| 250 | if (count > 30000) { |
| 251 | printf("%s: link down, check cable\n", dev->name); |
| 252 | return -1; |
| 253 | } |
| 254 | udelay(100); |
| 255 | } |
| 256 | |
| 257 | /* see what kind of link we have */ |
Mike Frysinger | 65b7d93 | 2008-10-20 13:59:51 -0400 | [diff] [blame] | 258 | if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat)) |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 259 | return -1; |
| 260 | if (phydat & LPA_DUPLEX) |
| 261 | *opmode = FDMODE; |
| 262 | else |
| 263 | *opmode = 0; |
| 264 | |
| 265 | bfin_write_EMAC_MMC_CTL(RSTC | CROLL); |
| 266 | |
| 267 | /* Initialize the TX DMA channel registers */ |
| 268 | *pDMA2_X_COUNT = 0; |
| 269 | *pDMA2_X_MODIFY = 4; |
| 270 | *pDMA2_Y_COUNT = 0; |
| 271 | *pDMA2_Y_MODIFY = 0; |
| 272 | |
| 273 | /* Initialize the RX DMA channel registers */ |
| 274 | *pDMA1_X_COUNT = 0; |
| 275 | *pDMA1_X_MODIFY = 4; |
| 276 | *pDMA1_Y_COUNT = 0; |
| 277 | *pDMA1_Y_MODIFY = 0; |
| 278 | |
| 279 | return 0; |
| 280 | } |
| 281 | |
Mike Frysinger | 35be872 | 2010-04-27 14:15:28 -0400 | [diff] [blame] | 282 | static int bfin_EMAC_setup_addr(struct eth_device *dev) |
| 283 | { |
| 284 | *pEMAC_ADDRLO = |
| 285 | dev->enetaddr[0] | |
| 286 | dev->enetaddr[1] << 8 | |
| 287 | dev->enetaddr[2] << 16 | |
| 288 | dev->enetaddr[3] << 24; |
| 289 | *pEMAC_ADDRHI = |
| 290 | dev->enetaddr[4] | |
| 291 | dev->enetaddr[5] << 8; |
| 292 | return 0; |
| 293 | } |
| 294 | |
Mike Frysinger | b11eb3f | 2008-02-24 23:58:13 -0500 | [diff] [blame] | 295 | static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 296 | { |
| 297 | u32 opmode; |
| 298 | int dat; |
| 299 | int i; |
Mike Frysinger | 3ac20c3 | 2008-11-05 06:36:15 -0500 | [diff] [blame] | 300 | debug("Eth_init: ......\n"); |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 301 | |
| 302 | txIdx = 0; |
| 303 | rxIdx = 0; |
| 304 | |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 305 | /* Initialize System Register */ |
| 306 | if (bfin_miiphy_init(dev, &dat) < 0) |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 307 | return -1; |
| 308 | |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 309 | /* Initialize EMAC address */ |
Mike Frysinger | 35be872 | 2010-04-27 14:15:28 -0400 | [diff] [blame] | 310 | bfin_EMAC_setup_addr(dev); |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 311 | |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 312 | /* Initialize TX and RX buffer */ |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 313 | for (i = 0; i < PKTBUFSRX; i++) { |
| 314 | rxbuf[i] = SetupRxBuffer(i); |
| 315 | if (i > 0) { |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 316 | rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 317 | if (i == (PKTBUFSRX - 1)) |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 318 | rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 319 | } |
| 320 | } |
| 321 | for (i = 0; i < TX_BUF_CNT; i++) { |
| 322 | txbuf[i] = SetupTxBuffer(i); |
| 323 | if (i > 0) { |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 324 | txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 325 | if (i == (TX_BUF_CNT - 1)) |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 326 | txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 327 | } |
| 328 | } |
| 329 | |
| 330 | /* Set RX DMA */ |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 331 | *pDMA1_NEXT_DESC_PTR = rxbuf[0]->Dma; |
| 332 | *pDMA1_CONFIG = rxbuf[0]->Dma[0].CONFIG_DATA; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 333 | |
| 334 | /* Wait MII done */ |
Mike Frysinger | 709ad97 | 2008-10-14 04:52:00 -0400 | [diff] [blame] | 335 | bfin_miiphy_wait(); |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 336 | |
| 337 | /* We enable only RX here */ |
| 338 | /* ASTP : Enable Automatic Pad Stripping |
| 339 | PR : Promiscuous Mode for test |
| 340 | PSF : Receive frames with total length less than 64 bytes. |
| 341 | FDMODE : Full Duplex Mode |
| 342 | LB : Internal Loopback for test |
| 343 | RE : Receiver Enable */ |
| 344 | if (dat == FDMODE) |
| 345 | opmode = ASTP | FDMODE | PSF; |
| 346 | else |
| 347 | opmode = ASTP | PSF; |
| 348 | opmode |= RE; |
Mike Frysinger | d11ab93 | 2008-12-09 17:46:21 -0500 | [diff] [blame] | 349 | #ifdef CONFIG_RMII |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 350 | opmode |= TE | RMII; |
| 351 | #endif |
| 352 | /* Turn on the EMAC */ |
| 353 | *pEMAC_OPMODE = opmode; |
| 354 | return 0; |
| 355 | } |
| 356 | |
| 357 | static void bfin_EMAC_halt(struct eth_device *dev) |
| 358 | { |
Mike Frysinger | 3ac20c3 | 2008-11-05 06:36:15 -0500 | [diff] [blame] | 359 | debug("Eth_halt: ......\n"); |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 360 | /* Turn off the EMAC */ |
| 361 | *pEMAC_OPMODE = 0x00000000; |
| 362 | /* Turn off the EMAC RX DMA */ |
| 363 | *pDMA1_CONFIG = 0x0000; |
| 364 | *pDMA2_CONFIG = 0x0000; |
| 365 | |
| 366 | } |
| 367 | |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 368 | ADI_ETHER_BUFFER *SetupRxBuffer(int no) |
| 369 | { |
| 370 | ADI_ETHER_FRAME_BUFFER *frmbuf; |
| 371 | ADI_ETHER_BUFFER *buf; |
| 372 | int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */ |
| 373 | int total_size = nobytes_buffer + RECV_BUFSIZE; |
| 374 | |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 375 | buf = (void *) (RXBUF_BASE_ADDR + no * total_size); |
| 376 | frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer); |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 377 | |
| 378 | memset(buf, 0x00, nobytes_buffer); |
| 379 | buf->FrmData = frmbuf; |
| 380 | memset(frmbuf, 0xfe, RECV_BUFSIZE); |
| 381 | |
| 382 | /* set up first desc to point to receive frame buffer */ |
| 383 | buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]); |
| 384 | buf->Dma[0].START_ADDR = (u32) buf->FrmData; |
| 385 | buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */ |
| 386 | buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */ |
| 387 | buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ |
| 388 | buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */ |
| 389 | buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */ |
| 390 | |
| 391 | /* set up second desc to point to status word */ |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 392 | buf->Dma[1].NEXT_DESC_PTR = buf->Dma; |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 393 | buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum; |
| 394 | buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */ |
| 395 | buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */ |
| 396 | buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ |
| 397 | buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */ |
| 398 | buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */ |
| 399 | buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */ |
| 400 | |
| 401 | return buf; |
| 402 | } |
| 403 | |
| 404 | ADI_ETHER_BUFFER *SetupTxBuffer(int no) |
| 405 | { |
| 406 | ADI_ETHER_FRAME_BUFFER *frmbuf; |
| 407 | ADI_ETHER_BUFFER *buf; |
| 408 | int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */ |
| 409 | int total_size = nobytes_buffer + RECV_BUFSIZE; |
| 410 | |
Mike Frysinger | 10be09f | 2009-01-08 11:57:57 -0500 | [diff] [blame] | 411 | buf = (void *) (TXBUF_BASE_ADDR + no * total_size); |
| 412 | frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer); |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 413 | |
| 414 | memset(buf, 0x00, nobytes_buffer); |
| 415 | buf->FrmData = frmbuf; |
| 416 | memset(frmbuf, 0x00, RECV_BUFSIZE); |
| 417 | |
| 418 | /* set up first desc to point to receive frame buffer */ |
| 419 | buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]); |
| 420 | buf->Dma[0].START_ADDR = (u32) buf->FrmData; |
| 421 | buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */ |
| 422 | buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */ |
| 423 | buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ |
| 424 | buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */ |
| 425 | buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */ |
| 426 | |
| 427 | /* set up second desc to point to status word */ |
| 428 | buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]); |
| 429 | buf->Dma[1].START_ADDR = (u32) & buf->StatusWord; |
| 430 | buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */ |
| 431 | buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */ |
| 432 | buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ |
| 433 | buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */ |
| 434 | buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */ |
| 435 | buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */ |
| 436 | |
| 437 | return buf; |
| 438 | } |
| 439 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 440 | #if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER) |
Aubrey Li | 10ebdd9 | 2007-03-19 01:24:52 +0800 | [diff] [blame] | 441 | int ether_post_test(int flags) |
| 442 | { |
| 443 | uchar buf[64]; |
| 444 | int i, value = 0; |
| 445 | int length; |
| 446 | |
| 447 | printf("\n--------"); |
| 448 | bfin_EMAC_init(NULL, NULL); |
| 449 | /* construct the package */ |
| 450 | buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF); |
| 451 | buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8); |
| 452 | buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16); |
| 453 | buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24); |
| 454 | buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF); |
| 455 | buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8); |
| 456 | buf[12] = 0x08; /* Type: ARP */ |
| 457 | buf[13] = 0x06; |
| 458 | buf[14] = 0x00; /* Hardware type: Ethernet */ |
| 459 | buf[15] = 0x01; |
| 460 | buf[16] = 0x08; /* Protocal type: IP */ |
| 461 | buf[17] = 0x00; |
| 462 | buf[18] = 0x06; /* Hardware size */ |
| 463 | buf[19] = 0x04; /* Protocol size */ |
| 464 | buf[20] = 0x00; /* Opcode: request */ |
| 465 | buf[21] = 0x01; |
| 466 | |
| 467 | for (i = 0; i < 42; i++) |
| 468 | buf[i + 22] = i; |
| 469 | printf("--------Send 64 bytes......\n"); |
| 470 | bfin_EMAC_send(NULL, (volatile void *)buf, 64); |
| 471 | for (i = 0; i < 100; i++) { |
| 472 | udelay(10000); |
| 473 | if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) { |
| 474 | value = 1; |
| 475 | break; |
| 476 | } |
| 477 | } |
| 478 | if (value == 0) { |
| 479 | printf("--------EMAC can't receive any data\n"); |
| 480 | eth_halt(); |
| 481 | return -1; |
| 482 | } |
| 483 | length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4; |
| 484 | for (i = 0; i < length; i++) { |
| 485 | if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) { |
| 486 | printf("--------EMAC receive error data!\n"); |
| 487 | eth_halt(); |
| 488 | return -1; |
| 489 | } |
| 490 | } |
| 491 | printf("--------receive %d bytes, matched\n", length); |
| 492 | bfin_EMAC_halt(NULL); |
| 493 | return 0; |
| 494 | } |
| 495 | #endif |