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git01.mediatek.com / filogic / uboot / 28debca01b71441e96bc2db34181924c3122e9e4 / . / arch / arm / dts / imx8mm-venice-gw7903.dts
blob: 1b69ac0e12b073ceee2c6cd0fcea51ef9e90fbd5 [file] [log] [blame]
Tim Harvey5cc5e192022-02-18 15:19:33 -0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12
13#include "imx8mm.dtsi"
14
15/ {
16 model = "Gateworks Venice GW7903 i.MX8MM board";
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
18
19 aliases {
20 ethernet0 = &fec1;
21 usb0 = &usbotg1;
22 };
23
24 chosen {
25 stdout-path = &uart2;
26 };
27
28 memory@40000000 {
29 device_type = "memory";
30 reg = <0x0 0x40000000 0 0x80000000>;
31 };
32
33 gpio-keys {
34 compatible = "gpio-keys";
35
36 user-pb {
37 label = "user_pb";
38 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
39 linux,code = <BTN_0>;
40 };
41
42 user-pb1x {
43 label = "user_pb1x";
44 linux,code = <BTN_1>;
45 interrupt-parent = <&gsc>;
46 interrupts = <0>;
47 };
48
49 key-erased {
50 label = "key_erased";
51 linux,code = <BTN_2>;
52 interrupt-parent = <&gsc>;
53 interrupts = <1>;
54 };
55
56 eeprom-wp {
57 label = "eeprom_wp";
58 linux,code = <BTN_3>;
59 interrupt-parent = <&gsc>;
60 interrupts = <2>;
61 };
62
63 switch-hold {
64 label = "switch_hold";
65 linux,code = <BTN_5>;
66 interrupt-parent = <&gsc>;
67 interrupts = <7>;
68 };
69 };
70
71 led-controller {
72 compatible = "gpio-leds";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpio_leds>;
75
76 led-0 {
77 function = LED_FUNCTION_STATUS;
78 color = <LED_COLOR_ID_RED>;
79 label = "led01_red";
80 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
81 default-state = "off";
82 };
83
84 led-1 {
85 function = LED_FUNCTION_STATUS;
86 color = <LED_COLOR_ID_GREEN>;
87 label = "led01_grn";
88 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
89 default-state = "off";
90 };
91
92 led-2 {
93 function = LED_FUNCTION_STATUS;
94 color = <LED_COLOR_ID_RED>;
95 label = "led02_red";
96 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
97 default-state = "off";
98 };
99
100 led-3 {
101 function = LED_FUNCTION_STATUS;
102 color = <LED_COLOR_ID_GREEN>;
103 label = "led02_grn";
104 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
105 default-state = "off";
106 };
107
108 led-4 {
109 function = LED_FUNCTION_STATUS;
110 color = <LED_COLOR_ID_RED>;
111 label = "led03_red";
112 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
113 default-state = "off";
114 };
115
116 led-5 {
117 function = LED_FUNCTION_STATUS;
118 color = <LED_COLOR_ID_GREEN>;
119 label = "led03_grn";
120 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
121 default-state = "off";
122 };
123
124 led-6 {
125 function = LED_FUNCTION_STATUS;
126 color = <LED_COLOR_ID_RED>;
127 label = "led04_red";
128 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
129 default-state = "off";
130 };
131
132 led-7 {
133 function = LED_FUNCTION_STATUS;
134 color = <LED_COLOR_ID_GREEN>;
135 label = "led04_grn";
136 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
137 default-state = "off";
138 };
139
140 led-8 {
141 function = LED_FUNCTION_STATUS;
142 color = <LED_COLOR_ID_RED>;
143 label = "led05_red";
144 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
145 default-state = "off";
146 };
147
148 led-9 {
149 function = LED_FUNCTION_STATUS;
150 color = <LED_COLOR_ID_GREEN>;
151 label = "led05_grn";
152 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
153 default-state = "off";
154 };
155
156 led-a {
157 function = LED_FUNCTION_STATUS;
158 color = <LED_COLOR_ID_RED>;
159 label = "led06_red";
160 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
161 default-state = "off";
162 };
163
164 led-b {
165 function = LED_FUNCTION_STATUS;
166 color = <LED_COLOR_ID_GREEN>;
167 label = "led06_grn";
168 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
169 default-state = "off";
170 };
171 };
172
173 pcie0_refclk: pcie0-refclk {
174 compatible = "fixed-clock";
175 #clock-cells = <0>;
176 clock-frequency = <100000000>;
177 };
178
179 reg_3p3v: regulator-3p3v {
180 compatible = "regulator-fixed";
181 regulator-name = "3P3V";
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
184 regulator-always-on;
185 };
186};
187
188&A53_0 {
189 cpu-supply = <&buck2>;
190};
191
192&A53_1 {
193 cpu-supply = <&buck2>;
194};
195
196&A53_2 {
197 cpu-supply = <&buck2>;
198};
199
200&A53_3 {
201 cpu-supply = <&buck2>;
202};
203
204&ddrc {
205 operating-points-v2 = <&ddrc_opp_table>;
206
207 ddrc_opp_table: opp-table {
208 compatible = "operating-points-v2";
209
210 opp-25M {
211 opp-hz = /bits/ 64 <25000000>;
212 };
213
214 opp-100M {
215 opp-hz = /bits/ 64 <100000000>;
216 };
217
218 opp-750M {
219 opp-hz = /bits/ 64 <750000000>;
220 };
221 };
222};
223
224&fec1 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_fec1>;
227 phy-mode = "rgmii-id";
228 phy-handle = <&ethphy0>;
229 local-mac-address = [00 00 00 00 00 00];
230 status = "okay";
231
232 mdio {
233 #address-cells = <1>;
234 #size-cells = <0>;
235
236 ethphy0: ethernet-phy@0 {
237 compatible = "ethernet-phy-ieee802.3-c22";
238 reg = <0>;
239 rx-internal-delay-ps = <2000>;
240 tx-internal-delay-ps = <2500>;
241 };
242 };
243};
244
245&gpio1 {
246 gpio-line-names = "", "", "", "", "", "", "", "",
247 "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
248 "", "", "", "", "", "", "", "",
249 "", "", "", "", "", "", "", "";
250};
251
252&gpio2 {
Tim Harvey28debca2022-09-09 15:58:42 -0700[diff] [blame^]253 gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "",
Tim Harvey5cc5e192022-02-18 15:19:33 -0800[diff] [blame]254 "dig1_out#", "dig1_in", "", "", "", "", "", "",
255 "", "", "", "", "", "", "", "",
256 "", "", "", "", "", "", "", "";
257};
258
259&gpio5 {
260 gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
261 "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
262 "", "", "", "", "", "", "", "",
263 "", "", "", "", "", "", "", "";
264};
265
266&i2c1 {
267 clock-frequency = <100000>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_i2c1>;
270 status = "okay";
271
272 gsc: gsc@20 {
273 compatible = "gw,gsc";
274 reg = <0x20>;
275 pinctrl-0 = <&pinctrl_gsc>;
276 interrupt-parent = <&gpio4>;
277 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
278 interrupt-controller;
279 #interrupt-cells = <1>;
280
281 adc {
282 compatible = "gw,gsc-adc";
283 #address-cells = <1>;
284 #size-cells = <0>;
285
286 channel@6 {
287 gw,mode = <0>;
288 reg = <0x06>;
289 label = "temp";
290 };
291
292 channel@8 {
293 gw,mode = <1>;
294 reg = <0x08>;
295 label = "vdd_bat";
296 };
297
298 channel@82 {
299 gw,mode = <2>;
300 reg = <0x82>;
301 label = "vin";
302 gw,voltage-divider-ohms = <22100 1000>;
303 gw,voltage-offset-microvolt = <700000>;
304 };
305
306 channel@84 {
307 gw,mode = <2>;
308 reg = <0x84>;
309 label = "vdd_5p0";
310 gw,voltage-divider-ohms = <10000 10000>;
311 };
312
313 channel@86 {
314 gw,mode = <2>;
315 reg = <0x86>;
316 label = "vdd_3p3";
317 gw,voltage-divider-ohms = <10000 10000>;
318 };
319
320 channel@88 {
321 gw,mode = <2>;
322 reg = <0x88>;
323 label = "vdd_0p9";
324 };
325
326 channel@8c {
327 gw,mode = <2>;
328 reg = <0x8c>;
329 label = "vdd_soc";
330 };
331
332 channel@8e {
333 gw,mode = <2>;
334 reg = <0x8e>;
335 label = "vdd_arm";
336 };
337
338 channel@90 {
339 gw,mode = <2>;
340 reg = <0x90>;
341 label = "vdd_1p8";
342 };
343
344 channel@92 {
345 gw,mode = <2>;
346 reg = <0x92>;
347 label = "vdd_dram";
348 };
349
350 channel@a2 {
351 gw,mode = <2>;
352 reg = <0xa2>;
353 label = "vdd_gsc";
354 gw,voltage-divider-ohms = <10000 10000>;
355 };
356 };
357 };
358
359 gpio: gpio@23 {
360 compatible = "nxp,pca9555";
361 reg = <0x23>;
362 gpio-controller;
363 #gpio-cells = <2>;
364 interrupt-parent = <&gsc>;
365 interrupts = <4>;
366 };
367
368 eeprom@50 {
369 compatible = "atmel,24c02";
370 reg = <0x50>;
371 pagesize = <16>;
372 };
373
374 eeprom@51 {
375 compatible = "atmel,24c02";
376 reg = <0x51>;
377 pagesize = <16>;
378 };
379
380 eeprom@52 {
381 compatible = "atmel,24c02";
382 reg = <0x52>;
383 pagesize = <16>;
384 };
385
386 eeprom@53 {
387 compatible = "atmel,24c02";
388 reg = <0x53>;
389 pagesize = <16>;
390 };
391
392 rtc@68 {
393 compatible = "dallas,ds1672";
394 reg = <0x68>;
395 };
396};
397
398&i2c2 {
399 clock-frequency = <400000>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_i2c2>;
402 status = "okay";
403
404 pmic@4b {
405 compatible = "rohm,bd71847";
406 reg = <0x4b>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_pmic>;
409 interrupt-parent = <&gpio3>;
410 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
411 rohm,reset-snvs-powered;
412 #clock-cells = <0>;
413 clocks = <&osc_32k 0>;
414 clock-output-names = "clk-32k-out";
415
416 regulators {
417 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
418 BUCK1 {
419 regulator-name = "buck1";
420 regulator-min-microvolt = <700000>;
421 regulator-max-microvolt = <1300000>;
422 regulator-boot-on;
423 regulator-always-on;
424 regulator-ramp-delay = <1250>;
425 };
426
427 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
428 buck2: BUCK2 {
429 regulator-name = "buck2";
430 regulator-min-microvolt = <700000>;
431 regulator-max-microvolt = <1300000>;
432 regulator-boot-on;
433 regulator-always-on;
434 regulator-ramp-delay = <1250>;
435 rohm,dvs-run-voltage = <1000000>;
436 rohm,dvs-idle-voltage = <900000>;
437 };
438
439 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
440 BUCK3 {
441 regulator-name = "buck3";
442 regulator-min-microvolt = <700000>;
443 regulator-max-microvolt = <1350000>;
444 regulator-boot-on;
445 regulator-always-on;
446 };
447
448 /* vdd_3p3 */
449 BUCK4 {
450 regulator-name = "buck4";
451 regulator-min-microvolt = <3000000>;
452 regulator-max-microvolt = <3300000>;
453 regulator-boot-on;
454 regulator-always-on;
455 };
456
457 /* vdd_1p8 */
458 BUCK5 {
459 regulator-name = "buck5";
460 regulator-min-microvolt = <1605000>;
461 regulator-max-microvolt = <1995000>;
462 regulator-boot-on;
463 regulator-always-on;
464 };
465
466 /* vdd_dram */
467 BUCK6 {
468 regulator-name = "buck6";
469 regulator-min-microvolt = <800000>;
470 regulator-max-microvolt = <1400000>;
471 regulator-boot-on;
472 regulator-always-on;
473 };
474
475 /* nvcc_snvs_1p8 */
476 LDO1 {
477 regulator-name = "ldo1";
478 regulator-min-microvolt = <1600000>;
479 regulator-max-microvolt = <1900000>;
480 regulator-boot-on;
481 regulator-always-on;
482 };
483
484 /* vdd_snvs_0p8 */
485 LDO2 {
486 regulator-name = "ldo2";
487 regulator-min-microvolt = <800000>;
488 regulator-max-microvolt = <900000>;
489 regulator-boot-on;
490 regulator-always-on;
491 };
492
493 /* vdda_1p8 */
494 LDO3 {
495 regulator-name = "ldo3";
496 regulator-min-microvolt = <1800000>;
497 regulator-max-microvolt = <3300000>;
498 regulator-boot-on;
499 regulator-always-on;
500 };
501
502 LDO4 {
503 regulator-name = "ldo4";
504 regulator-min-microvolt = <900000>;
505 regulator-max-microvolt = <1800000>;
506 regulator-boot-on;
507 regulator-always-on;
508 };
509
510 LDO6 {
511 regulator-name = "ldo6";
512 regulator-min-microvolt = <900000>;
513 regulator-max-microvolt = <1800000>;
514 regulator-boot-on;
515 regulator-always-on;
516 };
517 };
518 };
519};
520
521&i2c3 {
522 clock-frequency = <400000>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_i2c3>;
525 status = "okay";
526
527 accelerometer@19 {
528 pinctrl-names = "default";
529 pinctrl-0 = <&pinctrl_accel>;
530 compatible = "st,lis2de12";
531 reg = <0x19>;
532 st,drdy-int-pin = <1>;
533 interrupt-parent = <&gpio1>;
534 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
535 interrupt-names = "INT1";
536 };
537};
538
539&pcie_phy {
540 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
541 fsl,clkreq-unsupported;
542 clocks = <&pcie0_refclk>;
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]543 clock-names = "ref";
Tim Harvey5cc5e192022-02-18 15:19:33 -0800[diff] [blame]544 status = "okay";
545};
546
547&pcie0 {
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_pcie0>;
550 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
551 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
552 <&pcie0_refclk>;
553 clock-names = "pcie", "pcie_aux", "pcie_bus";
554 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
555 <&clk IMX8MM_CLK_PCIE1_CTRL>;
556 assigned-clock-rates = <10000000>, <250000000>;
557 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
558 <&clk IMX8MM_SYS_PLL2_250M>;
559 status = "okay";
560};
561
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]562&pgc_mipi {
563 status = "disabled";
564};
565
Tim Harvey5cc5e192022-02-18 15:19:33 -0800[diff] [blame]566/* off-board RS232/RS485/RS422 */
567&uart1 {
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_uart1>;
570 cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
571 rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
572 dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
573 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
574 dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
575 uart-has-rtscts;
576 status = "okay";
577};
578
579/* console */
580&uart2 {
581 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_uart2>;
583 status = "okay";
584};
585
586&usbotg1 {
587 dr_mode = "host";
588 disable-over-current;
589 status = "okay";
590};
591
592/* microSD */
593&usdhc2 {
594 pinctrl-names = "default", "state_100mhz", "state_200mhz";
595 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
596 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
597 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
598 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
599 bus-width = <4>;
600 vmmc-supply = <&reg_3p3v>;
601 status = "okay";
602};
603
604/* eMMC */
605&usdhc3 {
606 pinctrl-names = "default", "state_100mhz", "state_200mhz";
607 pinctrl-0 = <&pinctrl_usdhc3>;
608 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
609 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
610 bus-width = <8>;
611 non-removable;
612 status = "okay";
613};
614
615&wdog1 {
616 pinctrl-names = "default";
617 pinctrl-0 = <&pinctrl_wdog>;
618 fsl,ext-reset-output;
619 status = "okay";
620};
621
622&iomuxc {
623 pinctrl-names = "default";
624 pinctrl-0 = <&pinctrl_hog>;
625
626 pinctrl_hog: hoggrp {
627 fsl,pins = <
628 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
629 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
630 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
631 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
632 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
Tim Harvey28debca2022-09-09 15:58:42 -0700[diff] [blame^]633 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */
634 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */
Tim Harvey5cc5e192022-02-18 15:19:33 -0800[diff] [blame]635 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
636 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
637 MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
638 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */
639 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */
640 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
641 >;
642 };
643
644 pinctrl_accel: accelgrp {
645 fsl,pins = <
646 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
647 >;
648 };
649
650 pinctrl_fec1: fec1grp {
651 fsl,pins = <
652 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
653 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
654 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
655 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
656 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
657 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
658 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
659 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
660 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
661 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
662 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
663 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
664 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
665 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
666 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
667 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
668 >;
669 };
670
671 pinctrl_gsc: gscgrp {
672 fsl,pins = <
673 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
674 >;
675 };
676
677 pinctrl_i2c1: i2c1grp {
678 fsl,pins = <
679 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
680 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
681 >;
682 };
683
684 pinctrl_i2c2: i2c2grp {
685 fsl,pins = <
686 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
687 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
688 >;
689 };
690
691 pinctrl_i2c3: i2c3grp {
692 fsl,pins = <
693 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
694 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
695 >;
696 };
697
698 pinctrl_gpio_leds: gpioledgrp {
699 fsl,pins = <
700 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
701 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
702 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
703 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
704 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
705 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19
706 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
707 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
708 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
709 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
710 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
711 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
712 >;
713 };
714
715 pinctrl_pcie0: pciegrp {
716 fsl,pins = <
717 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
718 >;
719 };
720
721 pinctrl_pmic: pmicgrp {
722 fsl,pins = <
723 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
724 >;
725 };
726
727 pinctrl_uart1: uart1grp {
728 fsl,pins = <
729 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
730 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
731 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
732 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
733 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
734 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140
735 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140
736 >;
737 };
738
739 pinctrl_uart2: uart2grp {
740 fsl,pins = <
741 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
742 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
743 >;
744 };
745
746 pinctrl_usdhc2: usdhc2grp {
747 fsl,pins = <
748 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
749 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
750 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
751 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
752 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
753 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
754 >;
755 };
756
757 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
758 fsl,pins = <
759 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
760 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
761 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
762 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
763 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
764 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
765 >;
766 };
767
768 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
769 fsl,pins = <
770 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
771 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
772 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
773 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
774 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
775 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
776 >;
777 };
778
779 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
780 fsl,pins = <
781 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
782 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
783 >;
784 };
785
786 pinctrl_usdhc3: usdhc3grp {
787 fsl,pins = <
788 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
789 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
790 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
791 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
792 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
793 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
794 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
795 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
796 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
797 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
798 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
799 >;
800 };
801
802 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
803 fsl,pins = <
804 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
805 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
806 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
807 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
808 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
809 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
810 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
811 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
812 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
813 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
814 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
815 >;
816 };
817
818 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
819 fsl,pins = <
820 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
821 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
822 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
823 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
824 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
825 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
826 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
827 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
828 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
829 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
830 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
831 >;
832 };
833
834 pinctrl_wdog: wdoggrp {
835 fsl,pins = <
836 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
837 >;
838 };
839};