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git01.mediatek.com / filogic / uboot / 28d261ff50b9438e031d8b68f995eab9269045b3 / . / arch / arm / dts / imx53-cx9020.dts
blob: e08850999b1b02a46833384eb54ee0587e89f378 [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]2/*
3 * Copyright 2016 Beckhoff Automation
4 * Copyright 2011 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]6 */
7
8/dts-v1/;
9#include "imx53.dtsi"
10
11#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0
12#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0
13#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0
14#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0
15
16/ {
17 model = "Beckhoff CX9020-0100 i.MX53";
18 compatible = "fsl,imx53-qsb", "fsl,imx53";
19
20 chosen {
21 stdout-path = &uart2;
22 };
23};
24
25&iomuxc {
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_hog>;
28
29 imx53-qsb {
30 pinctrl_hog: hoggrp {
31 fsl,pins = <
32 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
33 MX53_PAD_GPIO_8__GPIO1_8 0x80000000
34 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
35 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
36 MX53_PAD_GPIO_1__GPIO1_1 0x80000000
37 MX53_PAD_GPIO_4__GPIO1_4 0x80000000
38 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]39 MX53_PAD_GPIO_16__GPIO7_11 0x80000000
40
41 MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
42 MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x80000000
43 MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x80000000
44 MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
45 MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x80000000
46 MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x80000000
47 MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x80000000
48 MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x80000000
49 MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x80000000
50 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
51 MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x80000000
52 MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x80000000
53 MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x80000000
54 MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x80000000
55 MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x80000000
56 MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x80000000
57 MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x80000000
58 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4
59 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4
60 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4
61 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4
62 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4
63 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4
64 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4
65 MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
66 MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0xa4
67 MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0xa4
68 MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0xa4
69 MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0xa4
70 MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0xa4
71 MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0xa4
72 MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0xa4
73 MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0xa4
74 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
75 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
76 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
77 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
78 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
79 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
80 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
81 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
82 MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0xa4
83 MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0xa4
84 MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0xa4
85 MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0xa4
86 MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0xa4
87 MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0xa4
88 MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0xa4
89 MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0xa4
90 MX53_PAD_NANDF_CLE__GPIO6_7 0x00000001
91 MX53_PAD_NANDF_WP_B__GPIO6_9 0x00000001
92 MX53_PAD_NANDF_ALE__GPIO6_8 0x00000001
93
94 MX53_PAD_EIM_D23__GPIO3_23 0x80000000
95
96 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
97 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
98 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
99 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
100
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]101 MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
102 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
103
104 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
105 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
106
107 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
108 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
109 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
110 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
111 MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
112 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
113 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
114 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
115 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
116 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
117 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
118 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
119 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
120 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
121 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
122 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
123 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
124 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
125 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
126 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
127 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
128 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
129 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
130 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
131 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
132 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
133 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
134 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
135 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
136 >;
137 };
138
Steffen Dirkwinkel9cd396f2019-10-23 07:40:40 +0200[diff] [blame]139 pinctrl_fec0: fec0grp {
140 fsl,pins = <
141 MX53_PAD_FEC_MDC__FEC_MDC 0x4
142 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
143 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
144 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
145 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
146 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
147 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
148 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
149 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
150 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
151 >;
152 };
153
Patrick Bruennc9ea8362019-01-03 07:54:34 +0100[diff] [blame]154 pinctrl_esdhc1: esdhc1grp {
155 fsl,pins = <
156 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
157 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
158 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
159 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
160 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
161 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
162 >;
163 };
164
165 pinctrl_esdhc2: esdhc2grp {
166 fsl,pins = <
167 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
168 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
169 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
170 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
171 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
172 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
173 >;
174 };
175
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]176 pinctrl_uart2: uart2grp {
177 fsl,pins = <
178 MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
179 MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
180 MX53_PAD_EIM_D28__UART2_RTS 0x1e4
181 MX53_PAD_EIM_D29__UART2_CTS 0x1e4
182 >;
183 };
184 };
185};
186
187&uart2 {
188 pinctrl-names = "default";
189 uart-has-rtscts;
190 fsl,dte-mode;
191 pinctrl-0 = <&pinctrl_uart2>;
192 status = "okay";
193};
194
Patrick Bruennc9ea8362019-01-03 07:54:34 +0100[diff] [blame]195&esdhc1 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_esdhc1>;
198 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
199 bus-width = <4>;
200 status = "okay";
201};
202
203&esdhc2 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_esdhc2>;
206 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
207 bus-width = <4>;
208 status = "okay";
209};
210
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]211&fec {
212 pinctrl-names = "default";
213 phy-mode = "rmii";
214 phy-reset-gpios = <&gpio7 6 0>;
Steffen Dirkwinkel9cd396f2019-10-23 07:40:40 +0200[diff] [blame]215 pinctrl-0 = <&pinctrl_fec0>;
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]216 status = "okay";
Steffen Dirkwinkel9cd396f2019-10-23 07:40:40 +0200[diff] [blame]217 fixed-link { /* RMII fixed link to KZ8863 */
218 speed = <100>;
219 full-duplex;
220 };
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]221};
Steffen Dirkwinkelcfe54da2019-10-23 07:40:41 +0200[diff] [blame]222
223&usbh1 {
224 phy_type = "utmi";
225 status = "okay";
226};
227
228&usbotg {
229 dr_mode = "host";
230 status = "okay";
231};