| Simon Glass | 355ec12 | 2019-01-11 18:37:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * max98088.h -- MAX98088 ALSA SoC Audio driver |
| 4 | * |
| 5 | * Copyright 2010 Maxim Integrated Products |
| 6 | */ |
| 7 | |
| 8 | #ifndef _MAX98088_H |
| 9 | #define _MAX98088_H |
| 10 | |
| 11 | /* MAX98088 Registers Definition */ |
| 12 | #define M98088_REG_IRQ_STATUS 0x00 |
| 13 | #define M98088_REG_MIC_STATUS 0x01 |
| 14 | #define M98088_REG_JACK_STAUS 0x02 |
| 15 | #define M98088_REG_BATTERY_VOLTAGE 0x03 |
| 16 | #define M98088_REG_IRQ_ENABLE 0x0f |
| 17 | #define M98088_REG_SYS_CLK 0X10 |
| 18 | #define M98088_REG_DAI1_CLKMODE 0x11 |
| 19 | #define M98088_REG_DAI1_CLKCFG_HI 0x12 |
| 20 | #define M98088_REG_DAI1_CLKCFG_LO 0x13 |
| 21 | #define M98088_REG_DAI1_FORMAT 0x14 |
| 22 | #define M98088_REG_DAI1_CLOCK 0x15 |
| 23 | #define M98088_REG_DAI1_IOCFG 0x16 |
| 24 | #define M98088_REG_DAI1_TDM 0X17 |
| 25 | #define M98088_REG_DAI1_FILTERS 0x18 |
| 26 | #define M98088_REG_DAI2_CLKMODE 0x19 |
| 27 | #define M98088_REG_DAI2_CLKCFG_HI 0x1a |
| 28 | #define M98088_REG_DAI2_CLKCFG_LO 0x1b |
| 29 | #define M98088_REG_DAI2_FORMAT 0x1c |
| 30 | #define M98088_REG_DAI2_CLOCK 0x1d |
| 31 | #define M98088_REG_DAI2_IOCFG 0x1e |
| 32 | #define M98088_REG_DAI2_TDM 0X1f |
| 33 | #define M98088_REG_DAI2_FILTERS 0x20 |
| 34 | #define M98088_REG_SRC 0X21 |
| 35 | #define M98088_REG_MIX_DAC 0X22 |
| 36 | #define M98088_REG_MIX_ADC_LEFT 0x23 |
| 37 | #define M98088_REG_MIX_ADC_RIGHT 0x24 |
| 38 | #define M98088_REG_MIX_HP_LEFT 0x25 |
| 39 | #define M98088_REG_MIX_HP_RIGHT 0x26 |
| 40 | #define M98088_REG_MIX_HP_CNTL 0x27 |
| 41 | #define M98088_REG_MIX_REC_LEFT 0x28 |
| 42 | #define M98088_REG_MIX_REC_RIGHT 0x29 |
| 43 | #define M98088_REG_MIC_REC_CNTL 0x2a |
| 44 | #define M98088_REG_MIX_SPK_LEFT 0x2b |
| 45 | #define M98088_REG_MIX_SPK_RIGHT 0x2c |
| 46 | #define M98088_REG_MIX_SPK_CNTL 0x2d |
| 47 | #define M98088_REG_LVL_SIDETONE 0x2e |
| 48 | #define M98088_REG_LVL_DAI1_PLAY 0x2f |
| 49 | #define M98088_REG_LVL_DAI1_PLAY_EQ 0x30 |
| 50 | #define M98088_REG_LVL_DAI2_PLAY 0x31 |
| 51 | #define M98088_REG_LVL_DAI2_PLAY_EQ 0x32 |
| 52 | #define M98088_REG_LVL_ADC_L 0X33 |
| 53 | #define M98088_REG_LVL_ADC_R 0X34 |
| 54 | #define M98088_REG_LVL_MIC1 0X35 |
| 55 | #define M98088_REG_LVL_MIC2 0X36 |
| 56 | #define M98088_REG_LVL_INA 0X37 |
| 57 | #define M98088_REG_LVL_INB 0X38 |
| 58 | #define M98088_REG_LVL_HP_L 0X39 |
| 59 | #define M98088_REG_LVL_HP_R 0X3a |
| 60 | #define M98088_REG_LVL_REC_L 0X3b |
| 61 | #define M98088_REG_LVL_REC_R 0X3c |
| 62 | #define M98088_REG_LVL_SPK_L 0X3d |
| 63 | #define M98088_REG_LVL_SPK_R 0X3e |
| 64 | #define M98088_REG_MICAGC_CFG 0x3f |
| 65 | #define M98088_REG_MICAGC_THRESH 0x40 |
| 66 | #define M98088_REG_SPKDHP 0X41 |
| 67 | #define M98088_REG_SPKDHP_THRESH 0x42 |
| 68 | #define M98088_REG_SPKALC_COMP 0x43 |
| 69 | #define M98088_REG_PWRLMT_CFG 0x44 |
| 70 | #define M98088_REG_PWRLMT_TIME 0x45 |
| 71 | #define M98088_REG_THDLMT_CFG 0x46 |
| 72 | #define M98088_REG_CFG_AUDIO_IN 0x47 |
| 73 | #define M98088_REG_CFG_MIC 0X48 |
| 74 | #define M98088_REG_CFG_LEVEL 0X49 |
| 75 | #define M98088_REG_CFG_BYPASS 0x4a |
| 76 | #define M98088_REG_CFG_JACKDET 0x4b |
| 77 | #define M98088_REG_PWR_EN_IN 0X4c |
| 78 | #define M98088_REG_PWR_EN_OUT 0x4d |
| 79 | #define M98088_REG_BIAS_CNTL 0X4e |
| 80 | #define M98088_REG_DAC_BIAS1 0X4f |
| 81 | #define M98088_REG_DAC_BIAS2 0X50 |
| 82 | #define M98088_REG_PWR_SYS 0X51 |
| 83 | #define M98088_REG_DAI1_EQ_BASE 0x52 |
| 84 | #define M98088_REG_DAI2_EQ_BASE 0x84 |
| 85 | #define M98088_REG_DAI1_BIQUAD_BASE 0xb6 |
| 86 | #define M98088_REG_DAI2_BIQUAD_BASE 0xc0 |
| 87 | #define M98088_REG_REV_ID 0xff |
| 88 | |
| 89 | #define M98088_REG_CNT (0xff + 1) |
| 90 | |
| 91 | /* MAX98088 Registers Bit Fields */ |
| 92 | |
| 93 | /* M98088_REG_11_DAI1_CLKMODE, M98088_REG_19_DAI2_CLKMODE */ |
| 94 | #define M98088_CLKMODE_MASK 0xFF |
| 95 | |
| 96 | /* M98088_REG_14_DAI1_FORMAT, M98088_REG_1C_DAI2_FORMAT */ |
| 97 | #define M98088_DAI_MAS BIT(7) |
| 98 | #define M98088_DAI_WCI BIT(6) |
| 99 | #define M98088_DAI_BCI BIT(5) |
| 100 | #define M98088_DAI_DLY BIT(4) |
| 101 | #define M98088_DAI_TDM BIT(2) |
| 102 | #define M98088_DAI_FSW BIT(1) |
| 103 | #define M98088_DAI_WS BIT(0) |
| 104 | |
| 105 | /* M98088_REG_15_DAI1_CLOCK, M98088_REG_1D_DAI2_CLOCK */ |
| 106 | #define M98088_DAI_BSEL64 BIT(0) |
| 107 | #define M98088_DAI_OSR64 BIT(6) |
| 108 | |
| 109 | /* M98088_REG_16_DAI1_IOCFG, M98088_REG_1E_DAI2_IOCFG */ |
| 110 | #define M98088_S1NORMAL BIT(6) |
| 111 | #define M98088_S2NORMAL (2 << 6) |
| 112 | #define M98088_SDATA (3 << 0) |
| 113 | |
| 114 | /* M98088_REG_18_DAI1_FILTERS, M98088_REG_20_DAI2_FILTERS */ |
| 115 | #define M98088_DAI_DHF BIT(3) |
| 116 | |
| 117 | /* M98088_REG_22_MIX_DAC */ |
| 118 | #define M98088_DAI1L_TO_DACL BIT(7) |
| 119 | #define M98088_DAI1R_TO_DACL BIT(6) |
| 120 | #define M98088_DAI2L_TO_DACL BIT(5) |
| 121 | #define M98088_DAI2R_TO_DACL BIT(4) |
| 122 | #define M98088_DAI1L_TO_DACR BIT(3) |
| 123 | #define M98088_DAI1R_TO_DACR BIT(2) |
| 124 | #define M98088_DAI2L_TO_DACR BIT(1) |
| 125 | #define M98088_DAI2R_TO_DACR BIT(0) |
| 126 | |
| 127 | /* M98088_REG_2A_MIC_REC_CNTL */ |
| 128 | #define M98088_REC_LINEMODE BIT(7) |
| 129 | #define M98088_REC_LINEMODE_MASK BIT(7) |
| 130 | |
| 131 | /* M98088_REG_2D_MIX_SPK_CNTL */ |
| 132 | #define M98088_MIX_SPKR_GAIN_MASK (3 << 2) |
| 133 | #define M98088_MIX_SPKR_GAIN_SHIFT 2 |
| 134 | #define M98088_MIX_SPKL_GAIN_MASK (3 << 0) |
| 135 | #define M98088_MIX_SPKL_GAIN_SHIFT 0 |
| 136 | |
| 137 | /* M98088_REG_2F_LVL_DAI1_PLAY, M98088_REG_31_LVL_DAI2_PLAY */ |
| 138 | #define M98088_DAI_MUTE BIT(7) |
| 139 | #define M98088_DAI_MUTE_MASK BIT(7) |
| 140 | #define M98088_DAI_VOICE_GAIN_MASK (3 << 4) |
| 141 | #define M98088_DAI_ATTENUATION_MASK (0xf << 0) |
| 142 | #define M98088_DAI_ATTENUATION_SHIFT 0 |
| 143 | |
| 144 | /* M98088_REG_35_LVL_MIC1, M98088_REG_36_LVL_MIC2 */ |
| 145 | #define M98088_MICPRE_MASK (3 << 5) |
| 146 | #define M98088_MICPRE_SHIFT 5 |
| 147 | |
| 148 | /* M98088_REG_3A_LVL_HP_R */ |
| 149 | #define M98088_HP_MUTE BIT(7) |
| 150 | |
| 151 | /* M98088_REG_3C_LVL_REC_R */ |
| 152 | #define M98088_REC_MUTE BIT(7) |
| 153 | |
| 154 | /* M98088_REG_3E_LVL_SPK_R */ |
| 155 | #define M98088_SP_MUTE BIT(7) |
| 156 | |
| 157 | /* M98088_REG_48_CFG_MIC */ |
| 158 | #define M98088_EXTMIC_MASK (3 << 0) |
| 159 | #define M98088_DIGMIC_L BIT(5) |
| 160 | #define M98088_DIGMIC_R BIT(4) |
| 161 | |
| 162 | /* M98088_REG_49_CFG_LEVEL */ |
| 163 | #define M98088_VSEN BIT(6) |
| 164 | #define M98088_ZDEN BIT(5) |
| 165 | #define M98088_EQ2EN BIT(1) |
| 166 | #define M98088_EQ1EN BIT(0) |
| 167 | |
| 168 | /* M98088_REG_4C_PWR_EN_IN */ |
| 169 | #define M98088_INAEN BIT(7) |
| 170 | #define M98088_INBEN BIT(6) |
| 171 | #define M98088_MBEN BIT(3) |
| 172 | #define M98088_ADLEN BIT(1) |
| 173 | #define M98088_ADREN BIT(0) |
| 174 | |
| 175 | /* M98088_REG_4D_PWR_EN_OUT */ |
| 176 | #define M98088_HPLEN BIT(7) |
| 177 | #define M98088_HPREN BIT(6) |
| 178 | #define M98088_HPEN (BIT(7) | BIT(6)) |
| 179 | #define M98088_SPLEN BIT(5) |
| 180 | #define M98088_SPREN BIT(4) |
| 181 | #define M98088_RECEN BIT(3) |
| 182 | #define M98088_DALEN BIT(1) |
| 183 | #define M98088_DAREN BIT(0) |
| 184 | |
| 185 | /* M98088_REG_51_PWR_SYS */ |
| 186 | #define M98088_SHDNRUN BIT(7) |
| 187 | #define M98088_PERFMODE BIT(3) |
| 188 | #define M98088_HPPLYBACK BIT(2) |
| 189 | #define M98088_PWRSV8K BIT(1) |
| 190 | #define M98088_PWRSV BIT(0) |
| 191 | |
| 192 | #endif |