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git01.mediatek.com / filogic / uboot / 284f95d49d958d5e659e97dc5da941ed9d8e3a74 / . / include / asm-ppc / fsl_ddr_sdram.h
blob: c1ea7cd6bb16a3ff3ec68fa951e28f04dee6fbd5 [file] [log] [blame]
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]1/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#ifndef FSL_DDR_MEMCTL_H
10#define FSL_DDR_MEMCTL_H
11
12/*
13 * Pick a basic DDR Technology.
14 */
15#include <ddr_spd.h>
16
17#define SDRAM_TYPE_DDR1 2
18#define SDRAM_TYPE_DDR2 3
19#define SDRAM_TYPE_LPDDR1 6
20#define SDRAM_TYPE_DDR3 7
21
22#if defined(CONFIG_FSL_DDR1)
23#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
24typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
25#ifndef CONFIG_FSL_SDRAM_TYPE
26#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
27#endif
28#elif defined(CONFIG_FSL_DDR2)
29#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
30typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
31#ifndef CONFIG_FSL_SDRAM_TYPE
32#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
33#endif
34#elif defined(CONFIG_FSL_DDR3)
35#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
36typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
37#endif
38
Haiying Wang272b5962008-10-03 12:36:39 -0400[diff] [blame]39/* define bank(chip select) interleaving mode */
40#define FSL_DDR_CS0_CS1 0x40
41#define FSL_DDR_CS2_CS3 0x20
42#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
43#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
44
45/* define memory controller interleaving mode */
46#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
47#define FSL_DDR_PAGE_INTERLEAVING 0x1
48#define FSL_DDR_BANK_INTERLEAVING 0x2
49#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
50
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]51/* Record of register values computed */
52typedef struct fsl_ddr_cfg_regs_s {
53 struct {
54 unsigned int bnds;
55 unsigned int config;
56 unsigned int config_2;
57 } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
58 unsigned int timing_cfg_3;
59 unsigned int timing_cfg_0;
60 unsigned int timing_cfg_1;
61 unsigned int timing_cfg_2;
62 unsigned int ddr_sdram_cfg;
63 unsigned int ddr_sdram_cfg_2;
64 unsigned int ddr_sdram_mode;
65 unsigned int ddr_sdram_mode_2;
66 unsigned int ddr_sdram_md_cntl;
67 unsigned int ddr_sdram_interval;
68 unsigned int ddr_data_init;
69 unsigned int ddr_sdram_clk_cntl;
70 unsigned int ddr_init_addr;
71 unsigned int ddr_init_ext_addr;
72 unsigned int timing_cfg_4;
73 unsigned int timing_cfg_5;
74 unsigned int ddr_zq_cntl;
75 unsigned int ddr_wrlvl_cntl;
76 unsigned int ddr_pd_cntl;
77 unsigned int ddr_sr_cntr;
78 unsigned int ddr_sdram_rcw_1;
79 unsigned int ddr_sdram_rcw_2;
80} fsl_ddr_cfg_regs_t;
81
82typedef struct memctl_options_partial_s {
83 unsigned int all_DIMMs_ECC_capable;
84 unsigned int all_DIMMs_tCKmax_ps;
85 unsigned int all_DIMMs_burst_lengths_bitmask;
86 unsigned int all_DIMMs_registered;
87 unsigned int all_DIMMs_unbuffered;
88 /* unsigned int lowest_common_SPD_caslat; */
89 unsigned int all_DIMMs_minimum_tRCD_ps;
90} memctl_options_partial_t;
91
92/*
93 * Generalized parameters for memory controller configuration,
94 * might be a little specific to the FSL memory controller
95 */
96typedef struct memctl_options_s {
97 /*
98 * Memory organization parameters
99 *
100 * if DIMM is present in the system
101 * where DIMMs are with respect to chip select
102 * where chip selects are with respect to memory boundaries
103 */
104 unsigned int registered_dimm_en; /* use registered DIMM support */
105
106 /* Options local to a Chip Select */
107 struct cs_local_opts_s {
108 unsigned int auto_precharge;
109 unsigned int odt_rd_cfg;
110 unsigned int odt_wr_cfg;
111 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
112
113 /* Special configurations for chip select */
114 unsigned int memctl_interleaving;
115 unsigned int memctl_interleaving_mode;
116 unsigned int ba_intlv_ctl;
117
118 /* Operational mode parameters */
119 unsigned int ECC_mode; /* Use ECC? */
120 /* Initialize ECC using memory controller? */
121 unsigned int ECC_init_using_memctl;
122 unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */
123 /* SREN - self-refresh during sleep */
124 unsigned int self_refresh_in_sleep;
125 unsigned int dynamic_power; /* DYN_PWR */
126 /* memory data width to use (16-bit, 32-bit, 64-bit) */
127 unsigned int data_bus_width;
128 unsigned int burst_length; /* 4, 8 */
129
130 /* Global Timing Parameters */
131 unsigned int cas_latency_override;
132 unsigned int cas_latency_override_value;
133 unsigned int use_derated_caslat;
134 unsigned int additive_latency_override;
135 unsigned int additive_latency_override_value;
136
137 unsigned int clk_adjust; /* */
138 unsigned int cpo_override;
139 unsigned int write_data_delay; /* DQS adjust */
140 unsigned int half_strength_driver_enable;
141 unsigned int twoT_en;
142 unsigned int threeT_en;
143 unsigned int bstopre;
144 unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
145 unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
146} memctl_options_t;
147
148extern phys_size_t fsl_ddr_sdram(void);
149#endif