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Kumar Gala1242b882008-01-17 01:01:09 -06001/*
Kumar Galaad4e9d42011-01-04 17:57:59 -06002 * Copyright 2008, 2011 Freescale Semiconductor, Inc.
Kumar Gala1242b882008-01-17 01:01:09 -06003 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020031 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
Kumar Gala1242b882008-01-17 01:01:09 -060032 MAS3_SX|MAS3_SW|MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
Kumar Gala1242b882008-01-17 01:01:09 -060035 MAS3_SX|MAS3_SW|MAS3_SR, 0,
36 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020037 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
Kumar Gala1242b882008-01-17 01:01:09 -060038 MAS3_SX|MAS3_SW|MAS3_SR, 0,
39 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
Kumar Gala1242b882008-01-17 01:01:09 -060041 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
43
chenhui zhaoe97171e2011-10-13 13:40:59 +080044 /* TLB 1 */
Kumar Gala1242b882008-01-17 01:01:09 -060045 /*
chenhui zhaoe97171e2011-10-13 13:40:59 +080046 * Entry 0:
47 * FLASH(cover boot page) 16M Non-cacheable, guarded
Kumar Gala1242b882008-01-17 01:01:09 -060048 */
chenhui zhaoe97171e2011-10-13 13:40:59 +080049 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
Kumar Gala1242b882008-01-17 01:01:09 -060050 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
51 0, 0, BOOKE_PAGESZ_16M, 1),
52
53 /*
chenhui zhaoe97171e2011-10-13 13:40:59 +080054 * Entry 1:
55 * CCSRBAR 1M Non-cacheable, guarded
Kumar Gala1242b882008-01-17 01:01:09 -060056 */
chenhui zhaoe97171e2011-10-13 13:40:59 +080057 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
Kumar Gala1242b882008-01-17 01:01:09 -060058 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
chenhui zhaoe97171e2011-10-13 13:40:59 +080059 0, 1, BOOKE_PAGESZ_1M, 1),
Kumar Gala1242b882008-01-17 01:01:09 -060060
Kumar Gala1242b882008-01-17 01:01:09 -060061 /*
chenhui zhaoe97171e2011-10-13 13:40:59 +080062 * Entry 2:
63 * LBC SDRAM 64M Cacheable, non-guarded
Kumar Gala1242b882008-01-17 01:01:09 -060064 */
chenhui zhaoe97171e2011-10-13 13:40:59 +080065 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
66 CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
67 MAS3_SX|MAS3_SW|MAS3_SR, 0,
68 0, 2, BOOKE_PAGESZ_64M, 1),
Kumar Gala1242b882008-01-17 01:01:09 -060069
70 /*
chenhui zhaoe97171e2011-10-13 13:40:59 +080071 * Entry 3:
72 * CADMUS registers 1M Non-cacheable, guarded
Kumar Gala1242b882008-01-17 01:01:09 -060073 */
chenhui zhaoe97171e2011-10-13 13:40:59 +080074 SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
Kumar Gala1242b882008-01-17 01:01:09 -060075 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
chenhui zhaoe97171e2011-10-13 13:40:59 +080076 0, 3, BOOKE_PAGESZ_1M, 1),
Kumar Galaad4e9d42011-01-04 17:57:59 -060077
Kumar Gala1242b882008-01-17 01:01:09 -060078 /*
chenhui zhaoe97171e2011-10-13 13:40:59 +080079 * Entry 4:
80 * PCI and PCIe MEM 1G Non-cacheable, guarded
Kumar Gala1242b882008-01-17 01:01:09 -060081 */
chenhui zhaoe97171e2011-10-13 13:40:59 +080082 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
Kumar Gala1242b882008-01-17 01:01:09 -060083 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
chenhui zhaoe97171e2011-10-13 13:40:59 +080084 0, 4, BOOKE_PAGESZ_1G, 1),
Kumar Gala1242b882008-01-17 01:01:09 -060085
86 /*
chenhui zhaoe97171e2011-10-13 13:40:59 +080087 * Entry 5:
88 * PCI1 IO 1M Non-cacheable, guarded
Kumar Gala1242b882008-01-17 01:01:09 -060089 */
chenhui zhaoe97171e2011-10-13 13:40:59 +080090 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
91 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
92 0, 5, BOOKE_PAGESZ_1M, 1),
Kumar Gala1242b882008-01-17 01:01:09 -060093
94 /*
chenhui zhaoe97171e2011-10-13 13:40:59 +080095 * Entry 6:
96 * PCIe IO 1M Non-cacheable, guarded
Kumar Gala1242b882008-01-17 01:01:09 -060097 */
chenhui zhaoe97171e2011-10-13 13:40:59 +080098 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
99 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
100 0, 6, BOOKE_PAGESZ_1M, 1),
Kumar Gala1242b882008-01-17 01:01:09 -0600101};
102
103int num_tlb_entries = ARRAY_SIZE(tlb_table);