blob: 25cac056bbdf2952fa383d79bf72ed88f465bb42 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -06007 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -07008
Simon Glassfef72b72014-07-23 06:55:03 -06009 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060011 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070012 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060013 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060014 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass0ccb0972015-01-25 08:27:05 -070016 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060017 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070019 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070021 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -050022 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060024 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060026 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020027 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070028 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020034 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060038 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020041 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020042 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060043 };
44
Simon Glassed96cde2018-12-10 10:37:33 -070045 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glassc953aaf2018-12-10 10:37:34 -070050 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060051 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Simon Glassb2c1cac2014-02-26 15:59:21 -070079 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -060080 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070081 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -060082 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070083 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -060084 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -070085 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
86 <0>, <&gpio_a 12>;
87 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
88 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
89 <&gpio_b 9 0xc 3 2 1>;
Simon Glass6df01f92018-12-10 10:37:37 -070090 int-value = <1234>;
91 uint-value = <(-1234)>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070092 };
93
94 junk {
Simon Glasscf61f742015-07-06 12:54:36 -060095 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070096 compatible = "not,compatible";
97 };
98
99 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600100 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700101 };
102
Simon Glass5620cf82018-10-01 12:22:40 -0600103 backlight: backlight {
104 compatible = "pwm-backlight";
105 enable-gpios = <&gpio_a 1>;
106 power-supply = <&ldo_1>;
107 pwms = <&pwm 0 1000>;
108 default-brightness-level = <5>;
109 brightness-levels = <0 16 32 64 128 170 202 234 255>;
110 };
111
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200112 bind-test {
113 bind-test-child1 {
114 compatible = "sandbox,phy";
115 #phy-cells = <1>;
116 };
117
118 bind-test-child2 {
119 compatible = "simple-bus";
120 };
121 };
122
Simon Glassb2c1cac2014-02-26 15:59:21 -0700123 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600124 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700125 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600126 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700127 ping-add = <3>;
128 };
129
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200130 phy_provider0: gen_phy@0 {
131 compatible = "sandbox,phy";
132 #phy-cells = <1>;
133 };
134
135 phy_provider1: gen_phy@1 {
136 compatible = "sandbox,phy";
137 #phy-cells = <0>;
138 broken;
139 };
140
141 gen_phy_user: gen_phy_user {
142 compatible = "simple-bus";
143 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
144 phy-names = "phy1", "phy2", "phy3";
145 };
146
Simon Glassb2c1cac2014-02-26 15:59:21 -0700147 some-bus {
148 #address-cells = <1>;
149 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600150 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600151 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600152 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700153 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600154 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700155 compatible = "denx,u-boot-fdt-test";
156 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600157 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700158 ping-add = <5>;
159 };
Simon Glass40717422014-07-23 06:55:18 -0600160 c-test@0 {
161 compatible = "denx,u-boot-fdt-test";
162 reg = <0>;
163 ping-expect = <6>;
164 ping-add = <6>;
165 };
166 c-test@1 {
167 compatible = "denx,u-boot-fdt-test";
168 reg = <1>;
169 ping-expect = <7>;
170 ping-add = <7>;
171 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700172 };
173
174 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600175 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600176 ping-expect = <6>;
177 ping-add = <6>;
178 compatible = "google,another-fdt-test";
179 };
180
181 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600182 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600183 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700184 ping-add = <6>;
185 compatible = "google,another-fdt-test";
186 };
187
Simon Glass0ccb0972015-01-25 08:27:05 -0700188 f-test {
189 compatible = "denx,u-boot-fdt-test";
190 };
191
192 g-test {
193 compatible = "denx,u-boot-fdt-test";
194 };
195
Bin Mengd9d24782018-10-10 22:07:01 -0700196 h-test {
197 compatible = "denx,u-boot-fdt-test1";
198 };
199
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200200 clocks {
201 clk_fixed: clk-fixed {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <1234>;
205 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000206
207 clk_fixed_factor: clk-fixed-factor {
208 compatible = "fixed-factor-clock";
209 #clock-cells = <0>;
210 clock-div = <3>;
211 clock-mult = <2>;
212 clocks = <&clk_fixed>;
213 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200214
215 osc {
216 compatible = "fixed-clock";
217 #clock-cells = <0>;
218 clock-frequency = <20000000>;
219 };
Stephen Warrena9622432016-06-17 09:44:00 -0600220 };
221
222 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600223 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600224 #clock-cells = <1>;
225 };
226
227 clk-test {
228 compatible = "sandbox,clk-test";
229 clocks = <&clk_fixed>,
230 <&clk_sandbox 1>,
231 <&clk_sandbox 0>;
232 clock-names = "fixed", "i2c", "spi";
Simon Glass8cc4d822015-07-06 12:54:24 -0600233 };
234
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200235 ccf: clk-ccf {
236 compatible = "sandbox,clk-ccf";
237 };
238
Simon Glass5b968632015-05-22 15:42:15 -0600239 eth@10002000 {
240 compatible = "sandbox,eth";
241 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500242 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600243 };
244
245 eth_5: eth@10003000 {
246 compatible = "sandbox,eth";
247 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500248 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600249 };
250
Bin Meng04a11cb2015-08-27 22:25:53 -0700251 eth_3: sbe5 {
252 compatible = "sandbox,eth";
253 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500254 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700255 };
256
Simon Glass5b968632015-05-22 15:42:15 -0600257 eth@10004000 {
258 compatible = "sandbox,eth";
259 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500260 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600261 };
262
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700263 firmware {
264 sandbox_firmware: sandbox-firmware {
265 compatible = "sandbox,firmware";
266 };
267 };
268
Simon Glass25348a42014-10-13 23:42:11 -0600269 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700270 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700271 gpio-controller;
272 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700273 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700274 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700275 };
276
Simon Glass16e10402015-01-05 20:05:29 -0700277 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700278 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700279 gpio-controller;
280 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700281 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700282 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700283 };
Simon Glass25348a42014-10-13 23:42:11 -0600284
Simon Glass7df766e2014-12-10 08:55:55 -0700285 i2c@0 {
286 #address-cells = <1>;
287 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600288 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700289 compatible = "sandbox,i2c";
290 clock-frequency = <100000>;
291 eeprom@2c {
292 reg = <0x2c>;
293 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700294 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700295 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200296
Simon Glass336b2952015-05-22 15:42:17 -0600297 rtc_0: rtc@43 {
298 reg = <0x43>;
299 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700300 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600301 };
302
303 rtc_1: rtc@61 {
304 reg = <0x61>;
305 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700306 sandbox,emul = <&emul1>;
307 };
308
309 i2c_emul: emul {
310 reg = <0xff>;
311 compatible = "sandbox,i2c-emul-parent";
312 emul_eeprom: emul-eeprom {
313 compatible = "sandbox,i2c-eeprom";
314 sandbox,filename = "i2c.bin";
315 sandbox,size = <256>;
316 };
317 emul0: emul0 {
318 compatible = "sandbox,i2c-rtc";
319 };
320 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600321 compatible = "sandbox,i2c-rtc";
322 };
323 };
324
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200325 sandbox_pmic: sandbox_pmic {
326 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700327 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200328 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200329
330 mc34708: pmic@41 {
331 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700332 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200333 };
Simon Glass7df766e2014-12-10 08:55:55 -0700334 };
335
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100336 bootcount@0 {
337 compatible = "u-boot,bootcount-rtc";
338 rtc = <&rtc_1>;
339 offset = <0x13>;
340 };
341
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100342 adc@0 {
343 compatible = "sandbox,adc";
344 vdd-supply = <&buck2>;
345 vss-microvolts = <0>;
346 };
347
Simon Glass90b6fef2016-01-18 19:52:26 -0700348 lcd {
349 u-boot,dm-pre-reloc;
350 compatible = "sandbox,lcd-sdl";
351 xres = <1366>;
352 yres = <768>;
353 };
354
Simon Glassd783eb32015-07-06 12:54:34 -0600355 leds {
356 compatible = "gpio-leds";
357
358 iracibble {
359 gpios = <&gpio_a 1 0>;
360 label = "sandbox:red";
361 };
362
363 martinet {
364 gpios = <&gpio_a 2 0>;
365 label = "sandbox:green";
366 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200367
368 default_on {
369 gpios = <&gpio_a 5 0>;
370 label = "sandbox:default_on";
371 default-state = "on";
372 };
373
374 default_off {
375 gpios = <&gpio_a 6 0>;
376 label = "sandbox:default_off";
377 default-state = "off";
378 };
Simon Glassd783eb32015-07-06 12:54:34 -0600379 };
380
Stephen Warren62f2c902016-05-16 17:41:37 -0600381 mbox: mbox {
382 compatible = "sandbox,mbox";
383 #mbox-cells = <1>;
384 };
385
386 mbox-test {
387 compatible = "sandbox,mbox-test";
388 mboxes = <&mbox 100>, <&mbox 1>;
389 mbox-names = "other", "test";
390 };
391
Mario Sixdea5df72018-08-06 10:23:44 +0200392 cpu-test1 {
393 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700394 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200395 };
396
397 cpu-test2 {
398 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700399 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200400 };
401
402 cpu-test3 {
403 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700404 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200405 };
406
Simon Glassc953aaf2018-12-10 10:37:34 -0700407 i2s: i2s {
408 compatible = "sandbox,i2s";
409 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700410 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700411 };
412
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200413 nop-test_0 {
414 compatible = "sandbox,nop_sandbox1";
415 nop-test_1 {
416 compatible = "sandbox,nop_sandbox2";
417 bind = "True";
418 };
419 nop-test_2 {
420 compatible = "sandbox,nop_sandbox2";
421 bind = "False";
422 };
423 };
424
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200425 misc-test {
426 compatible = "sandbox,misc_sandbox";
427 };
428
Simon Glasse4fef742017-04-23 20:02:07 -0600429 mmc2 {
430 compatible = "sandbox,mmc";
431 };
432
433 mmc1 {
434 compatible = "sandbox,mmc";
435 };
436
437 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600438 compatible = "sandbox,mmc";
439 };
440
Simon Glass53a68b32019-02-16 20:24:50 -0700441 pch {
442 compatible = "sandbox,pch";
443 };
444
Bin Meng408e5902018-08-03 01:14:41 -0700445 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700446 compatible = "sandbox,pci";
447 device_type = "pci";
448 #address-cells = <3>;
449 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600450 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700451 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700452 pci@0,0 {
453 compatible = "pci-generic";
454 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600455 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700456 };
Alex Margineanf1274432019-06-07 11:24:24 +0300457 pci@1,0 {
458 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600459 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
460 reg = <0x02000814 0 0 0 0
461 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600462 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300463 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700464 pci@1f,0 {
465 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600466 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
467 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600468 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700469 };
470 };
471
Simon Glassb98ba4c2019-09-25 08:56:10 -0600472 pci-emul0 {
473 compatible = "sandbox,pci-emul-parent";
474 swap_case_emul0_0: emul0@0,0 {
475 compatible = "sandbox,swap-case";
476 };
477 swap_case_emul0_1: emul0@1,0 {
478 compatible = "sandbox,swap-case";
479 use-ea;
480 };
481 swap_case_emul0_1f: emul0@1f,0 {
482 compatible = "sandbox,swap-case";
483 };
484 };
485
Bin Meng408e5902018-08-03 01:14:41 -0700486 pci1: pci-controller1 {
487 compatible = "sandbox,pci";
488 device_type = "pci";
489 #address-cells = <3>;
490 #size-cells = <2>;
491 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
492 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700493 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200494 0x0c 0x00 0x1234 0x5678
495 0x10 0x00 0x1234 0x5678>;
496 pci@10,0 {
497 reg = <0x8000 0 0 0 0>;
498 };
Bin Meng408e5902018-08-03 01:14:41 -0700499 };
500
Bin Meng510dddb2018-08-03 01:14:50 -0700501 pci2: pci-controller2 {
502 compatible = "sandbox,pci";
503 device_type = "pci";
504 #address-cells = <3>;
505 #size-cells = <2>;
506 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
507 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
508 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
509 pci@1f,0 {
510 compatible = "pci-generic";
511 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600512 sandbox,emul = <&swap_case_emul2_1f>;
513 };
514 };
515
516 pci-emul2 {
517 compatible = "sandbox,pci-emul-parent";
518 swap_case_emul2_1f: emul2@1f,0 {
519 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700520 };
521 };
522
Ramon Friedc64f19b2019-04-27 11:15:23 +0300523 pci_ep: pci_ep {
524 compatible = "sandbox,pci_ep";
525 };
526
Simon Glass9c433fe2017-04-23 20:10:44 -0600527 probing {
528 compatible = "simple-bus";
529 test1 {
530 compatible = "denx,u-boot-probe-test";
531 };
532
533 test2 {
534 compatible = "denx,u-boot-probe-test";
535 };
536
537 test3 {
538 compatible = "denx,u-boot-probe-test";
539 };
540
541 test4 {
542 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100543 first-syscon = <&syscon0>;
544 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100545 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600546 };
547 };
548
Stephen Warren92c67fa2016-07-13 13:45:31 -0600549 pwrdom: power-domain {
550 compatible = "sandbox,power-domain";
551 #power-domain-cells = <1>;
552 };
553
554 power-domain-test {
555 compatible = "sandbox,power-domain-test";
556 power-domains = <&pwrdom 2>;
557 };
558
Simon Glass5620cf82018-10-01 12:22:40 -0600559 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600560 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600561 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600562 };
563
564 pwm2 {
565 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600566 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600567 };
568
Simon Glass3d355e62015-07-06 12:54:31 -0600569 ram {
570 compatible = "sandbox,ram";
571 };
572
Simon Glassd860f222015-07-06 12:54:29 -0600573 reset@0 {
574 compatible = "sandbox,warm-reset";
575 };
576
577 reset@1 {
578 compatible = "sandbox,reset";
579 };
580
Stephen Warren6488e642016-06-17 09:43:59 -0600581 resetc: reset-ctl {
582 compatible = "sandbox,reset-ctl";
583 #reset-cells = <1>;
584 };
585
586 reset-ctl-test {
587 compatible = "sandbox,reset-ctl-test";
588 resets = <&resetc 100>, <&resetc 2>;
589 reset-names = "other", "test";
590 };
591
Nishanth Menonedf85812015-09-17 15:42:41 -0500592 rproc_1: rproc@1 {
593 compatible = "sandbox,test-processor";
594 remoteproc-name = "remoteproc-test-dev1";
595 };
596
597 rproc_2: rproc@2 {
598 compatible = "sandbox,test-processor";
599 internal-memory-mapped;
600 remoteproc-name = "remoteproc-test-dev2";
601 };
602
Simon Glass5620cf82018-10-01 12:22:40 -0600603 panel {
604 compatible = "simple-panel";
605 backlight = <&backlight 0 100>;
606 };
607
Ramon Fried26ed32e2018-07-02 02:57:59 +0300608 smem@0 {
609 compatible = "sandbox,smem";
610 };
611
Simon Glass76072ac2018-12-10 10:37:36 -0700612 sound {
613 compatible = "sandbox,sound";
614 cpu {
615 sound-dai = <&i2s 0>;
616 };
617
618 codec {
619 sound-dai = <&audio 0>;
620 };
621 };
622
Simon Glass25348a42014-10-13 23:42:11 -0600623 spi@0 {
624 #address-cells = <1>;
625 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600626 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600627 compatible = "sandbox,spi";
628 cs-gpios = <0>, <&gpio_a 0>;
629 spi.bin@0 {
630 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000631 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600632 spi-max-frequency = <40000000>;
633 sandbox,filename = "spi.bin";
634 };
635 };
636
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100637 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600638 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200639 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600640 };
641
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100642 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600643 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600644 reg = <0x20 5
645 0x28 6
646 0x30 7
647 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600648 };
649
Patrick Delaunayee010432019-03-07 09:57:13 +0100650 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900651 compatible = "simple-mfd", "syscon";
652 reg = <0x40 5
653 0x48 6
654 0x50 7
655 0x58 8>;
656 };
657
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800658 timer {
659 compatible = "sandbox,timer";
660 clock-frequency = <1000000>;
661 };
662
Miquel Raynal80938c12018-05-15 11:57:27 +0200663 tpm2 {
664 compatible = "sandbox,tpm2";
665 };
666
Simon Glass5b968632015-05-22 15:42:15 -0600667 uart0: serial {
668 compatible = "sandbox,serial";
669 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500670 };
671
Simon Glass31680482015-03-25 12:23:05 -0600672 usb_0: usb@0 {
673 compatible = "sandbox,usb";
674 status = "disabled";
675 hub {
676 compatible = "sandbox,usb-hub";
677 #address-cells = <1>;
678 #size-cells = <0>;
679 flash-stick {
680 reg = <0>;
681 compatible = "sandbox,usb-flash";
682 };
683 };
684 };
685
686 usb_1: usb@1 {
687 compatible = "sandbox,usb";
688 hub {
689 compatible = "usb-hub";
690 usb,device-class = <9>;
691 hub-emul {
692 compatible = "sandbox,usb-hub";
693 #address-cells = <1>;
694 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700695 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600696 reg = <0>;
697 compatible = "sandbox,usb-flash";
698 sandbox,filepath = "testflash.bin";
699 };
700
Simon Glass4700fe52015-11-08 23:48:01 -0700701 flash-stick@1 {
702 reg = <1>;
703 compatible = "sandbox,usb-flash";
704 sandbox,filepath = "testflash1.bin";
705 };
706
707 flash-stick@2 {
708 reg = <2>;
709 compatible = "sandbox,usb-flash";
710 sandbox,filepath = "testflash2.bin";
711 };
712
Simon Glassc0ccc722015-11-08 23:48:08 -0700713 keyb@3 {
714 reg = <3>;
715 compatible = "sandbox,usb-keyb";
716 };
717
Simon Glass31680482015-03-25 12:23:05 -0600718 };
719 };
720 };
721
722 usb_2: usb@2 {
723 compatible = "sandbox,usb";
724 status = "disabled";
725 };
726
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200727 spmi: spmi@0 {
728 compatible = "sandbox,spmi";
729 #address-cells = <0x1>;
730 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600731 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200732 pm8916@0 {
733 compatible = "qcom,spmi-pmic";
734 reg = <0x0 0x1>;
735 #address-cells = <0x1>;
736 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600737 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200738
739 spmi_gpios: gpios@c000 {
740 compatible = "qcom,pm8916-gpio";
741 reg = <0xc000 0x400>;
742 gpio-controller;
743 gpio-count = <4>;
744 #gpio-cells = <2>;
745 gpio-bank-name="spmi";
746 };
747 };
748 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700749
750 wdt0: wdt@0 {
751 compatible = "sandbox,wdt";
752 };
Rob Clarka471b672018-01-10 11:33:30 +0100753
Mario Six95922152018-08-09 14:51:19 +0200754 axi: axi@0 {
755 compatible = "sandbox,axi";
756 #address-cells = <0x1>;
757 #size-cells = <0x1>;
758 store@0 {
759 compatible = "sandbox,sandbox_store";
760 reg = <0x0 0x400>;
761 };
762 };
763
Rob Clarka471b672018-01-10 11:33:30 +0100764 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700765 #address-cells = <1>;
766 #size-cells = <1>;
Rob Clarka471b672018-01-10 11:33:30 +0100767 chosen-test {
768 compatible = "denx,u-boot-fdt-test";
769 reg = <9 1>;
770 };
771 };
Mario Six35616ef2018-03-12 14:53:33 +0100772
773 translation-test@8000 {
774 compatible = "simple-bus";
775 reg = <0x8000 0x4000>;
776
777 #address-cells = <0x2>;
778 #size-cells = <0x1>;
779
780 ranges = <0 0x0 0x8000 0x1000
781 1 0x100 0x9000 0x1000
782 2 0x200 0xA000 0x1000
783 3 0x300 0xB000 0x1000
784 >;
785
Fabien Dessenne22236e02019-05-31 15:11:30 +0200786 dma-ranges = <0 0x000 0x10000000 0x1000
787 1 0x100 0x20000000 0x1000
788 >;
789
Mario Six35616ef2018-03-12 14:53:33 +0100790 dev@0,0 {
791 compatible = "denx,u-boot-fdt-dummy";
792 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100793 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100794 };
795
796 dev@1,100 {
797 compatible = "denx,u-boot-fdt-dummy";
798 reg = <1 0x100 0x1000>;
799
800 };
801
802 dev@2,200 {
803 compatible = "denx,u-boot-fdt-dummy";
804 reg = <2 0x200 0x1000>;
805 };
806
807
808 noxlatebus@3,300 {
809 compatible = "simple-bus";
810 reg = <3 0x300 0x1000>;
811
812 #address-cells = <0x1>;
813 #size-cells = <0x0>;
814
815 dev@42 {
816 compatible = "denx,u-boot-fdt-dummy";
817 reg = <0x42>;
818 };
819 };
820 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200821
822 osd {
823 compatible = "sandbox,sandbox_osd";
824 };
Tom Rinib93eea72018-09-30 18:16:51 -0400825
Mario Sixab664ff2018-07-31 11:44:13 +0200826 board {
827 compatible = "sandbox,board_sandbox";
828 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200829
830 sandbox_tee {
831 compatible = "sandbox,tee";
832 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700833
834 sandbox_virtio1 {
835 compatible = "sandbox,virtio1";
836 };
837
838 sandbox_virtio2 {
839 compatible = "sandbox,virtio2";
840 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200841
842 pinctrl {
843 compatible = "sandbox,pinctrl";
844 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100845
846 hwspinlock@0 {
847 compatible = "sandbox,hwspinlock";
848 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100849
850 dma: dma {
851 compatible = "sandbox,dma";
852 #dma-cells = <1>;
853
854 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
855 dma-names = "m2m", "tx0", "rx0";
856 };
Alex Marginean0daa53a2019-06-03 19:12:28 +0300857
Alex Marginean0649be52019-07-12 10:13:53 +0300858 /*
859 * keep mdio-mux ahead of mdio so that the mux is removed first at the
860 * end of the test. If parent mdio is removed first, clean-up of the
861 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
862 * active at the end of the test. That it turn doesn't allow the mdio
863 * class to be destroyed, triggering an error.
864 */
865 mdio-mux-test {
866 compatible = "sandbox,mdio-mux";
867 #address-cells = <1>;
868 #size-cells = <0>;
869 mdio-parent-bus = <&mdio>;
870
871 mdio-ch-test@0 {
872 reg = <0>;
873 };
874 mdio-ch-test@1 {
875 reg = <1>;
876 };
877 };
878
879 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +0300880 compatible = "sandbox,mdio";
881 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700882};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200883
884#include "sandbox_pmic.dtsi"