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git01.mediatek.com / filogic / uboot / 27ee03c1f8b9dc12e2b5f6aff6f081ed9eaded02 / . / drivers / gpio / qe_gpio.c
blob: 16e8d1eae6edea5966764ba188a65e6ef69e7a4c [file] [log] [blame]
Christophe Leroyd4f79cb2023-02-21 19:31:11 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2023 CR GROUP France
4 * Christophe Leroy <christophe.leroy@csgroup.eu>
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <mapmem.h>
10#include <asm/gpio.h>
11#include <asm/immap_83xx.h>
12#include <asm/io.h>
13#include <dm/of_access.h>
14
15#define QE_DIR_NONE 0
16#define QE_DIR_OUT 1
17#define QE_DIR_IN 2
18#define QE_DIR_IN_OUT 3
19
20struct qe_gpio_data {
21 /* The bank's register base in memory */
22 struct gpio_n __iomem *base;
23 /* The address of the registers; used to identify the bank */
24 phys_addr_t addr;
25};
26
27static inline u32 gpio_mask(uint gpio)
28{
29 return 1U << (31 - (gpio));
30}
31
32static inline u32 gpio_mask2(uint gpio)
33{
34 return 1U << (30 - ((gpio & 15) << 1));
35}
36
37static int qe_gpio_direction_input(struct udevice *dev, uint gpio)
38{
39 struct qe_gpio_data *data = dev_get_priv(dev);
40 struct gpio_n __iomem *base = data->base;
41 u32 mask2 = gpio_mask2(gpio);
42
43 if (gpio < 16)
44 clrsetbits_be32(&base->dir1, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN);
45 else
46 clrsetbits_be32(&base->dir2, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN);
47
48 return 0;
49}
50
51static int qe_gpio_set_value(struct udevice *dev, uint gpio, int value)
52{
53 struct qe_gpio_data *data = dev_get_priv(dev);
54 struct gpio_n __iomem *base = data->base;
55 u32 mask = gpio_mask(gpio);
56 u32 mask2 = gpio_mask2(gpio);
57
58 if (gpio < 16)
59 clrsetbits_be32(&base->dir1, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT);
60 else
61 clrsetbits_be32(&base->dir2, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT);
62
63 if (value)
64 setbits_be32(&base->pdat, mask);
65 else
66 clrbits_be32(&base->pdat, mask);
67
68 return 0;
69}
70
71static int qe_gpio_get_value(struct udevice *dev, uint gpio)
72{
73 struct qe_gpio_data *data = dev_get_priv(dev);
74 struct gpio_n __iomem *base = data->base;
75 u32 mask = gpio_mask(gpio);
76
77 return !!(in_be32(&base->pdat) & mask);
78}
79
80static int qe_gpio_get_function(struct udevice *dev, uint gpio)
81{
82 struct qe_gpio_data *data = dev_get_priv(dev);
83 struct gpio_n __iomem *base = data->base;
84 u32 mask2 = gpio_mask2(gpio);
85 int dir;
86
87 if (gpio < 16)
88 dir = in_be32(&base->dir1);
89 else
90 dir = in_be32(&base->dir2);
91
92 if ((dir & (mask2 * QE_DIR_IN_OUT)) == (mask2 & QE_DIR_IN))
93 return GPIOF_INPUT;
94 else if ((dir & (mask2 * QE_DIR_IN_OUT)) == (mask2 & QE_DIR_OUT))
95 return GPIOF_OUTPUT;
96 else
97 return GPIOF_UNKNOWN;
98}
99
100static int qe_gpio_of_to_plat(struct udevice *dev)
101{
102 struct qe_gpio_plat *plat = dev_get_plat(dev);
103
104 plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
105
106 return 0;
107}
108
109static int qe_gpio_plat_to_priv(struct udevice *dev)
110{
111 struct qe_gpio_data *priv = dev_get_priv(dev);
112 struct qe_gpio_plat *plat = dev_get_plat(dev);
113 unsigned long size = plat->size;
114
115 if (size == 0)
116 size = sizeof(struct gpio_n);
117
118 priv->addr = plat->addr;
119 priv->base = (void __iomem *)plat->addr;
120
121 if (!priv->base)
122 return -ENOMEM;
123
124 return 0;
125}
126
127static int qe_gpio_probe(struct udevice *dev)
128{
129 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
130 struct qe_gpio_data *data = dev_get_priv(dev);
131 char name[32], *str;
132
133 qe_gpio_plat_to_priv(dev);
134
135 snprintf(name, sizeof(name), "QE@%.8llx",
136 (unsigned long long)data->addr);
137 str = strdup(name);
138
139 if (!str)
140 return -ENOMEM;
141
142 uc_priv->bank_name = str;
143 uc_priv->gpio_count = 32;
144
145 return 0;
146}
147
148static const struct dm_gpio_ops gpio_qe_ops = {
149 .direction_input = qe_gpio_direction_input,
150 .direction_output = qe_gpio_set_value,
151 .get_value = qe_gpio_get_value,
152 .set_value = qe_gpio_set_value,
153 .get_function = qe_gpio_get_function,
154};
155
156static const struct udevice_id qe_gpio_ids[] = {
157 { .compatible = "fsl,mpc8323-qe-pario-bank"},
158 { /* sentinel */ }
159};
160
161U_BOOT_DRIVER(gpio_qe) = {
162 .name = "gpio_qe",
163 .id = UCLASS_GPIO,
164 .ops = &gpio_qe_ops,
165 .of_to_plat = qe_gpio_of_to_plat,
166 .plat_auto = sizeof(struct qe_gpio_plat),
167 .of_match = qe_gpio_ids,
168 .probe = qe_gpio_probe,
169 .priv_auto = sizeof(struct qe_gpio_data),
170};