blob: 661808929021634d723ea6b6c8ca2965b1823096 [file] [log] [blame]
Magnus Lilja4133f652009-06-13 20:50:01 +02001/*
Magnus Lilja4133f652009-06-13 20:50:01 +02002 * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __FSL_NFC_H
24#define __FSL_NFC_H
25
26/*
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020027 * Register map and bit definitions for the Freescale NAND Flash Controller
28 * present in various i.MX devices.
John Rigby4c94c452010-01-26 19:24:17 -070029 *
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020030 * MX31 and MX27 have version 1, which has:
31 * 4 512-byte main buffers and
32 * 4 16-byte spare buffers
33 * to support up to 2K byte pagesize nand.
34 * Reading or writing a 2K page requires 4 FDI/FDO cycles.
John Rigby4c94c452010-01-26 19:24:17 -070035 *
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020036 * MX25 and MX35 have version 1.1, which has:
37 * 8 512-byte main buffers and
38 * 8 64-byte spare buffers
39 * to support up to 4K byte pagesize nand.
40 * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
41 * Also some of registers are moved and/or changed meaning as seen below.
Magnus Lilja4133f652009-06-13 20:50:01 +020042 */
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020043#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
John Rigby4c94c452010-01-26 19:24:17 -070044#define MXC_NFC_V1
Benoît Thébaudeau27d64532012-08-13 22:50:42 +020045#define is_mxc_nfc_11() 0
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020046#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
John Rigby4c94c452010-01-26 19:24:17 -070047#define MXC_NFC_V1_1
Benoît Thébaudeau27d64532012-08-13 22:50:42 +020048#define is_mxc_nfc_11() 1
John Rigby4c94c452010-01-26 19:24:17 -070049#else
Benoît Thébaudeau27d64532012-08-13 22:50:42 +020050#error "MXC NFC implementation not supported"
John Rigby4c94c452010-01-26 19:24:17 -070051#endif
52
53#if defined(MXC_NFC_V1)
54#define NAND_MXC_NR_BUFS 4
55#define NAND_MXC_SPARE_BUF_SIZE 16
56#define NAND_MXC_REG_OFFSET 0xe00
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020057#define NAND_MXC_2K_MULTI_CYCLE
John Rigby4c94c452010-01-26 19:24:17 -070058#elif defined(MXC_NFC_V1_1)
59#define NAND_MXC_NR_BUFS 8
60#define NAND_MXC_SPARE_BUF_SIZE 64
61#define NAND_MXC_REG_OFFSET 0x1e00
John Rigby4c94c452010-01-26 19:24:17 -070062#endif
Magnus Lilja4133f652009-06-13 20:50:01 +020063
64struct fsl_nfc_regs {
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020065 u8 main_area[NAND_MXC_NR_BUFS][0x200];
66 u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
John Rigby4c94c452010-01-26 19:24:17 -070067 /*
68 * reserved size is offset of nfc registers
69 * minus total main and spare sizes
70 */
71 u8 reserved1[NAND_MXC_REG_OFFSET
72 - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
73#if defined(MXC_NFC_V1)
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020074 u16 buf_size;
Magnus Lilja4133f652009-06-13 20:50:01 +020075 u16 reserved2;
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020076 u16 buf_addr;
77 u16 flash_addr;
Magnus Lilja4133f652009-06-13 20:50:01 +020078 u16 flash_cmd;
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020079 u16 config;
Magnus Lilja4133f652009-06-13 20:50:01 +020080 u16 ecc_status_result;
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020081 u16 rsltmain_area;
82 u16 rsltspare_area;
83 u16 wrprot;
84 u16 unlockstart_blkaddr;
85 u16 unlockend_blkaddr;
86 u16 nf_wrprst;
87 u16 config1;
88 u16 config2;
John Rigby4c94c452010-01-26 19:24:17 -070089#elif defined(MXC_NFC_V1_1)
90 u16 reserved2[2];
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020091 u16 buf_addr;
92 u16 flash_addr;
John Rigby4c94c452010-01-26 19:24:17 -070093 u16 flash_cmd;
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020094 u16 config;
Benoît Thébaudeaud29aeba2012-08-13 22:49:42 +020095 u32 ecc_status_result;
John Rigby4c94c452010-01-26 19:24:17 -070096 u16 spare_area_size;
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020097 u16 wrprot;
John Rigby4c94c452010-01-26 19:24:17 -070098 u16 reserved3[2];
Benoît Thébaudeau3f775192012-08-13 22:48:12 +020099 u16 nf_wrprst;
100 u16 config1;
101 u16 config2;
John Rigby4c94c452010-01-26 19:24:17 -0700102 u16 reserved4;
Benoît Thébaudeau3f775192012-08-13 22:48:12 +0200103 u16 unlockstart_blkaddr;
104 u16 unlockend_blkaddr;
105 u16 unlockstart_blkaddr1;
106 u16 unlockend_blkaddr1;
107 u16 unlockstart_blkaddr2;
108 u16 unlockend_blkaddr2;
109 u16 unlockstart_blkaddr3;
110 u16 unlockend_blkaddr3;
John Rigby4c94c452010-01-26 19:24:17 -0700111#endif
Magnus Lilja4133f652009-06-13 20:50:01 +0200112};
113
114/*
115 * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
116 * operation
117 */
118#define NFC_CMD 0x1
119
120/*
121 * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
122 * operation
123 */
124#define NFC_ADDR 0x2
125
126/*
127 * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
128 * operation
129 */
130#define NFC_INPUT 0x4
131
132/*
133 * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
134 * Output operation
135 */
136#define NFC_OUTPUT 0x8
137
138/*
139 * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
140 * operation
141 */
142#define NFC_ID 0x10
143
144/*
145 * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
146 * Status operation
147 */
148#define NFC_STATUS 0x20
149
150/*
151 * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
152 * operation
153 */
154#define NFC_INT 0x8000
155
John Rigby4c94c452010-01-26 19:24:17 -0700156#ifdef MXC_NFC_V1_1
157#define NFC_4_8N_ECC (1 << 0)
158#endif
Magnus Lilja4133f652009-06-13 20:50:01 +0200159#define NFC_SP_EN (1 << 2)
160#define NFC_ECC_EN (1 << 3)
161#define NFC_INT_MSK (1 << 4)
162#define NFC_BIG (1 << 5)
163#define NFC_RST (1 << 6)
164#define NFC_CE (1 << 7)
165#define NFC_ONE_CYCLE (1 << 8)
Benoît Thébaudeau32ae5b42012-08-13 22:48:26 +0200166#define NFC_FP_INT (1 << 11)
Magnus Lilja4133f652009-06-13 20:50:01 +0200167
168#endif /* __FSL_NFC_H */