| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Tom Warren | c47e717 | 2013-01-28 13:32:07 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
| Tom Warren | c47e717 | 2013-01-28 13:32:07 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _TEGRA114_GPIO_H_ |
| 7 | #define _TEGRA114_GPIO_H_ |
| 8 | |
| 9 | /* |
| 10 | * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports, |
| 11 | * each with 8 GPIOs. |
| 12 | */ |
| 13 | #define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ |
| 14 | #define TEGRA_GPIO_BANKS 8 /* number of banks */ |
| 15 | |
| 16 | #include <asm/arch-tegra/gpio.h> |
| 17 | #include <asm/arch-tegra30/gpio.h> |
| 18 | |
| 19 | #endif /* _TEGRA114_GPIO_H_ */ |