Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
Sean Anderson | 9baaaef | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 3 | * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com> |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 4 | * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> |
Sean Anderson | 9baaaef | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 5 | * Copyright (C) 2018, Anup Patel <anup@brainfault.org> |
| 6 | * Copyright (C) 2012 Regents of the University of California |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 7 | * |
Sean Anderson | 9baaaef | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 8 | * RISC-V architecturally-defined generic timer driver |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 9 | * |
Sean Anderson | 9baaaef | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 10 | * This driver provides generic timer support for S-mode U-Boot. |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <common.h> |
| 14 | #include <dm.h> |
| 15 | #include <errno.h> |
Torsten Duwe | 002858c | 2023-08-14 18:05:28 +0200 | [diff] [blame] | 16 | #include <fdt_support.h> |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 17 | #include <timer.h> |
Sean Anderson | 9baaaef | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 18 | #include <asm/csr.h> |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 19 | |
Pragnesh Patel | 02038c3 | 2021-01-17 18:11:25 +0530 | [diff] [blame] | 20 | static u64 notrace riscv_timer_get_count(struct udevice *dev) |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 21 | { |
Sean Anderson | 947fc2d | 2020-10-07 14:37:44 -0400 | [diff] [blame] | 22 | __maybe_unused u32 hi, lo; |
Sean Anderson | 9baaaef | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 23 | |
Sean Anderson | 947fc2d | 2020-10-07 14:37:44 -0400 | [diff] [blame] | 24 | if (IS_ENABLED(CONFIG_64BIT)) |
| 25 | return csr_read(CSR_TIME); |
Sean Anderson | 9baaaef | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 26 | |
Sean Anderson | 947fc2d | 2020-10-07 14:37:44 -0400 | [diff] [blame] | 27 | do { |
| 28 | hi = csr_read(CSR_TIMEH); |
| 29 | lo = csr_read(CSR_TIME); |
| 30 | } while (hi != csr_read(CSR_TIMEH)); |
Sean Anderson | 9baaaef | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 31 | |
Sean Anderson | 947fc2d | 2020-10-07 14:37:44 -0400 | [diff] [blame] | 32 | return ((u64)hi << 32) | lo; |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 33 | } |
| 34 | |
Pragnesh Patel | 02038c3 | 2021-01-17 18:11:25 +0530 | [diff] [blame] | 35 | #if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) |
| 36 | /** |
| 37 | * timer_early_get_rate() - Get the timer rate before driver model |
| 38 | */ |
| 39 | unsigned long notrace timer_early_get_rate(void) |
| 40 | { |
| 41 | return RISCV_SMODE_TIMER_FREQ; |
| 42 | } |
| 43 | |
| 44 | /** |
| 45 | * timer_early_get_count() - Get the timer count before driver model |
| 46 | * |
| 47 | */ |
| 48 | u64 notrace timer_early_get_count(void) |
| 49 | { |
| 50 | return riscv_timer_get_count(NULL); |
| 51 | } |
| 52 | #endif |
| 53 | |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 54 | static int riscv_timer_probe(struct udevice *dev) |
| 55 | { |
| 56 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
Torsten Duwe | 002858c | 2023-08-14 18:05:28 +0200 | [diff] [blame] | 57 | u32 rate; |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 58 | |
Torsten Duwe | 002858c | 2023-08-14 18:05:28 +0200 | [diff] [blame] | 59 | /* When this function was called from the CPU driver, clock |
| 60 | * frequency is passed as driver data. |
| 61 | */ |
| 62 | rate = dev->driver_data; |
| 63 | |
| 64 | /* When called from an FDT match, the rate needs to be looked up. */ |
| 65 | if (!rate && gd->fdt_blob) { |
| 66 | rate = fdt_getprop_u32_default(gd->fdt_blob, |
| 67 | "/cpus", "timebase-frequency", 0); |
| 68 | } |
| 69 | |
| 70 | uc_priv->clock_rate = rate; |
| 71 | |
| 72 | /* With rate==0, timer uclass post_probe might later fail with -EINVAL. |
| 73 | * Give a hint at the cause for debugging. |
| 74 | */ |
| 75 | if (!rate) |
| 76 | log_err("riscv_timer_probe with invalid clock rate 0!\n"); |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 77 | |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | static const struct timer_ops riscv_timer_ops = { |
| 82 | .get_count = riscv_timer_get_count, |
| 83 | }; |
| 84 | |
Torsten Duwe | 002858c | 2023-08-14 18:05:28 +0200 | [diff] [blame] | 85 | static const struct udevice_id riscv_timer_ids[] = { |
| 86 | { .compatible = "riscv,timer", }, |
| 87 | { } |
| 88 | }; |
| 89 | |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 90 | U_BOOT_DRIVER(riscv_timer) = { |
| 91 | .name = "riscv_timer", |
| 92 | .id = UCLASS_TIMER, |
Torsten Duwe | 002858c | 2023-08-14 18:05:28 +0200 | [diff] [blame] | 93 | .of_match = of_match_ptr(riscv_timer_ids), |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 94 | .probe = riscv_timer_probe, |
| 95 | .ops = &riscv_timer_ops, |
| 96 | .flags = DM_FLAG_PRE_RELOC, |
| 97 | }; |