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Masahiro Yamada0bc56842018-04-16 12:35:33 +09001// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier Pro5 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadac857ded2015-08-28 22:33:14 +09007
Masahiro Yamadac857ded2015-08-28 22:33:14 +09008/ {
Masahiro Yamada39a67ff2016-10-07 16:43:00 +09009 compatible = "socionext,uniphier-pro5";
Masahiro Yamada6cd78f72017-03-13 00:16:39 +090010 #address-cells = <1>;
11 #size-cells = <1>;
Masahiro Yamadac857ded2015-08-28 22:33:14 +090012
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
Masahiro Yamadac857ded2015-08-28 22:33:14 +090016
17 cpu@0 {
18 device_type = "cpu";
19 compatible = "arm,cortex-a9";
20 reg = <0>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +090021 clocks = <&sys_clk 32>;
Masahiro Yamada39a67ff2016-10-07 16:43:00 +090022 enable-method = "psci";
Masahiro Yamadab36f3052015-12-16 10:54:08 +090023 next-level-cache = <&l2>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +090024 operating-points-v2 = <&cpu_opp>;
Masahiro Yamadac857ded2015-08-28 22:33:14 +090025 };
26
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a9";
30 reg = <1>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +090031 clocks = <&sys_clk 32>;
Masahiro Yamada39a67ff2016-10-07 16:43:00 +090032 enable-method = "psci";
Masahiro Yamadab36f3052015-12-16 10:54:08 +090033 next-level-cache = <&l2>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +090034 operating-points-v2 = <&cpu_opp>;
Masahiro Yamadac857ded2015-08-28 22:33:14 +090035 };
36 };
37
Masahiro Yamada6c086d02017-11-25 00:25:35 +090038 cpu_opp: opp-table {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090039 compatible = "operating-points-v2";
40 opp-shared;
41
Masahiro Yamada552acbf2017-04-20 16:54:44 +090042 opp-100000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090043 opp-hz = /bits/ 64 <100000000>;
44 clock-latency-ns = <300>;
45 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090046 opp-116667000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090047 opp-hz = /bits/ 64 <116667000>;
48 clock-latency-ns = <300>;
49 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090050 opp-150000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090051 opp-hz = /bits/ 64 <150000000>;
52 clock-latency-ns = <300>;
53 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090054 opp-175000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090055 opp-hz = /bits/ 64 <175000000>;
56 clock-latency-ns = <300>;
57 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090058 opp-200000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090059 opp-hz = /bits/ 64 <200000000>;
60 clock-latency-ns = <300>;
61 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090062 opp-233334000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090063 opp-hz = /bits/ 64 <233334000>;
64 clock-latency-ns = <300>;
65 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090066 opp-300000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090067 opp-hz = /bits/ 64 <300000000>;
68 clock-latency-ns = <300>;
69 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090070 opp-350000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090071 opp-hz = /bits/ 64 <350000000>;
72 clock-latency-ns = <300>;
73 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090074 opp-400000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090075 opp-hz = /bits/ 64 <400000000>;
76 clock-latency-ns = <300>;
77 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090078 opp-466667000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090079 opp-hz = /bits/ 64 <466667000>;
80 clock-latency-ns = <300>;
81 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090082 opp-600000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090083 opp-hz = /bits/ 64 <600000000>;
84 clock-latency-ns = <300>;
85 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090086 opp-700000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090087 opp-hz = /bits/ 64 <700000000>;
88 clock-latency-ns = <300>;
89 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090090 opp-800000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090091 opp-hz = /bits/ 64 <800000000>;
92 clock-latency-ns = <300>;
93 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090094 opp-933334000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090095 opp-hz = /bits/ 64 <933334000>;
96 clock-latency-ns = <300>;
97 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +090098 opp-1200000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +090099 opp-hz = /bits/ 64 <1200000000>;
100 clock-latency-ns = <300>;
101 };
Masahiro Yamada552acbf2017-04-20 16:54:44 +0900102 opp-1400000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900103 opp-hz = /bits/ 64 <1400000000>;
104 clock-latency-ns = <300>;
105 };
106 };
107
108 psci {
109 compatible = "arm,psci-0.2";
110 method = "smc";
111 };
112
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900113 clocks {
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900114 refclk: ref {
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900115 compatible = "fixed-clock";
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900116 #clock-cells = <0>;
117 clock-frequency = <20000000>;
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900118 };
119
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900120 arm_timer_clk: arm-timer {
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900121 #clock-cells = <0>;
122 compatible = "fixed-clock";
123 clock-frequency = <50000000>;
124 };
125 };
126
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900127 soc {
128 compatible = "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
131 ranges;
132 interrupt-parent = <&intc>;
Masahiro Yamadab36f3052015-12-16 10:54:08 +0900133
Masahiro Yamada277516a2020-02-28 21:57:19 +0900134 l2: cache-controller@500c0000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900135 compatible = "socionext,uniphier-system-cache";
136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
137 <0x506c0000 0x400>;
138 interrupts = <0 190 4>, <0 191 4>;
139 cache-unified;
140 cache-size = <(2 * 1024 * 1024)>;
141 cache-sets = <512>;
142 cache-line-size = <128>;
143 cache-level = <2>;
144 next-level-cache = <&l3>;
145 };
Masahiro Yamadab36f3052015-12-16 10:54:08 +0900146
Masahiro Yamada277516a2020-02-28 21:57:19 +0900147 l3: cache-controller@500c8000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900148 compatible = "socionext,uniphier-system-cache";
149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
150 <0x506c8000 0x400>;
151 interrupts = <0 174 4>, <0 175 4>;
152 cache-unified;
153 cache-size = <(2 * 1024 * 1024)>;
154 cache-sets = <512>;
155 cache-line-size = <256>;
156 cache-level = <3>;
157 };
Masahiro Yamada6835b452016-02-16 17:03:51 +0900158
Masahiro Yamada6bd84d72018-12-19 20:03:21 +0900159 spi0: spi@54006000 {
160 compatible = "socionext,uniphier-scssi";
161 status = "disabled";
162 reg = <0x54006000 0x100>;
163 interrupts = <0 39 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_spi0>;
166 clocks = <&peri_clk 11>;
167 resets = <&peri_rst 11>;
168 };
169
170 spi1: spi@54006100 {
171 compatible = "socionext,uniphier-scssi";
172 status = "disabled";
173 reg = <0x54006100 0x100>;
174 interrupts = <0 216 4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_spi1>;
177 clocks = <&peri_clk 11>;
178 resets = <&peri_rst 11>;
179 };
180
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900181 serial0: serial@54006800 {
182 compatible = "socionext,uniphier-uart";
183 status = "disabled";
184 reg = <0x54006800 0x40>;
185 interrupts = <0 33 4>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_uart0>;
188 clocks = <&peri_clk 0>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900189 resets = <&peri_rst 0>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900190 };
Masahiro Yamada6835b452016-02-16 17:03:51 +0900191
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900192 serial1: serial@54006900 {
193 compatible = "socionext,uniphier-uart";
194 status = "disabled";
195 reg = <0x54006900 0x40>;
196 interrupts = <0 35 4>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart1>;
199 clocks = <&peri_clk 1>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900200 resets = <&peri_rst 1>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900201 };
Masahiro Yamada6835b452016-02-16 17:03:51 +0900202
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900203 serial2: serial@54006a00 {
204 compatible = "socionext,uniphier-uart";
205 status = "disabled";
206 reg = <0x54006a00 0x40>;
207 interrupts = <0 37 4>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_uart2>;
210 clocks = <&peri_clk 2>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900211 resets = <&peri_rst 2>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900212 };
Masahiro Yamada6835b452016-02-16 17:03:51 +0900213
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900214 serial3: serial@54006b00 {
215 compatible = "socionext,uniphier-uart";
216 status = "disabled";
217 reg = <0x54006b00 0x40>;
218 interrupts = <0 177 4>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_uart3>;
221 clocks = <&peri_clk 3>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900222 resets = <&peri_rst 3>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900223 };
Masahiro Yamada6835b452016-02-16 17:03:51 +0900224
Masahiro Yamada964edbf2017-10-13 19:21:52 +0900225 gpio: gpio@55000000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900226 compatible = "socionext,uniphier-gpio";
Masahiro Yamada964edbf2017-10-13 19:21:52 +0900227 reg = <0x55000000 0x200>;
228 interrupt-parent = <&aidet>;
229 interrupt-controller;
230 #interrupt-cells = <2>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900231 gpio-controller;
232 #gpio-cells = <2>;
Masahiro Yamada964edbf2017-10-13 19:21:52 +0900233 gpio-ranges = <&pinctrl 0 0 0>;
234 gpio-ranges-group-names = "gpio_range";
235 ngpios = <248>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900236 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900237 };
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900238
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900239 i2c0: i2c@58780000 {
240 compatible = "socionext,uniphier-fi2c";
241 status = "disabled";
242 reg = <0x58780000 0x80>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 interrupts = <0 41 4>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_i2c0>;
248 clocks = <&peri_clk 4>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900249 resets = <&peri_rst 4>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900250 clock-frequency = <100000>;
251 };
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900252
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900253 i2c1: i2c@58781000 {
254 compatible = "socionext,uniphier-fi2c";
255 status = "disabled";
256 reg = <0x58781000 0x80>;
257 #address-cells = <1>;
258 #size-cells = <0>;
259 interrupts = <0 42 4>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_i2c1>;
262 clocks = <&peri_clk 5>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900263 resets = <&peri_rst 5>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900264 clock-frequency = <100000>;
265 };
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900266
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900267 i2c2: i2c@58782000 {
268 compatible = "socionext,uniphier-fi2c";
269 status = "disabled";
270 reg = <0x58782000 0x80>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 interrupts = <0 43 4>;
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_i2c2>;
276 clocks = <&peri_clk 6>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900277 resets = <&peri_rst 6>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900278 clock-frequency = <100000>;
279 };
Masahiro Yamada2707e832016-06-29 19:39:02 +0900280
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900281 i2c3: i2c@58783000 {
282 compatible = "socionext,uniphier-fi2c";
283 status = "disabled";
284 reg = <0x58783000 0x80>;
285 #address-cells = <1>;
286 #size-cells = <0>;
287 interrupts = <0 44 4>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_i2c3>;
290 clocks = <&peri_clk 7>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900291 resets = <&peri_rst 7>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900292 clock-frequency = <100000>;
293 };
Masahiro Yamada299307d2016-02-18 19:52:50 +0900294
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900295 /* i2c4 does not exist */
Masahiro Yamada299307d2016-02-18 19:52:50 +0900296
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900297 /* chip-internal connection for DMD */
298 i2c5: i2c@58785000 {
299 compatible = "socionext,uniphier-fi2c";
300 reg = <0x58785000 0x80>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 interrupts = <0 25 4>;
304 clocks = <&peri_clk 9>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900305 resets = <&peri_rst 9>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900306 clock-frequency = <400000>;
307 };
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900308
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900309 /* chip-internal connection for HDMI */
310 i2c6: i2c@58786000 {
311 compatible = "socionext,uniphier-fi2c";
312 reg = <0x58786000 0x80>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 interrupts = <0 26 4>;
316 clocks = <&peri_clk 10>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900317 resets = <&peri_rst 10>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900318 clock-frequency = <400000>;
319 };
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900320
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900321 system_bus: system-bus@58c00000 {
322 compatible = "socionext,uniphier-system-bus";
323 status = "disabled";
324 reg = <0x58c00000 0x400>;
325 #address-cells = <2>;
326 #size-cells = <1>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_system_bus>;
329 };
Masahiro Yamada224e2f72016-02-02 21:11:33 +0900330
Masahiro Yamada938ab162017-05-15 14:23:46 +0900331 smpctrl@59801000 {
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900332 compatible = "socionext,uniphier-smpctrl";
333 reg = <0x59801000 0x400>;
334 };
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900335
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900336 sdctrl@59810000 {
337 compatible = "socionext,uniphier-pro5-sdctrl",
338 "simple-mfd", "syscon";
Masahiro Yamada1a420bd2017-08-29 12:20:52 +0900339 reg = <0x59810000 0x400>;
Masahiro Yamadaa4e54cc2015-11-04 21:56:07 +0900340
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900341 sd_clk: clock {
342 compatible = "socionext,uniphier-pro5-sd-clock";
343 #clock-cells = <1>;
344 };
Masahiro Yamadaa4e54cc2015-11-04 21:56:07 +0900345
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900346 sd_rst: reset {
347 compatible = "socionext,uniphier-pro5-sd-reset";
348 #reset-cells = <1>;
349 };
350 };
Masahiro Yamadac857ded2015-08-28 22:33:14 +0900351
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900352 perictrl@59820000 {
353 compatible = "socionext,uniphier-pro5-perictrl",
354 "simple-mfd", "syscon";
355 reg = <0x59820000 0x200>;
Masahiro Yamada02bf5b82016-09-22 07:42:23 +0900356
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900357 peri_clk: clock {
358 compatible = "socionext,uniphier-pro5-peri-clock";
359 #clock-cells = <1>;
360 };
Masahiro Yamada02bf5b82016-09-22 07:42:23 +0900361
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900362 peri_rst: reset {
363 compatible = "socionext,uniphier-pro5-peri-reset";
364 #reset-cells = <1>;
365 };
366 };
Masahiro Yamada1d5df7b2016-02-02 21:11:36 +0900367
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900368 soc-glue@5f800000 {
369 compatible = "socionext,uniphier-pro5-soc-glue",
370 "simple-mfd", "syscon";
371 reg = <0x5f800000 0x2000>;
Masahiro Yamada80951832016-02-02 21:11:35 +0900372
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900373 pinctrl: pinctrl {
374 compatible = "socionext,uniphier-pro5-pinctrl";
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900375 };
376 };
Masahiro Yamadae84513b2016-02-02 21:11:34 +0900377
Masahiro Yamadab61327d2018-03-15 11:43:03 +0900378 soc-glue@5f900000 {
379 compatible = "socionext,uniphier-pro5-soc-glue-debug",
380 "simple-mfd";
381 #address-cells = <1>;
382 #size-cells = <1>;
383 ranges = <0 0x5f900000 0x2000>;
384
385 efuse@100 {
386 compatible = "socionext,uniphier-efuse";
387 reg = <0x100 0x28>;
388 };
389
390 efuse@130 {
391 compatible = "socionext,uniphier-efuse";
392 reg = <0x130 0x8>;
393 };
394
395 efuse@200 {
396 compatible = "socionext,uniphier-efuse";
397 reg = <0x200 0x28>;
398 };
399
400 efuse@300 {
401 compatible = "socionext,uniphier-efuse";
402 reg = <0x300 0x14>;
403 };
404
405 efuse@400 {
406 compatible = "socionext,uniphier-efuse";
407 reg = <0x400 0x8>;
408 };
409 };
410
Masahiro Yamada277516a2020-02-28 21:57:19 +0900411 aidet: interrupt-controller@5fc20000 {
Masahiro Yamada1a420bd2017-08-29 12:20:52 +0900412 compatible = "socionext,uniphier-pro5-aidet";
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900413 reg = <0x5fc20000 0x200>;
Masahiro Yamada1a420bd2017-08-29 12:20:52 +0900414 interrupt-controller;
415 #interrupt-cells = <2>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900416 };
417
418 timer@60000200 {
419 compatible = "arm,cortex-a9-global-timer";
420 reg = <0x60000200 0x20>;
421 interrupts = <1 11 0x304>;
422 clocks = <&arm_timer_clk>;
423 };
424
425 timer@60000600 {
426 compatible = "arm,cortex-a9-twd-timer";
427 reg = <0x60000600 0x20>;
428 interrupts = <1 13 0x304>;
429 clocks = <&arm_timer_clk>;
430 };
431
432 intc: interrupt-controller@60001000 {
433 compatible = "arm,cortex-a9-gic";
434 reg = <0x60001000 0x1000>,
435 <0x60000100 0x100>;
436 #interrupt-cells = <3>;
437 interrupt-controller;
438 };
439
440 sysctrl@61840000 {
441 compatible = "socionext,uniphier-pro5-sysctrl",
442 "simple-mfd", "syscon";
443 reg = <0x61840000 0x10000>;
444
445 sys_clk: clock {
446 compatible = "socionext,uniphier-pro5-clock";
447 #clock-cells = <1>;
448 };
449
450 sys_rst: reset {
451 compatible = "socionext,uniphier-pro5-reset";
452 #reset-cells = <1>;
453 };
454 };
455
456 usb0: usb@65b00000 {
457 compatible = "socionext,uniphier-pro5-dwc3";
458 status = "disabled";
459 reg = <0x65b00000 0x1000>;
460 #address-cells = <1>;
461 #size-cells = <1>;
462 ranges;
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_usb0>;
465 dwc3@65a00000 {
466 compatible = "snps,dwc3";
467 reg = <0x65a00000 0x10000>;
468 interrupts = <0 134 4>;
Masahiro Yamadad2c8abd2017-08-13 09:01:17 +0900469 dr_mode = "host";
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900470 tx-fifo-resize;
471 };
472 };
473
474 usb1: usb@65d00000 {
475 compatible = "socionext,uniphier-pro5-dwc3";
476 status = "disabled";
477 reg = <0x65d00000 0x1000>;
478 #address-cells = <1>;
479 #size-cells = <1>;
480 ranges;
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
483 dwc3@65c00000 {
484 compatible = "snps,dwc3";
485 reg = <0x65c00000 0x10000>;
486 interrupts = <0 137 4>;
Masahiro Yamadad2c8abd2017-08-13 09:01:17 +0900487 dr_mode = "host";
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900488 tx-fifo-resize;
489 };
490 };
491
Masahiro Yamada277516a2020-02-28 21:57:19 +0900492 nand: nand-controller@68000000 {
Masahiro Yamada552acbf2017-04-20 16:54:44 +0900493 compatible = "socionext,uniphier-denali-nand-v5b";
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900494 status = "disabled";
495 reg-names = "nand_data", "denali_reg";
496 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
497 interrupts = <0 65 4>;
498 pinctrl-names = "default";
Masahiro Yamada1a420bd2017-08-29 12:20:52 +0900499 pinctrl-0 = <&pinctrl_nand2cs>;
Masahiro Yamada6bd84d72018-12-19 20:03:21 +0900500 clock-names = "nand", "nand_x", "ecc";
501 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
Masahiro Yamada6c086d02017-11-25 00:25:35 +0900502 resets = <&sys_rst 2>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900503 };
Masahiro Yamada02bf5b82016-09-22 07:42:23 +0900504
Masahiro Yamada277516a2020-02-28 21:57:19 +0900505 emmc: mmc@68400000 {
Masahiro Yamada6c7ad4d2018-09-10 12:58:35 +0900506 compatible = "socionext,uniphier-sd-v3.1";
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900507 status = "disabled";
508 reg = <0x68400000 0x800>;
509 interrupts = <0 78 4>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_emmc>;
512 clocks = <&sd_clk 1>;
Masahiro Yamada6c7ad4d2018-09-10 12:58:35 +0900513 reset-names = "host", "hw";
514 resets = <&sd_rst 1>, <&sd_rst 6>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900515 bus-width = <8>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900516 cap-mmc-highspeed;
517 cap-mmc-hw-reset;
Masahiro Yamada6c7ad4d2018-09-10 12:58:35 +0900518 non-removable;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900519 };
520
Masahiro Yamada277516a2020-02-28 21:57:19 +0900521 sd: mmc@68800000 {
Masahiro Yamada6c7ad4d2018-09-10 12:58:35 +0900522 compatible = "socionext,uniphier-sd-v3.1";
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900523 status = "disabled";
524 reg = <0x68800000 0x800>;
525 interrupts = <0 76 4>;
Masahiro Yamada6c7ad4d2018-09-10 12:58:35 +0900526 pinctrl-names = "default", "uhs";
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900527 pinctrl-0 = <&pinctrl_sd>;
Masahiro Yamada6c7ad4d2018-09-10 12:58:35 +0900528 pinctrl-1 = <&pinctrl_sd_uhs>;
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900529 clocks = <&sd_clk 0>;
530 reset-names = "host";
531 resets = <&sd_rst 0>;
532 bus-width = <4>;
533 cap-sd-highspeed;
534 sd-uhs-sdr12;
535 sd-uhs-sdr25;
536 sd-uhs-sdr50;
537 };
538 };
Masahiro Yamadae84513b2016-02-02 21:11:34 +0900539};
Masahiro Yamada6e485b22016-12-05 18:31:39 +0900540
Masahiro Yamada1a420bd2017-08-29 12:20:52 +0900541#include "uniphier-pinctrl.dtsi"