blob: 7db9d25544ce323f3d557e2e3b72776f35156130 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Max Krummenachereeb16b22016-11-30 19:43:09 +01002/*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
Marcel Ziswiler3e43a502019-02-08 18:42:10 +01005 * Copyright (C) 2014-2019, Toradex AG
Max Krummenachereeb16b22016-11-30 19:43:09 +01006 * copied from nitrogen6x
Max Krummenachereeb16b22016-11-30 19:43:09 +01007 */
8
9#include <common.h>
Simon Glass11c89f32017-05-17 17:18:03 -060010#include <dm.h>
Simon Glass6eaea252019-08-01 09:46:48 -060011#include <env.h>
Simon Glassa7b51302019-11-14 12:57:46 -070012#include <init.h>
Marcel Ziswiler3e43a502019-02-08 18:42:10 +010013
Max Krummenachereeb16b22016-11-30 19:43:09 +010014#include <asm/arch/clock.h>
15#include <asm/arch/crm_regs.h>
16#include <asm/arch/imx-regs.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010017#include <asm/arch/mx6-ddr.h>
Marcel Ziswiler3e43a502019-02-08 18:42:10 +010018#include <asm/arch/mx6-pins.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010019#include <asm/arch/mxc_hdmi.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/bootm.h>
22#include <asm/gpio.h>
Marcel Ziswiler3e43a502019-02-08 18:42:10 +010023#include <asm/mach-imx/boot_mode.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020024#include <asm/mach-imx/iomux-v3.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020025#include <asm/mach-imx/sata.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020026#include <asm/mach-imx/video.h>
Bhuvanchandra DVcd6072c2019-02-08 18:42:24 +010027#include <cpu.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010028#include <dm/platform_data/serial_mxc.h>
Yangbo Lu73340382019-06-21 11:42:28 +080029#include <fsl_esdhc_imx.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010030#include <imx_thermal.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010031#include <miiphy.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010032#include <netdev.h>
Gerard Salvatella7fba5092019-02-08 18:42:28 +010033#include <cpu.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010034
35#include "../common/tdx-cfg-block.h"
36#ifdef CONFIG_TDX_CMD_IMX_MFGR
37#include "pf0100.h"
38#endif
39
40DECLARE_GLOBAL_DATA_PTR;
41
42#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
Max Krummenachera0f4d792019-02-08 18:42:19 +010047 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
48 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49
50#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
Max Krummenachereeb16b22016-11-30 19:43:09 +010051 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
52 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
53
Max Krummenachereeb16b22016-11-30 19:43:09 +010054#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
55 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
56 PAD_CTL_SRE_SLOW)
57
58#define NO_PULLUP ( \
59 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
60 PAD_CTL_SRE_SLOW)
61
62#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
64 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
65
Max Krummenachereeb16b22016-11-30 19:43:09 +010066#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
67
68int dram_init(void)
69{
70 /* use the DDR controllers configured size */
71 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
72 (ulong)imx_ddr_size());
73
74 return 0;
75}
76
77/* Colibri UARTA */
78iomux_v3_cfg_t const uart1_pads[] = {
79 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
80 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
81};
82
Igor Opaniuk6c6a9862019-12-06 18:24:16 +020083#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
Marcel Ziswilerc882cfb2019-02-08 18:42:12 +010084/* Colibri MMC */
Max Krummenachereeb16b22016-11-30 19:43:09 +010085iomux_v3_cfg_t const usdhc1_pads[] = {
86 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
93# define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
94};
95
96/* eMMC */
97iomux_v3_cfg_t const usdhc3_pads[] = {
Max Krummenachera0f4d792019-02-08 18:42:19 +010098 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
99 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
100 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
101 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
102 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
103 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
104 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
105 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
106 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
107 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
Max Krummenachereeb16b22016-11-30 19:43:09 +0100108 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109};
Yangbo Lu73340382019-06-21 11:42:28 +0800110#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
Max Krummenachereeb16b22016-11-30 19:43:09 +0100111
Max Krummenachereeb16b22016-11-30 19:43:09 +0100112/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
113iomux_v3_cfg_t const gpio_pads[] = {
114 /* ADDRESS[17:18] [25] used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100115 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
116 MUX_MODE_SION,
117 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
118 MUX_MODE_SION,
119 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
120 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100121 /* ADDRESS[19:24] used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100122 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
123 MUX_MODE_SION,
124 MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
125 MUX_MODE_SION,
126 MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
127 MUX_MODE_SION,
128 MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
129 MUX_MODE_SION,
130 MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
131 MUX_MODE_SION,
132 MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
133 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100134 /* DATA[16:29] [31] used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100135 MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
136 MUX_MODE_SION,
137 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
138 MUX_MODE_SION,
139 MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
140 MUX_MODE_SION,
141 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
142 MUX_MODE_SION,
143 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
144 MUX_MODE_SION,
145 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
146 MUX_MODE_SION,
147 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
148 MUX_MODE_SION,
149 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
150 MUX_MODE_SION,
151 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
152 MUX_MODE_SION,
153 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
154 MUX_MODE_SION,
155 MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
156 MUX_MODE_SION,
157 MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
158 MUX_MODE_SION,
159 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
160 MUX_MODE_SION,
161 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
162 MUX_MODE_SION,
163 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
164 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100165 /* DQM[0:3] used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100166 MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
167 MUX_MODE_SION,
168 MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
169 MUX_MODE_SION,
170 MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
171 MUX_MODE_SION,
172 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
173 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100174 /* RDY used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100175 MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
176 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100177 /* ADDRESS[16] DATA[30] used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100178 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
179 MUX_MODE_SION,
180 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
181 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100182 /* CSI pins used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100183 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
184 MUX_MODE_SION,
185 MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
186 MUX_MODE_SION,
187 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
188 MUX_MODE_SION,
189 MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
190 MUX_MODE_SION,
191 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
192 MUX_MODE_SION,
193 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
194 MUX_MODE_SION,
195 MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
196 MUX_MODE_SION,
197 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
198 MUX_MODE_SION,
199 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
200 MUX_MODE_SION,
201 MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
202 MUX_MODE_SION,
203 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
204 MUX_MODE_SION,
205 MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
206 MUX_MODE_SION,
207 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
208 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100209 /* GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100210 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
211 MUX_MODE_SION,
212 MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
213 MUX_MODE_SION,
214 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
215 MUX_MODE_SION,
216 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
217 MUX_MODE_SION,
218 MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
219 MUX_MODE_SION,
220 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
221 MUX_MODE_SION,
222 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
223 MUX_MODE_SION,
224 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
225 MUX_MODE_SION,
226 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
227 MUX_MODE_SION,
228 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
229 MUX_MODE_SION,
230 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
231 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100232 /* USBH_OC */
233 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
234 /* USBC_ID */
235 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
236 /* USBC_DET */
237 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
238};
239
240static void setup_iomux_gpio(void)
241{
242 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
243}
244
245iomux_v3_cfg_t const usb_pads[] = {
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100246 /* USBH_PEN */
247 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100248# define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
249};
250
251/*
252 * UARTs are used in DTE mode, switch the mode on all UARTs before
253 * any pinmuxing connects a (DCE) output to a transceiver output.
254 */
Max Krummenacher003bc132019-02-08 18:42:21 +0100255#define UCR3 0x88 /* FIFO Control Register */
256#define UCR3_RI BIT(8) /* RIDELT DTE mode */
257#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
Max Krummenachereeb16b22016-11-30 19:43:09 +0100258#define UFCR 0x90 /* FIFO Control Register */
Max Krummenacher003bc132019-02-08 18:42:21 +0100259#define UFCR_DCEDTE BIT(6) /* DCE=0 */
Max Krummenachereeb16b22016-11-30 19:43:09 +0100260
261static void setup_dtemode_uart(void)
262{
263 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
264 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
265 setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
Max Krummenacher003bc132019-02-08 18:42:21 +0100266
267 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
268 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
269 clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
Max Krummenachereeb16b22016-11-30 19:43:09 +0100270}
271
272static void setup_iomux_uart(void)
273{
274 setup_dtemode_uart();
275 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
276}
277
278#ifdef CONFIG_USB_EHCI_MX6
279int board_ehci_hcd_init(int port)
280{
281 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
282 return 0;
283}
Marcel Ziswilerf2839442019-02-08 18:42:15 +0100284#endif
Max Krummenachereeb16b22016-11-30 19:43:09 +0100285
Igor Opaniuk6c6a9862019-12-06 18:24:16 +0200286#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
Max Krummenachereeb16b22016-11-30 19:43:09 +0100287/* use the following sequence: eMMC, MMC */
288struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
289 {USDHC3_BASE_ADDR},
290 {USDHC1_BASE_ADDR},
291};
292
293int board_mmc_getcd(struct mmc *mmc)
294{
295 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
296 int ret = true; /* default: assume inserted */
297
298 switch (cfg->esdhc_base) {
299 case USDHC1_BASE_ADDR:
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100300 gpio_request(GPIO_MMC_CD, "MMC_CD");
Max Krummenachereeb16b22016-11-30 19:43:09 +0100301 gpio_direction_input(GPIO_MMC_CD);
302 ret = !gpio_get_value(GPIO_MMC_CD);
303 break;
304 }
305
306 return ret;
307}
308
309int board_mmc_init(bd_t *bis)
310{
Max Krummenachereeb16b22016-11-30 19:43:09 +0100311 struct src *psrc = (struct src *)SRC_BASE_ADDR;
312 unsigned reg = readl(&psrc->sbmr1) >> 11;
313 /*
314 * Upon reading BOOT_CFG register the following map is done:
315 * Bit 11 and 12 of BOOT_CFG register can determine the current
316 * mmc port
317 * 0x1 SD1
318 * 0x2 SD2
319 * 0x3 SD4
320 */
321
322 switch (reg & 0x3) {
323 case 0x0:
324 imx_iomux_v3_setup_multiple_pads(
325 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
326 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
327 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
328 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
329 break;
330 case 0x2:
331 imx_iomux_v3_setup_multiple_pads(
332 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
333 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
334 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
335 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
336 break;
337 default:
338 puts("MMC boot device not available");
339 }
340
341 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
Max Krummenachereeb16b22016-11-30 19:43:09 +0100342}
Yangbo Lu73340382019-06-21 11:42:28 +0800343#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
Max Krummenachereeb16b22016-11-30 19:43:09 +0100344
345int board_phy_config(struct phy_device *phydev)
346{
347 if (phydev->drv->config)
348 phydev->drv->config(phydev);
349
350 return 0;
351}
352
Igor Opaniuk03e68cd2019-11-04 11:12:00 +0100353int setup_fec(void)
Max Krummenachereeb16b22016-11-30 19:43:09 +0100354{
Max Krummenachereeb16b22016-11-30 19:43:09 +0100355 int ret;
356
357 /* provide the PHY clock from the i.MX 6 */
358 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
359 if (ret)
360 return ret;
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100361
Max Krummenachereeb16b22016-11-30 19:43:09 +0100362 return 0;
363}
364
365static iomux_v3_cfg_t const pwr_intb_pads[] = {
366 /*
367 * the bootrom sets the iomux to vselect, potentially connecting
368 * two outputs. Set this back to GPIO
369 */
370 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
371};
372
373#if defined(CONFIG_VIDEO_IPUV3)
374
375static iomux_v3_cfg_t const backlight_pads[] = {
376 /* Backlight On */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100377 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100378#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
379 /* Backlight PWM, used as GPIO in U-Boot */
380 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100381 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
382 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100383#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
384};
385
386static iomux_v3_cfg_t const rgb_pads[] = {
387 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
388 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
389 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
390 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
391 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
392 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
393 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
394 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
395 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
396 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
397 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
398 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
399 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
400 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
401 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
402 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
403 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
404 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
405 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
406 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
407 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
408 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
409};
410
411static void do_enable_hdmi(struct display_info_t const *dev)
412{
413 imx_enable_hdmi_phy();
414}
415
416static void enable_rgb(struct display_info_t const *dev)
417{
418 imx_iomux_v3_setup_multiple_pads(
419 rgb_pads,
420 ARRAY_SIZE(rgb_pads));
421 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
422 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
423}
424
425static int detect_default(struct display_info_t const *dev)
426{
427 (void) dev;
428 return 1;
429}
430
431struct display_info_t const displays[] = {{
432 .bus = -1,
433 .addr = 0,
434 .pixfmt = IPU_PIX_FMT_RGB24,
435 .detect = detect_hdmi,
436 .enable = do_enable_hdmi,
437 .mode = {
438 .name = "HDMI",
439 .refresh = 60,
440 .xres = 1024,
441 .yres = 768,
442 .pixclock = 15385,
443 .left_margin = 220,
444 .right_margin = 40,
445 .upper_margin = 21,
446 .lower_margin = 7,
447 .hsync_len = 60,
448 .vsync_len = 10,
449 .sync = FB_SYNC_EXT,
450 .vmode = FB_VMODE_NONINTERLACED
451} }, {
452 .bus = -1,
453 .addr = 0,
454 .pixfmt = IPU_PIX_FMT_RGB666,
455 .detect = detect_default,
456 .enable = enable_rgb,
457 .mode = {
458 .name = "vga-rgb",
459 .refresh = 60,
460 .xres = 640,
461 .yres = 480,
462 .pixclock = 33000,
463 .left_margin = 48,
464 .right_margin = 16,
465 .upper_margin = 31,
466 .lower_margin = 11,
467 .hsync_len = 96,
468 .vsync_len = 2,
469 .sync = 0,
470 .vmode = FB_VMODE_NONINTERLACED
471} }, {
472 .bus = -1,
473 .addr = 0,
474 .pixfmt = IPU_PIX_FMT_RGB666,
475 .enable = enable_rgb,
476 .mode = {
477 .name = "wvga-rgb",
478 .refresh = 60,
479 .xres = 800,
480 .yres = 480,
481 .pixclock = 25000,
482 .left_margin = 40,
483 .right_margin = 88,
484 .upper_margin = 33,
485 .lower_margin = 10,
486 .hsync_len = 128,
487 .vsync_len = 2,
488 .sync = 0,
489 .vmode = FB_VMODE_NONINTERLACED
490} } };
491size_t display_count = ARRAY_SIZE(displays);
492
493static void setup_display(void)
494{
495 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
496 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
497 int reg;
498
499 enable_ipu_clock();
500 imx_setup_hdmi();
501 /* Turn on LDB0,IPU,IPU DI0 clocks */
502 reg = __raw_readl(&mxc_ccm->CCGR3);
503 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
504 writel(reg, &mxc_ccm->CCGR3);
505
506 /* set LDB0, LDB1 clk select to 011/011 */
507 reg = readl(&mxc_ccm->cs2cdr);
508 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
509 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
510 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
511 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
512 writel(reg, &mxc_ccm->cs2cdr);
513
514 reg = readl(&mxc_ccm->cscmr2);
515 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
516 writel(reg, &mxc_ccm->cscmr2);
517
518 reg = readl(&mxc_ccm->chsccdr);
519 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
520 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
521 writel(reg, &mxc_ccm->chsccdr);
522
523 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
524 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
525 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
526 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
527 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
528 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
529 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
530 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
531 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
532 writel(reg, &iomux->gpr[2]);
533
534 reg = readl(&iomux->gpr[3]);
535 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
536 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
537 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
538 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
539 writel(reg, &iomux->gpr[3]);
540
541 /* backlight unconditionally on for now */
542 imx_iomux_v3_setup_multiple_pads(backlight_pads,
543 ARRAY_SIZE(backlight_pads));
544 /* use 0 for EDT 7", use 1 for LG fullHD panel */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100545 gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
546 gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
Max Krummenachereeb16b22016-11-30 19:43:09 +0100547 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
548 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
549}
Gerard Salvatella108d7392018-11-19 15:54:10 +0100550
551/*
552 * Backlight off before OS handover
553 */
554void board_preboot_os(void)
555{
556 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
557 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
558}
Max Krummenachereeb16b22016-11-30 19:43:09 +0100559#endif /* defined(CONFIG_VIDEO_IPUV3) */
560
561int board_early_init_f(void)
562{
563 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
564 ARRAY_SIZE(pwr_intb_pads));
565 setup_iomux_uart();
566
Max Krummenachereeb16b22016-11-30 19:43:09 +0100567 return 0;
568}
569
570/*
571 * Do not overwrite the console
572 * Use always serial for U-Boot console
573 */
574int overwrite_console(void)
575{
576 return 1;
577}
578
579int board_init(void)
580{
581 /* address of boot parameters */
582 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
Igor Opaniuk03e68cd2019-11-04 11:12:00 +0100583#if defined(CONFIG_FEC_MXC)
584 setup_fec();
585#endif
Fabio Estevamfd2525a2017-09-22 23:45:33 -0300586#if defined(CONFIG_VIDEO_IPUV3)
587 setup_display();
588#endif
589
Max Krummenachereeb16b22016-11-30 19:43:09 +0100590#ifdef CONFIG_TDX_CMD_IMX_MFGR
591 (void) pmic_init();
592#endif
593
Simon Glassab3055a2017-06-14 21:28:25 -0600594#ifdef CONFIG_SATA
Max Krummenachereeb16b22016-11-30 19:43:09 +0100595 setup_sata();
596#endif
597
598 setup_iomux_gpio();
599
600 return 0;
601}
602
603#ifdef CONFIG_BOARD_LATE_INIT
604int board_late_init(void)
605{
606#if defined(CONFIG_REVISION_TAG) && \
607 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
608 char env_str[256];
609 u32 rev;
610
611 rev = get_board_rev();
612 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
Simon Glass6a38e412017-08-03 12:22:09 -0600613 env_set("board_rev", env_str);
Max Krummenachereeb16b22016-11-30 19:43:09 +0100614#endif
615
Stefan Agnerea8e2e92019-02-08 18:42:26 +0100616#ifdef CONFIG_CMD_USB_SDP
617 if (is_boot_from_usb()) {
618 printf("Serial Downloader recovery mode, using sdp command\n");
619 env_set("bootdelay", "0");
620 env_set("bootcmd", "sdp 0");
621 }
622#endif /* CONFIG_CMD_USB_SDP */
623
Max Krummenachereeb16b22016-11-30 19:43:09 +0100624 return 0;
625}
626#endif /* CONFIG_BOARD_LATE_INIT */
627
Max Krummenachereeb16b22016-11-30 19:43:09 +0100628int checkboard(void)
629{
630 char it[] = " IT";
631 int minc, maxc;
632
633 switch (get_cpu_temp_grade(&minc, &maxc)) {
634 case TEMP_AUTOMOTIVE:
635 case TEMP_INDUSTRIAL:
636 break;
637 case TEMP_EXTCOMMERCIAL:
638 default:
639 it[0] = 0;
640 };
641 printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
642 is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
643 (gd->ram_size == 0x20000000) ? "512" : "256", it);
644 return 0;
645}
646
647#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
648int ft_board_setup(void *blob, bd_t *bd)
649{
Bhuvanchandra DVcd6072c2019-02-08 18:42:24 +0100650 u32 cma_size;
651
652 ft_common_board_setup(blob, bd);
653
Stefan Agnerea8e2e92019-02-08 18:42:26 +0100654 cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
Bhuvanchandra DVcd6072c2019-02-08 18:42:24 +0100655 cma_size = min((u32)(gd->ram_size >> 1), cma_size);
656
657 fdt_setprop_u32(blob,
658 fdt_path_offset(blob, "/reserved-memory/linux,cma"),
659 "size",
660 cma_size);
661 return 0;
Max Krummenachereeb16b22016-11-30 19:43:09 +0100662}
663#endif
664
665#ifdef CONFIG_CMD_BMODE
666static const struct boot_mode board_boot_modes[] = {
667 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
668 {NULL, 0},
669};
670#endif
671
672int misc_init_r(void)
673{
674#ifdef CONFIG_CMD_BMODE
675 add_board_boot_modes(board_boot_modes);
676#endif
677 return 0;
678}
679
680#ifdef CONFIG_LDO_BYPASS_CHECK
681/* TODO, use external pmic, for now always ldo_enable */
682void ldo_mode_set(int ldo_bypass)
683{
684 return;
685}
686#endif
687
688#ifdef CONFIG_SPL_BUILD
689#include <spl.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +0900690#include <linux/libfdt.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +0100691#include "asm/arch/mx6dl-ddr.h"
692#include "asm/arch/iomux.h"
693#include "asm/arch/crm_regs.h"
694
695static int mx6s_dcd_table[] = {
696/* ddr-setup.cfg */
697
698MX6_IOM_DRAM_SDQS0, 0x00000030,
699MX6_IOM_DRAM_SDQS1, 0x00000030,
700MX6_IOM_DRAM_SDQS2, 0x00000030,
701MX6_IOM_DRAM_SDQS3, 0x00000030,
702MX6_IOM_DRAM_SDQS4, 0x00000030,
703MX6_IOM_DRAM_SDQS5, 0x00000030,
704MX6_IOM_DRAM_SDQS6, 0x00000030,
705MX6_IOM_DRAM_SDQS7, 0x00000030,
706
707MX6_IOM_GRP_B0DS, 0x00000030,
708MX6_IOM_GRP_B1DS, 0x00000030,
709MX6_IOM_GRP_B2DS, 0x00000030,
710MX6_IOM_GRP_B3DS, 0x00000030,
711MX6_IOM_GRP_B4DS, 0x00000030,
712MX6_IOM_GRP_B5DS, 0x00000030,
713MX6_IOM_GRP_B6DS, 0x00000030,
714MX6_IOM_GRP_B7DS, 0x00000030,
715MX6_IOM_GRP_ADDDS, 0x00000030,
716/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
717MX6_IOM_GRP_CTLDS, 0x00000030,
718
719MX6_IOM_DRAM_DQM0, 0x00020030,
720MX6_IOM_DRAM_DQM1, 0x00020030,
721MX6_IOM_DRAM_DQM2, 0x00020030,
722MX6_IOM_DRAM_DQM3, 0x00020030,
723MX6_IOM_DRAM_DQM4, 0x00020030,
724MX6_IOM_DRAM_DQM5, 0x00020030,
725MX6_IOM_DRAM_DQM6, 0x00020030,
726MX6_IOM_DRAM_DQM7, 0x00020030,
727
728MX6_IOM_DRAM_CAS, 0x00020030,
729MX6_IOM_DRAM_RAS, 0x00020030,
730MX6_IOM_DRAM_SDCLK_0, 0x00020030,
731MX6_IOM_DRAM_SDCLK_1, 0x00020030,
732
733MX6_IOM_DRAM_RESET, 0x00020030,
734MX6_IOM_DRAM_SDCKE0, 0x00003000,
735MX6_IOM_DRAM_SDCKE1, 0x00003000,
736
737MX6_IOM_DRAM_SDODT0, 0x00003030,
738MX6_IOM_DRAM_SDODT1, 0x00003030,
739
740/* (differential input) */
741MX6_IOM_DDRMODE_CTL, 0x00020000,
742/* (differential input) */
743MX6_IOM_GRP_DDRMODE, 0x00020000,
744/* disable ddr pullups */
745MX6_IOM_GRP_DDRPKE, 0x00000000,
746MX6_IOM_DRAM_SDBA2, 0x00000000,
747/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
748MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
749
750/* Read data DQ Byte0-3 delay */
751MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
752MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
753MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
754MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
755MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
756MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
757MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
758MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
759
760/*
761 * MDMISC mirroring interleaved (row/bank/col)
762 */
763/* TODO: check what the RALAT field does */
764MX6_MMDC_P0_MDMISC, 0x00081740,
765
766/*
767 * MDSCR con_req
768 */
769MX6_MMDC_P0_MDSCR, 0x00008000,
770
771
772/* 800mhz_2x64mx16.cfg */
773
774MX6_MMDC_P0_MDPDC, 0x0002002D,
775MX6_MMDC_P0_MDCFG0, 0x2C305503,
776MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
777MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
778MX6_MMDC_P0_MDRWD, 0x000026D2,
779MX6_MMDC_P0_MDOR, 0x00301023,
780MX6_MMDC_P0_MDOTC, 0x00333030,
781MX6_MMDC_P0_MDPDC, 0x0002556D,
782/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
783MX6_MMDC_P0_MDASP, 0x00000017,
784/* DDR3 DATA BUS SIZE: 64BIT */
785/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
786/* DDR3 DATA BUS SIZE: 32BIT */
787MX6_MMDC_P0_MDCTL, 0x82190000,
788
789/* Write commands to DDR */
790/* Load Mode Registers */
791/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
792/* MX6_MMDC_P0_MDSCR, 0x04408032, */
793MX6_MMDC_P0_MDSCR, 0x04008032,
794MX6_MMDC_P0_MDSCR, 0x00008033,
795MX6_MMDC_P0_MDSCR, 0x00048031,
796MX6_MMDC_P0_MDSCR, 0x13208030,
797/* ZQ calibration */
798MX6_MMDC_P0_MDSCR, 0x04008040,
799
800MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
801MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
802MX6_MMDC_P0_MDREF, 0x00005800,
803
804MX6_MMDC_P0_MPODTCTRL, 0x00000000,
805MX6_MMDC_P1_MPODTCTRL, 0x00000000,
806
807MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
808MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
809MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
810MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
811
812MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
813MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
814MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
815MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
816
817MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
818MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
819MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
820MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
821
822MX6_MMDC_P0_MPMUR0, 0x00000800,
823MX6_MMDC_P1_MPMUR0, 0x00000800,
824MX6_MMDC_P0_MDSCR, 0x00000000,
825MX6_MMDC_P0_MAPSR, 0x00011006,
826};
827
828static int mx6dl_dcd_table[] = {
829/* ddr-setup.cfg */
830
831MX6_IOM_DRAM_SDQS0, 0x00000030,
832MX6_IOM_DRAM_SDQS1, 0x00000030,
833MX6_IOM_DRAM_SDQS2, 0x00000030,
834MX6_IOM_DRAM_SDQS3, 0x00000030,
835MX6_IOM_DRAM_SDQS4, 0x00000030,
836MX6_IOM_DRAM_SDQS5, 0x00000030,
837MX6_IOM_DRAM_SDQS6, 0x00000030,
838MX6_IOM_DRAM_SDQS7, 0x00000030,
839
840MX6_IOM_GRP_B0DS, 0x00000030,
841MX6_IOM_GRP_B1DS, 0x00000030,
842MX6_IOM_GRP_B2DS, 0x00000030,
843MX6_IOM_GRP_B3DS, 0x00000030,
844MX6_IOM_GRP_B4DS, 0x00000030,
845MX6_IOM_GRP_B5DS, 0x00000030,
846MX6_IOM_GRP_B6DS, 0x00000030,
847MX6_IOM_GRP_B7DS, 0x00000030,
848MX6_IOM_GRP_ADDDS, 0x00000030,
849/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
850MX6_IOM_GRP_CTLDS, 0x00000030,
851
852MX6_IOM_DRAM_DQM0, 0x00020030,
853MX6_IOM_DRAM_DQM1, 0x00020030,
854MX6_IOM_DRAM_DQM2, 0x00020030,
855MX6_IOM_DRAM_DQM3, 0x00020030,
856MX6_IOM_DRAM_DQM4, 0x00020030,
857MX6_IOM_DRAM_DQM5, 0x00020030,
858MX6_IOM_DRAM_DQM6, 0x00020030,
859MX6_IOM_DRAM_DQM7, 0x00020030,
860
861MX6_IOM_DRAM_CAS, 0x00020030,
862MX6_IOM_DRAM_RAS, 0x00020030,
863MX6_IOM_DRAM_SDCLK_0, 0x00020030,
864MX6_IOM_DRAM_SDCLK_1, 0x00020030,
865
866MX6_IOM_DRAM_RESET, 0x00020030,
867MX6_IOM_DRAM_SDCKE0, 0x00003000,
868MX6_IOM_DRAM_SDCKE1, 0x00003000,
869
870MX6_IOM_DRAM_SDODT0, 0x00003030,
871MX6_IOM_DRAM_SDODT1, 0x00003030,
872
873/* (differential input) */
874MX6_IOM_DDRMODE_CTL, 0x00020000,
875/* (differential input) */
876MX6_IOM_GRP_DDRMODE, 0x00020000,
877/* disable ddr pullups */
878MX6_IOM_GRP_DDRPKE, 0x00000000,
879MX6_IOM_DRAM_SDBA2, 0x00000000,
880/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
881MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
882
883/* Read data DQ Byte0-3 delay */
884MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
885MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
886MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
887MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
888MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
889MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
890MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
891MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
892
893/*
894 * MDMISC mirroring interleaved (row/bank/col)
895 */
896/* TODO: check what the RALAT field does */
897MX6_MMDC_P0_MDMISC, 0x00081740,
898
899/*
900 * MDSCR con_req
901 */
902MX6_MMDC_P0_MDSCR, 0x00008000,
903
904
905/* 800mhz_2x64mx16.cfg */
906
907MX6_MMDC_P0_MDPDC, 0x0002002D,
908MX6_MMDC_P0_MDCFG0, 0x2C305503,
909MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
910MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
911MX6_MMDC_P0_MDRWD, 0x000026D2,
912MX6_MMDC_P0_MDOR, 0x00301023,
913MX6_MMDC_P0_MDOTC, 0x00333030,
914MX6_MMDC_P0_MDPDC, 0x0002556D,
915/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
916MX6_MMDC_P0_MDASP, 0x00000017,
917/* DDR3 DATA BUS SIZE: 64BIT */
918MX6_MMDC_P0_MDCTL, 0x821A0000,
919/* DDR3 DATA BUS SIZE: 32BIT */
920/* MX6_MMDC_P0_MDCTL, 0x82190000, */
921
922/* Write commands to DDR */
923/* Load Mode Registers */
924/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
925/* MX6_MMDC_P0_MDSCR, 0x04408032, */
926MX6_MMDC_P0_MDSCR, 0x04008032,
927MX6_MMDC_P0_MDSCR, 0x00008033,
928MX6_MMDC_P0_MDSCR, 0x00048031,
929MX6_MMDC_P0_MDSCR, 0x13208030,
930/* ZQ calibration */
931MX6_MMDC_P0_MDSCR, 0x04008040,
932
933MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
934MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
935MX6_MMDC_P0_MDREF, 0x00005800,
936
937MX6_MMDC_P0_MPODTCTRL, 0x00000000,
938MX6_MMDC_P1_MPODTCTRL, 0x00000000,
939
940MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
941MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
942MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
943MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
944
945MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
946MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
947MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
948MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
949
950MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
951MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
952MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
953MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
954
955MX6_MMDC_P0_MPMUR0, 0x00000800,
956MX6_MMDC_P1_MPMUR0, 0x00000800,
957MX6_MMDC_P0_MDSCR, 0x00000000,
958MX6_MMDC_P0_MAPSR, 0x00011006,
959};
960
961static void ccgr_init(void)
962{
963 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
964
965 writel(0x00C03F3F, &ccm->CCGR0);
966 writel(0x0030FC03, &ccm->CCGR1);
967 writel(0x0FFFFFF3, &ccm->CCGR2);
968 writel(0x3FF0300F, &ccm->CCGR3);
969 writel(0x00FFF300, &ccm->CCGR4);
970 writel(0x0F0000F3, &ccm->CCGR5);
971 writel(0x000003FF, &ccm->CCGR6);
972
973/*
974 * Setup CCM_CCOSR register as follows:
975 *
976 * cko1_en = 1 --> CKO1 enabled
977 * cko1_div = 111 --> divide by 8
978 * cko1_sel = 1011 --> ahb_clk_root
979 *
980 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
981 */
982 writel(0x000000FB, &ccm->ccosr);
983}
984
Max Krummenachereeb16b22016-11-30 19:43:09 +0100985static void ddr_init(int *table, int size)
986{
987 int i;
988
989 for (i = 0; i < size / 2 ; i++)
990 writel(table[2 * i + 1], table[2 * i]);
991}
992
993static void spl_dram_init(void)
994{
995 int minc, maxc;
996
997 switch (get_cpu_temp_grade(&minc, &maxc)) {
998 case TEMP_COMMERCIAL:
999 case TEMP_EXTCOMMERCIAL:
1000 if (is_cpu_type(MXC_CPU_MX6DL)) {
1001 puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1002 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1003 } else {
1004 puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1005 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1006 }
1007 break;
1008 case TEMP_INDUSTRIAL:
1009 case TEMP_AUTOMOTIVE:
1010 default:
1011 if (is_cpu_type(MXC_CPU_MX6DL)) {
Max Krummenacherc1ce7cb2019-02-08 18:42:17 +01001012 puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
Max Krummenachereeb16b22016-11-30 19:43:09 +01001013 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1014 } else {
1015 puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1016 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1017 }
1018 break;
1019 };
1020 udelay(100);
1021}
1022
Gerard Salvatella7fba5092019-02-08 18:42:28 +01001023static iomux_v3_cfg_t const gpio_reset_pad[] = {
1024 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
1025 MUX_MODE_SION
1026#define GPIO_NRESET IMX_GPIO_NR(6, 27)
1027};
1028
1029#define IMX_RESET_CAUSE_POR 0x00011
1030static void nreset_out(void)
1031{
1032 int reset_cause = get_imx_reset_cause();
1033
1034 if (reset_cause != IMX_RESET_CAUSE_POR) {
1035 imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
1036 ARRAY_SIZE(gpio_reset_pad));
1037 gpio_direction_output(GPIO_NRESET, 1);
1038 udelay(100);
1039 gpio_direction_output(GPIO_NRESET, 0);
1040 }
1041}
1042
Max Krummenachereeb16b22016-11-30 19:43:09 +01001043void board_init_f(ulong dummy)
1044{
1045 /* setup AIPS and disable watchdog */
1046 arch_cpu_init();
1047
1048 ccgr_init();
1049 gpr_init();
1050
Marcel Ziswilerc882cfb2019-02-08 18:42:12 +01001051 /* iomux */
Max Krummenachereeb16b22016-11-30 19:43:09 +01001052 board_early_init_f();
1053
1054 /* setup GP timer */
1055 timer_init();
1056
1057 /* UART clocks enabled and gd valid - init serial console */
1058 preloader_console_init();
1059
1060 /* Make sure we use dte mode */
1061 setup_dtemode_uart();
1062
1063 /* DDR initialization */
1064 spl_dram_init();
1065
1066 /* Clear the BSS. */
1067 memset(__bss_start, 0, __bss_end - __bss_start);
1068
Gerard Salvatella7fba5092019-02-08 18:42:28 +01001069 /* Assert nReset_Out */
1070 nreset_out();
1071
Max Krummenachereeb16b22016-11-30 19:43:09 +01001072 /* load/boot image from boot device */
1073 board_init_r(NULL, 0);
1074}
1075
1076void reset_cpu(ulong addr)
1077{
1078}
1079
Marcel Ziswiler3e43a502019-02-08 18:42:10 +01001080#endif /* CONFIG_SPL_BUILD */
Max Krummenachereeb16b22016-11-30 19:43:09 +01001081
1082static struct mxc_serial_platdata mxc_serial_plat = {
1083 .reg = (struct mxc_uart *)UART1_BASE,
1084 .use_dte = true,
1085};
1086
1087U_BOOT_DEVICE(mxc_serial) = {
1088 .name = "serial_mxc",
1089 .platdata = &mxc_serial_plat,
1090};