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git01.mediatek.com / filogic / uboot / 275d851ca526b0e0f97667c8635627f606015a0b / . / board / alliedtelesis / SBx81LIFXCAT / sbx81lifxcat.c
blob: 52b8eba92fc1ab520a3b8a51de142bf21ada30eb [file] [log] [blame]
Chris Packhamc6408d12018-06-25 22:34:57 +1200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2010, 2018
4 * Allied Telesis <www.alliedtelesis.com>
5 */
6
7#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]8#include <init.h>
Chris Packhamc6408d12018-06-25 22:34:57 +1200[diff] [blame]9#include <miiphy.h>
Simon Glass0c364412019-12-28 10:44:48 -0700[diff] [blame]10#include <net.h>
Chris Packhamc6408d12018-06-25 22:34:57 +1200[diff] [blame]11#include <netdev.h>
12#include <led.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]13#include <asm/global_data.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Chris Packhamc6408d12018-06-25 22:34:57 +1200[diff] [blame]15#include <linux/io.h>
16#include <asm/arch/cpu.h>
17#include <asm/arch/soc.h>
18#include <asm/arch/mpp.h>
19#include <asm/arch/gpio.h>
20
21#define SBX81LIFXCAT_OE_LOW (~0)
22#define SBX81LIFXCAT_OE_HIGH (~BIT(11))
23#define SBX81LIFXCAT_OE_VAL_LOW (0)
24#define SBX81LIFXCAT_OE_VAL_HIGH (BIT(11))
25
26DECLARE_GLOBAL_DATA_PTR;
27
28int board_early_init_f(void)
29{
30 /*
31 * default gpio configuration
32 * There are maximum 64 gpios controlled through 2 sets of registers
33 * the below configuration configures mainly initial LED status
34 */
35 mvebu_config_gpio(SBX81LIFXCAT_OE_VAL_LOW,
36 SBX81LIFXCAT_OE_VAL_HIGH,
37 SBX81LIFXCAT_OE_LOW, SBX81LIFXCAT_OE_HIGH);
38
39 /* Multi-Purpose Pins Functionality configuration */
40 static const u32 kwmpp_config[] = {
41 MPP0_SPI_SCn,
42 MPP1_SPI_MOSI,
43 MPP2_SPI_SCK,
44 MPP3_SPI_MISO,
45 MPP4_NF_IO6,
46 MPP5_NF_IO7,
47 MPP6_SYSRST_OUTn,
48 MPP7_GPO,
49 MPP8_TW_SDA,
50 MPP9_TW_SCK,
51 MPP10_UART0_TXD,
52 MPP11_UART0_RXD,
53 MPP12_GPO,
54 MPP13_UART1_TXD,
55 MPP14_UART1_RXD,
56 MPP15_GPIO,
57 MPP16_GPIO,
58 MPP17_GPIO,
59 MPP18_NF_IO0,
60 MPP19_NF_IO1,
61 MPP20_GE1_0,
62 MPP21_GE1_1,
63 MPP22_GE1_2,
64 MPP23_GE1_3,
65 MPP24_GE1_4,
66 MPP25_GE1_5,
67 MPP26_GE1_6,
68 MPP27_GE1_7,
69 MPP28_GE1_8,
70 MPP29_GE1_9,
71 MPP30_GE1_10,
72 MPP31_GE1_11,
73 MPP32_GE1_12,
74 MPP33_GE1_13,
75 MPP34_GPIO,
76 MPP35_GPIO,
77 MPP36_GPIO,
78 MPP37_GPIO,
79 MPP38_GPIO,
80 MPP39_GPIO,
81 MPP40_GPIO,
82 MPP41_GPIO,
83 MPP42_GPIO,
84 MPP43_GPIO,
85 MPP44_GPIO,
86 MPP45_GPIO,
87 MPP46_GPIO,
88 MPP47_GPIO,
89 MPP48_GPIO,
90 MPP49_GPIO,
91 0
92 };
93
94 kirkwood_mpp_conf(kwmpp_config, NULL);
95 return 0;
96}
97
98int board_init(void)
99{
100 /* address of boot parameters */
101 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
102
103 return 0;
104}
105
106#ifdef CONFIG_RESET_PHY_R
107/* automatically defined by kirkwood config.h */
108void reset_phy(void)
109{
110}
111#endif
112
113#ifdef CONFIG_MV88E61XX_SWITCH
114int mv88e61xx_hw_reset(struct phy_device *phydev)
115{
116 phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
117
118 return 0;
119}
120#endif
121
122#ifdef CONFIG_MISC_INIT_R
123int misc_init_r(void)
124{
125 struct udevice *dev;
126 int ret;
127
128 ret = led_get_by_label("status:ledp", &dev);
129 if (!ret)
130 led_set_state(dev, LEDST_ON);
131
132 ret = led_get_by_label("status:ledn", &dev);
133 if (!ret)
134 led_set_state(dev, LEDST_OFF);
135
136 return 0;
137}
138#endif