blob: 09cad743c550fe428db31fe960ac1d105f351017 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada127f5772017-02-14 01:24:25 +09002/*
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada127f5772017-02-14 01:24:25 +09005 */
6
Masahiro Yamada127f5772017-02-14 01:24:25 +09007#include <mmc.h>
8#include <spl.h>
9
Andre Przywara3cb12ef2021-07-12 11:06:49 +010010u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
Masahiro Yamada127f5772017-02-14 01:24:25 +090011{
Masahiro Yamada127f5772017-02-14 01:24:25 +090012 /*
Masahiro Yamadad3c14612017-08-13 09:01:13 +090013 * work around a bug in the Boot ROM of LD4, Pro4, and sLD8:
Masahiro Yamada127f5772017-02-14 01:24:25 +090014 *
15 * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of
16 * Extended CSD register; when switching to the Boot Partition 1, the
17 * Boot ROM should issue the SWITCH command (CMD6) with Set Bits for
18 * the Access Bits, but in fact it uses Write Byte for the Access Bits.
19 * As a result, the BOOT_PARTITION_ENABLE field of the PARTITION_CONFIG
20 * is lost. This bug was fixed for PH1-Pro5 and later SoCs.
21 *
22 * Fixup mmc->part_config here because it is used to determine the
23 * partition which the U-Boot image is read from.
24 */
Masahiro Yamada127f5772017-02-14 01:24:25 +090025 mmc->part_config &= ~EXT_CSD_BOOT_PART_NUM(PART_ACCESS_MASK);
26 mmc->part_config |= EXT_CSD_BOOT_PARTITION_ENABLE;
27
28 return MMCSD_MODE_EMMCBOOT;
29}