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git01.mediatek.com / filogic / uboot / 274f38d1661042e40f53847e75794bf5b6b10469 / . / board / xilinx / xilinx_enet / xemac_i.h
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wdenke537b3b2004-02-23 23:54:43 +0000[diff] [blame]1/******************************************************************************
2*
3* Author: Xilinx, Inc.
4*
5*
6* This program is free software; you can redistribute it and/or modify it
7* under the terms of the GNU General Public License as published by the
8* Free Software Foundation; either version 2 of the License, or (at your
9* option) any later version.
10*
11*
12* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
13* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
14* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
15* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
16* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
17* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
18* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
19* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
20* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
21* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
22* FITNESS FOR A PARTICULAR PURPOSE.
23*
24*
25* Xilinx hardware products are not intended for use in life support
26* appliances, devices, or systems. Use in such applications is
27* expressly prohibited.
28*
29*
30* (c) Copyright 2002-2004 Xilinx Inc.
31* All rights reserved.
32*
33*
34* You should have received a copy of the GNU General Public License along
35* with this program; if not, write to the Free Software Foundation, Inc.,
36* 675 Mass Ave, Cambridge, MA 02139, USA.
37*
38******************************************************************************/
39/*****************************************************************************/
40/**
41*
42* @file xemac_i.h
43*
44* This header file contains internal identifiers, which are those shared
45* between XEmac components. The identifiers in this file are not intended for
46* use external to the driver.
47*
48* <pre>
49* MODIFICATION HISTORY:
50*
51* Ver Who Date Changes
52* ----- ---- -------- -----------------------------------------------
53* 1.00a rpm 07/31/01 First release
54* 1.00b rpm 02/20/02 Repartitioned files and functions
55* 1.00b rpm 04/29/02 Moved register definitions to xemac_l.h
56* 1.00c rpm 12/05/02 New version includes support for simple DMA
57* </pre>
58*
59******************************************************************************/
60
61#ifndef XEMAC_I_H /* prevent circular inclusions */
62#define XEMAC_I_H /* by using protection macros */
63
64/***************************** Include Files *********************************/
65
66#include "xemac.h"
67#include "xemac_l.h"
68
69/************************** Constant Definitions *****************************/
70
71/*
72 * Default buffer descriptor control word masks. The default send BD control
73 * is set for incrementing the source address by one for each byte transferred,
74 * and specify that the destination address (FIFO) is local to the device. The
75 * default receive BD control is set for incrementing the destination address
76 * by one for each byte transferred, and specify that the source address is
77 * local to the device.
78 */
79#define XEM_DFT_SEND_BD_MASK (XDC_DMACR_SOURCE_INCR_MASK | \
80 XDC_DMACR_DEST_LOCAL_MASK)
81#define XEM_DFT_RECV_BD_MASK (XDC_DMACR_DEST_INCR_MASK | \
82 XDC_DMACR_SOURCE_LOCAL_MASK)
83
84/*
85 * Masks for the IPIF Device Interrupt enable and status registers.
86 */
87#define XEM_IPIF_EMAC_MASK 0x00000004UL /* MAC interrupt */
88#define XEM_IPIF_SEND_DMA_MASK 0x00000008UL /* Send DMA interrupt */
89#define XEM_IPIF_RECV_DMA_MASK 0x00000010UL /* Receive DMA interrupt */
90#define XEM_IPIF_RECV_FIFO_MASK 0x00000020UL /* Receive FIFO interrupt */
91#define XEM_IPIF_SEND_FIFO_MASK 0x00000040UL /* Send FIFO interrupt */
92
93/*
94 * Default IPIF Device Interrupt mask when configured for DMA
95 */
96#define XEM_IPIF_DMA_DFT_MASK (XEM_IPIF_SEND_DMA_MASK | \
97 XEM_IPIF_RECV_DMA_MASK | \
98 XEM_IPIF_EMAC_MASK | \
99 XEM_IPIF_SEND_FIFO_MASK | \
100 XEM_IPIF_RECV_FIFO_MASK)
101
102/*
103 * Default IPIF Device Interrupt mask when configured without DMA
104 */
105#define XEM_IPIF_FIFO_DFT_MASK (XEM_IPIF_EMAC_MASK | \
106 XEM_IPIF_SEND_FIFO_MASK | \
107 XEM_IPIF_RECV_FIFO_MASK)
108
109#define XEM_IPIF_DMA_DEV_INTR_COUNT 7 /* Number of interrupt sources */
110#define XEM_IPIF_FIFO_DEV_INTR_COUNT 5 /* Number of interrupt sources */
111#define XEM_IPIF_DEVICE_INTR_COUNT 7 /* Number of interrupt sources */
112#define XEM_IPIF_IP_INTR_COUNT 22 /* Number of MAC interrupts */
113
114/* a mask for all transmit interrupts, used in polled mode */
115#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK | \
116 XEM_EIR_XMIT_ERROR_MASK | \
117 XEM_EIR_XMIT_SFIFO_EMPTY_MASK | \
118 XEM_EIR_XMIT_LFIFO_FULL_MASK)
119
120/* a mask for all receive interrupts, used in polled mode */
121#define XEM_EIR_RECV_ALL_MASK (XEM_EIR_RECV_DONE_MASK | \
122 XEM_EIR_RECV_ERROR_MASK | \
123 XEM_EIR_RECV_LFIFO_EMPTY_MASK | \
124 XEM_EIR_RECV_LFIFO_OVER_MASK | \
125 XEM_EIR_RECV_LFIFO_UNDER_MASK | \
126 XEM_EIR_RECV_DFIFO_OVER_MASK | \
127 XEM_EIR_RECV_MISSED_FRAME_MASK | \
128 XEM_EIR_RECV_COLLISION_MASK | \
129 XEM_EIR_RECV_FCS_ERROR_MASK | \
130 XEM_EIR_RECV_LEN_ERROR_MASK | \
131 XEM_EIR_RECV_SHORT_ERROR_MASK | \
132 XEM_EIR_RECV_LONG_ERROR_MASK | \
133 XEM_EIR_RECV_ALIGN_ERROR_MASK)
134
135/* a default interrupt mask for scatter-gather DMA operation */
136#define XEM_EIR_DFT_SG_MASK (XEM_EIR_RECV_ERROR_MASK | \
137 XEM_EIR_RECV_LFIFO_OVER_MASK | \
138 XEM_EIR_RECV_LFIFO_UNDER_MASK | \
139 XEM_EIR_XMIT_SFIFO_OVER_MASK | \
140 XEM_EIR_XMIT_SFIFO_UNDER_MASK | \
141 XEM_EIR_XMIT_LFIFO_OVER_MASK | \
142 XEM_EIR_XMIT_LFIFO_UNDER_MASK | \
143 XEM_EIR_RECV_DFIFO_OVER_MASK | \
144 XEM_EIR_RECV_MISSED_FRAME_MASK | \
145 XEM_EIR_RECV_COLLISION_MASK | \
146 XEM_EIR_RECV_FCS_ERROR_MASK | \
147 XEM_EIR_RECV_LEN_ERROR_MASK | \
148 XEM_EIR_RECV_SHORT_ERROR_MASK | \
149 XEM_EIR_RECV_LONG_ERROR_MASK | \
150 XEM_EIR_RECV_ALIGN_ERROR_MASK)
151
152/* a default interrupt mask for non-DMA operation (direct FIFOs) */
153#define XEM_EIR_DFT_FIFO_MASK (XEM_EIR_XMIT_DONE_MASK | \
154 XEM_EIR_RECV_DONE_MASK | \
155 XEM_EIR_DFT_SG_MASK)
156
157/*
158 * Mask for the DMA interrupt enable and status registers when configured
159 * for scatter-gather DMA.
160 */
161#define XEM_DMA_SG_INTR_MASK (XDC_IXR_DMA_ERROR_MASK | \
162 XDC_IXR_PKT_THRESHOLD_MASK | \
163 XDC_IXR_PKT_WAIT_BOUND_MASK | \
164 XDC_IXR_SG_END_MASK)
165
166/**************************** Type Definitions *******************************/
167
168/***************** Macros (Inline Functions) Definitions *********************/
169
170/*****************************************************************************/
171/*
172*
173* Clears a structure of given size, in bytes, by setting each byte to 0.
174*
175* @param StructPtr is a pointer to the structure to be cleared.
176* @param NumBytes is the number of bytes in the structure.
177*
178* @return
179*
180* None.
181*
182* @note
183*
184* Signature: void XEmac_mClearStruct(u8 *StructPtr, unsigned int NumBytes)
185*
186******************************************************************************/
187#define XEmac_mClearStruct(StructPtr, NumBytes) \
188{ \
189 int i; \
190 u8 *BytePtr = (u8 *)(StructPtr); \
191 for (i=0; i < (unsigned int)(NumBytes); i++) \
192 { \
193 *BytePtr++ = 0; \
194 } \
195}
196
197/************************** Variable Definitions *****************************/
198
199extern XEmac_Config XEmac_ConfigTable[];
200
201/************************** Function Prototypes ******************************/
202
203void XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus);
204void XEmac_CheckFifoRecvError(XEmac * InstancePtr);
205void XEmac_CheckFifoSendError(XEmac * InstancePtr);
206
207#endif /* end of protection macro */