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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Heiko Schocher499c4982013-08-19 16:39:01 +02002/*
3 * Board functions for TI AM335X based rut board
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
7 * Based on:
8 * u-boot:/board/ti/am335x/board.c
9 *
10 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
Heiko Schocher499c4982013-08-19 16:39:01 +020011 */
12
13#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060014#include <env.h>
Heiko Schocher499c4982013-08-19 16:39:01 +020015#include <errno.h>
Simon Glassa7b51302019-11-14 12:57:46 -070016#include <init.h>
Simon Glass9bc15642020-02-03 07:36:16 -070017#include <malloc.h>
Simon Glass274e0b02020-05-10 11:39:56 -060018#include <net.h>
Heiko Schocher499c4982013-08-19 16:39:01 +020019#include <spi.h>
20#include <spl.h>
21#include <asm/arch/cpu.h>
22#include <asm/arch/hardware.h>
23#include <asm/arch/omap.h>
24#include <asm/arch/ddr_defs.h>
25#include <asm/arch/clock.h>
26#include <asm/arch/gpio.h>
27#include <asm/arch/mmc_host_def.h>
28#include <asm/arch/sys_proto.h>
29#include <asm/io.h>
30#include <asm/emif.h>
31#include <asm/gpio.h>
32#include <i2c.h>
33#include <miiphy.h>
34#include <cpsw.h>
35#include <video.h>
36#include <watchdog.h>
37#include "board.h"
38#include "../common/factoryset.h"
39#include "../../../drivers/video/da8xx-fb.h"
40
Heiko Schocher499c4982013-08-19 16:39:01 +020041/*
42 * Read header information from EEPROM into global structure.
43 */
44static int read_eeprom(void)
45{
46 return 0;
47}
48
49#ifdef CONFIG_SPL_BUILD
50static void board_init_ddr(void)
51{
52struct emif_regs rut_ddr3_emif_reg_data = {
53 .sdram_config = 0x61C04AB2,
54 .sdram_tim1 = 0x0888A39B,
55 .sdram_tim2 = 0x26337FDA,
56 .sdram_tim3 = 0x501F830F,
57 .emif_ddr_phy_ctlr_1 = 0x6,
58 .zq_config = 0x50074BE4,
59 .ref_ctrl = 0x93B,
60};
61
62struct ddr_data rut_ddr3_data = {
63 .datardsratio0 = 0x3b,
64 .datawdsratio0 = 0x85,
65 .datafwsratio0 = 0x100,
66 .datawrsratio0 = 0xc1,
Heiko Schocher499c4982013-08-19 16:39:01 +020067};
68
69struct cmd_control rut_ddr3_cmd_ctrl_data = {
70 .cmd0csratio = 0x40,
Heiko Schocher499c4982013-08-19 16:39:01 +020071 .cmd0iclkout = 1,
72 .cmd1csratio = 0x40,
Heiko Schocher499c4982013-08-19 16:39:01 +020073 .cmd1iclkout = 1,
74 .cmd2csratio = 0x40,
Heiko Schocher499c4982013-08-19 16:39:01 +020075 .cmd2iclkout = 1,
76};
77
Lokesh Vutla303b2672013-12-10 15:02:21 +053078const struct ctrl_ioregs ioregs = {
79 .cm0ioctl = RUT_IOCTRL_VAL,
80 .cm1ioctl = RUT_IOCTRL_VAL,
81 .cm2ioctl = RUT_IOCTRL_VAL,
82 .dt0ioctl = RUT_IOCTRL_VAL,
83 .dt1ioctl = RUT_IOCTRL_VAL,
84};
85
86 config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
Heiko Schocher499c4982013-08-19 16:39:01 +020087 &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
88}
89
Samuel Egli8069bfe2013-11-04 14:05:03 +010090static int request_and_pulse_reset(int gpio, const char *name)
91{
92 int ret;
93 const int delay_us = 2000; /* 2ms */
94
95 ret = gpio_request(gpio, name);
96 if (ret < 0) {
97 printf("%s: Unable to request %s\n", __func__, name);
98 goto err;
99 }
100
101 ret = gpio_direction_output(gpio, 0);
102 if (ret < 0) {
103 printf("%s: Unable to set %s as output\n", __func__, name);
104 goto err_free_gpio;
105 }
106
107 udelay(delay_us);
108
109 gpio_set_value(gpio, 1);
110
111 return 0;
112
113err_free_gpio:
114 gpio_free(gpio);
115err:
116 return ret;
117}
118
119#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
120#define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
121#define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
122#define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
123
124#define REQUEST_AND_PULSE_RESET(N) \
125 request_and_pulse_reset(N, #N);
126
Heiko Schocher499c4982013-08-19 16:39:01 +0200127static void spl_siemens_board_init(void)
128{
Samuel Egli8069bfe2013-11-04 14:05:03 +0100129 REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
130 REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
131 REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
Heiko Schocher499c4982013-08-19 16:39:01 +0200132}
133#endif /* if def CONFIG_SPL_BUILD */
134
135#if defined(CONFIG_DRIVER_TI_CPSW)
136static void cpsw_control(int enabled)
137{
138 /* VTP can be added here */
139
140 return;
141}
142
143static struct cpsw_slave_data cpsw_slaves[] = {
144 {
145 .slave_reg_ofs = 0x208,
146 .sliver_reg_ofs = 0xd80,
Mugunthan V N4944f372014-02-18 07:31:52 -0500147 .phy_addr = 1,
Heiko Schocher499c4982013-08-19 16:39:01 +0200148 .phy_if = PHY_INTERFACE_MODE_RMII,
149 },
150 {
151 .slave_reg_ofs = 0x308,
152 .sliver_reg_ofs = 0xdc0,
Mugunthan V N4944f372014-02-18 07:31:52 -0500153 .phy_addr = 0,
Heiko Schocher499c4982013-08-19 16:39:01 +0200154 .phy_if = PHY_INTERFACE_MODE_RMII,
155 },
156};
157
158static struct cpsw_platform_data cpsw_data = {
159 .mdio_base = CPSW_MDIO_BASE,
160 .cpsw_base = CPSW_BASE,
161 .mdio_div = 0xff,
162 .channels = 8,
163 .cpdma_reg_ofs = 0x800,
164 .slaves = 1,
165 .slave_data = cpsw_slaves,
166 .ale_reg_ofs = 0xd00,
167 .ale_entries = 1024,
168 .host_port_reg_ofs = 0x108,
169 .hw_stats_reg_ofs = 0x900,
170 .bd_ram_ofs = 0x2000,
171 .mac_control = (1 << 5),
172 .control = cpsw_control,
173 .host_port_num = 0,
174 .version = CPSW_CTRL_VERSION_2,
175};
176
177#if defined(CONFIG_DRIVER_TI_CPSW) || \
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +0200178 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
Heiko Schocher499c4982013-08-19 16:39:01 +0200179int board_eth_init(bd_t *bis)
180{
181 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
182 int n = 0;
183 int rv;
184
185#ifndef CONFIG_SPL_BUILD
Simon Glass6a38e412017-08-03 12:22:09 -0600186 factoryset_env_set();
Heiko Schocher499c4982013-08-19 16:39:01 +0200187#endif
188
189 /* Set rgmii mode and enable rmii clock to be sourced from chip */
190 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
191
192 rv = cpsw_register(&cpsw_data);
193 if (rv < 0)
194 printf("Error %d registering CPSW switch\n", rv);
195 else
196 n += rv;
197 return n;
198}
199#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
200#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
201
202#if defined(CONFIG_HW_WATCHDOG)
203static bool hw_watchdog_init_done;
204static int hw_watchdog_trigger_level;
205
206void hw_watchdog_reset(void)
207{
208 if (!hw_watchdog_init_done)
209 return;
210
211 hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
212 gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
213}
214
215void hw_watchdog_init(void)
216{
217 gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
218 gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
219
220 hw_watchdog_reset();
221
222 hw_watchdog_init_done = 1;
223}
224#endif /* defined(CONFIG_HW_WATCHDOG) */
225
226#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
227static struct da8xx_panel lcd_panels[] = {
228 /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
229 [0] = {
230 .name = "KWH043MC17-F01",
231 .width = 480,
232 .height = 800,
233 .hfp = 50, /* no spec, "don't care" values */
234 .hbp = 50,
235 .hsw = 50,
236 .vfp = 50,
237 .vbp = 50,
238 .vsw = 50,
239 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
240 .invert_pxl_clk = 1,
241 },
242 /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
243 [1] = {
244 .name = "KWH043ST20-F01",
245 .width = 480,
246 .height = 800,
247 .hfp = 50, /* no spec, "don't care" values */
248 .hbp = 50,
249 .hsw = 50,
250 .vfp = 50,
251 .vbp = 50,
252 .vsw = 50,
253 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
254 .invert_pxl_clk = 1,
255 },
256 /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
257 [2] = {
258 .name = "MI0430VT-1",
259 .width = 480,
260 .height = 800,
261 .hfp = 50, /* no spec, "don't care" values */
262 .hbp = 50,
263 .hsw = 50,
264 .vfp = 50,
265 .vbp = 50,
266 .vsw = 50,
267 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
268 .invert_pxl_clk = 1,
269 },
270};
271
272static const struct display_panel disp_panels[] = {
273 [0] = {
274 WVGA,
275 16, /* RGB 888 */
276 16,
277 COLOR_ACTIVE,
278 },
279 [1] = {
280 WVGA,
281 16, /* RGB 888 */
282 16,
283 COLOR_ACTIVE,
284 },
285 [2] = {
286 WVGA,
287 24, /* RGB 888 */
288 16,
289 COLOR_ACTIVE,
290 },
291};
292
293static const struct lcd_ctrl_config lcd_cfgs[] = {
294 [0] = {
295 &disp_panels[0],
296 .ac_bias = 255,
297 .ac_bias_intrpt = 0,
298 .dma_burst_sz = 16,
299 .bpp = 16,
300 .fdd = 0x80,
301 .tft_alt_mode = 0,
302 .stn_565_mode = 0,
303 .mono_8bit_mode = 0,
304 .invert_line_clock = 1,
305 .invert_frm_clock = 1,
306 .sync_edge = 0,
307 .sync_ctrl = 1,
308 .raster_order = 0,
309 },
310 [1] = {
311 &disp_panels[1],
312 .ac_bias = 255,
313 .ac_bias_intrpt = 0,
314 .dma_burst_sz = 16,
315 .bpp = 16,
316 .fdd = 0x80,
317 .tft_alt_mode = 0,
318 .stn_565_mode = 0,
319 .mono_8bit_mode = 0,
320 .invert_line_clock = 1,
321 .invert_frm_clock = 1,
322 .sync_edge = 0,
323 .sync_ctrl = 1,
324 .raster_order = 0,
325 },
326 [2] = {
327 &disp_panels[2],
328 .ac_bias = 255,
329 .ac_bias_intrpt = 0,
330 .dma_burst_sz = 16,
331 .bpp = 24,
332 .fdd = 0x80,
333 .tft_alt_mode = 0,
334 .stn_565_mode = 0,
335 .mono_8bit_mode = 0,
336 .invert_line_clock = 1,
337 .invert_frm_clock = 1,
338 .sync_edge = 0,
339 .sync_ctrl = 1,
340 .raster_order = 0,
341 },
342
343};
344
345/* no console on this board */
346int board_cfb_skip(void)
347{
348 return 1;
349}
350
351#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
352#define PLL_GET_N(v) (v & 0x7f)
353
354static struct dpll_regs dpll_lcd_regs = {
355 .cm_clkmode_dpll = CM_WKUP + 0x98,
356 .cm_idlest_dpll = CM_WKUP + 0x48,
357 .cm_clksel_dpll = CM_WKUP + 0x54,
358};
359
360static int get_clk(struct dpll_regs *dpll_regs)
361{
362 unsigned int val;
363 unsigned int m, n;
364 int f = 0;
365
366 val = readl(dpll_regs->cm_clksel_dpll);
367 m = PLL_GET_M(val);
368 n = PLL_GET_N(val);
369 f = (m * V_OSCK) / n;
370
371 return f;
372};
373
Heiko Schocher499c4982013-08-19 16:39:01 +0200374int clk_get(int clk)
375{
376 return get_clk(&dpll_lcd_regs);
377};
378
379static int conf_disp_pll(int m, int n)
380{
381 struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
Heiko Schocher499c4982013-08-19 16:39:01 +0200382 struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
383#if defined(DISPL_PLL_SPREAD_SPECTRUM)
384 struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
385#endif
386
387 u32 *const clk_domains[] = {
388 &cmper->lcdclkctrl,
389 0
390 };
391 u32 *const clk_modules_explicit_en[] = {
392 &cmper->lcdclkctrl,
393 &cmper->lcdcclkstctrl,
394 &cmper->spi1clkctrl,
395 0
396 };
397 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
Heiko Schocher499c4982013-08-19 16:39:01 +0200398
399 do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
400
401#if defined(DISPL_PLL_SPREAD_SPECTRUM)
402 writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
403 writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
Yegor Yefremovcacea6c2014-04-19 22:12:18 +0200404 writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
Heiko Schocher499c4982013-08-19 16:39:01 +0200405 &cmwkup->clkmoddplldisp); /* 0x98 */
406#endif
407 return 0;
408}
409
410static int set_gpio(int gpio, int state)
411{
412 gpio_request(gpio, "temp");
413 gpio_direction_output(gpio, state);
414 gpio_set_value(gpio, state);
415 gpio_free(gpio);
416 return 0;
417}
418
419static int enable_lcd(void)
420{
421 unsigned char buf[1];
422
Samuel Egli8069bfe2013-11-04 14:05:03 +0100423 set_gpio(BOARD_LCD_RESET, 0);
424 mdelay(1);
Heiko Schocher499c4982013-08-19 16:39:01 +0200425 set_gpio(BOARD_LCD_RESET, 1);
Samuel Egli8069bfe2013-11-04 14:05:03 +0100426 mdelay(1);
Heiko Schocher499c4982013-08-19 16:39:01 +0200427
428 /* spi lcd init */
Samuel Egli8069bfe2013-11-04 14:05:03 +0100429 kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
Heiko Schocher499c4982013-08-19 16:39:01 +0200430
431 /* backlight on */
432 buf[0] = 0xf;
433 i2c_write(0x24, 0x7, 1, buf, 1);
434 buf[0] = 0x3f;
435 i2c_write(0x24, 0x8, 1, buf, 1);
436 return 0;
437}
438
439int arch_early_init_r(void)
440{
441 enable_lcd();
442 return 0;
443}
444
445static int board_video_init(void)
446{
447 int i;
448 int anzdisp = ARRAY_SIZE(lcd_panels);
449 int display = 1;
450
451 for (i = 0; i < anzdisp; i++) {
452 if (strncmp((const char *)factory_dat.disp_name,
453 lcd_panels[i].name,
454 strlen((const char *)factory_dat.disp_name)) == 0) {
455 printf("DISPLAY: %s\n", factory_dat.disp_name);
456 break;
457 }
458 }
459 if (i == anzdisp) {
460 i = 1;
461 printf("%s: %s not found, using default %s\n", __func__,
462 factory_dat.disp_name, lcd_panels[i].name);
463 }
Samuel Egli8069bfe2013-11-04 14:05:03 +0100464 conf_disp_pll(24, 1);
Heiko Schocher499c4982013-08-19 16:39:01 +0200465 da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
466 lcd_cfgs[display].bpp);
467
468 return 0;
469}
Heiko Schocher499c4982013-08-19 16:39:01 +0200470#endif /* ifdef CONFIG_VIDEO */
Heiko Schocherfaf2dc62014-11-18 11:51:06 +0100471
472#ifdef CONFIG_BOARD_LATE_INIT
473int board_late_init(void)
474{
475 int ret;
476 char tmp[2 * MAX_STRING_LENGTH + 2];
477
478 omap_nand_switch_ecc(1, 8);
479
480 if (factory_dat.asn[0] != 0)
481 sprintf(tmp, "%s_%s", factory_dat.asn,
482 factory_dat.comp_version);
483 else
Ben Whitten34fd6c92015-12-30 13:05:58 +0000484 strcpy(tmp, "QMX7.E38_4.0");
Heiko Schocherfaf2dc62014-11-18 11:51:06 +0100485
Simon Glass6a38e412017-08-03 12:22:09 -0600486 ret = env_set("boardid", tmp);
Heiko Schocherfaf2dc62014-11-18 11:51:06 +0100487 if (ret)
488 printf("error setting board id\n");
489
490 return 0;
491}
492#endif
493
Heiko Schocher499c4982013-08-19 16:39:01 +0200494#include "../common/board.c"