blob: 0a762bc553629b4cacc7e154122c8e2b110b0084 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +09002/*
3 * Copyright (C) 2012 Renesas Solutions Corp.
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +09004 */
5
6#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -06007#include <env.h>
Simon Glass8e201882020-05-10 11:39:54 -06008#include <flash.h>
Simon Glassa7b51302019-11-14 12:57:46 -07009#include <init.h>
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090010#include <malloc.h>
Simon Glass274e0b02020-05-10 11:39:56 -060011#include <net.h>
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090012#include <asm/processor.h>
13#include <asm/io.h>
14#include <asm/mmc.h>
Simon Glassd34b4562014-10-13 23:42:04 -060015#include <spi.h>
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090016#include <spi_flash.h>
17
18int checkboard(void)
19{
20 puts("BOARD: SH7753 EVB\n");
21
22 return 0;
23}
24
25static void init_gpio(void)
26{
27 struct gpio_regs *gpio = GPIO_BASE;
28 struct sermux_regs *sermux = SERMUX_BASE;
29
30 /* GPIO */
31 writew(0x0000, &gpio->pacr); /* GETHER */
32 writew(0x0001, &gpio->pbcr); /* INTC */
33 writew(0x0000, &gpio->pccr); /* PWMU, INTC */
34 writew(0x0000, &gpio->pdcr); /* SPI0 */
35 writew(0xeaff, &gpio->pecr); /* GPIO */
36 writew(0x0000, &gpio->pfcr); /* WDT */
37 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
38 writew(0x0000, &gpio->phcr); /* SPI1 */
39 writew(0x0000, &gpio->picr); /* SDHI */
40 writew(0x0000, &gpio->pjcr); /* SCIF4 */
41 writew(0x0003, &gpio->pkcr); /* SerMux */
42 writew(0x0000, &gpio->plcr); /* SerMux */
43 writew(0x0000, &gpio->pmcr); /* RIIC */
44 writew(0x0000, &gpio->pncr); /* USB, SGPIO */
45 writew(0x0000, &gpio->pocr); /* SGPIO */
46 writew(0xd555, &gpio->pqcr); /* GPIO */
47 writew(0x0000, &gpio->prcr); /* RIIC */
48 writew(0x0000, &gpio->pscr); /* RIIC */
49 writew(0x0000, &gpio->ptcr); /* STATUS */
50 writeb(0x00, &gpio->pudr);
51 writew(0x5555, &gpio->pucr); /* Debug LED */
52 writew(0x0000, &gpio->pvcr); /* RSPI */
53 writew(0x0000, &gpio->pwcr); /* EVC */
54 writew(0x0000, &gpio->pxcr); /* LBSC */
55 writew(0x0000, &gpio->pycr); /* LBSC */
56 writew(0x0000, &gpio->pzcr); /* eMMC */
57 writew(0xfe00, &gpio->psel0);
58 writew(0x0000, &gpio->psel1);
59 writew(0x3000, &gpio->psel2);
60 writew(0xff00, &gpio->psel3);
61 writew(0x771f, &gpio->psel4);
62 writew(0x0ffc, &gpio->psel5);
63 writew(0x00ff, &gpio->psel6);
64 writew(0xfc00, &gpio->psel7);
65
66 writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
67}
68
69static void init_usb_phy(void)
70{
71 struct usb_common_regs *common0 = USB0_COMMON_BASE;
72 struct usb_common_regs *common1 = USB1_COMMON_BASE;
73 struct usb0_phy_regs *phy = USB0_PHY_BASE;
74 struct usb1_port_regs *port = USB1_PORT_BASE;
75 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
76
77 writew(0x0100, &phy->reset); /* set reset */
78 /* port0 = USB0, port1 = USB1 */
79 writew(0x0002, &phy->portsel);
80 writel(0x0001, &port->port1sel); /* port1 = Host */
81 writew(0x0111, &phy->reset); /* clear reset */
82
83 writew(0x4000, &common0->suspmode);
84 writew(0x4000, &common1->suspmode);
85
86#if defined(__LITTLE_ENDIAN)
87 writel(0x00000000, &align->ehcidatac);
88 writel(0x00000000, &align->ohcidatac);
89#endif
90}
91
92static void init_gether_mdio(void)
93{
94 struct gpio_regs *gpio = GPIO_BASE;
95
96 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
97 writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
98}
99
100static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
101{
102 struct ether_mac_regs *ether;
103 unsigned char mac[6];
104 unsigned long val;
105
Joe Hershberger8e7545e2019-09-13 19:21:16 -0500106 string_to_enetaddr(mac_string, mac);
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900107
108 if (!channel)
109 ether = GETHER0_MAC_BASE;
110 else
111 ether = GETHER1_MAC_BASE;
112
113 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
114 writel(val, &ether->mahr);
115 val = (mac[4] << 8) | mac[5];
116 writel(val, &ether->malr);
117}
118
Bin Meng148c3692016-01-24 21:45:46 -0800119#if defined(CONFIG_SH_32BIT)
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900120/*****************************************************************
121 * This PMB must be set on this timing. The lowlevel_init is run on
122 * Area 0(phys 0x00000000), so we have to map it.
123 *
124 * The new PMB table is following:
125 * ent virt phys v sz c wt
126 * 0 0xa0000000 0x40000000 1 128M 0 1
127 * 1 0xa8000000 0x48000000 1 128M 0 1
128 * 2 0xb0000000 0x50000000 1 128M 0 1
129 * 3 0xb8000000 0x58000000 1 128M 0 1
130 * 4 0x80000000 0x40000000 1 128M 1 1
131 * 5 0x88000000 0x48000000 1 128M 1 1
132 * 6 0x90000000 0x50000000 1 128M 1 1
133 * 7 0x98000000 0x58000000 1 128M 1 1
134 */
135static void set_pmb_on_board_init(void)
136{
137 struct mmu_regs *mmu = MMU_BASE;
138
139 /* clear ITLB */
140 writel(0x00000004, &mmu->mmucr);
141
142 /* delete PMB for SPIBOOT */
143 writel(0, PMB_ADDR_BASE(0));
144 writel(0, PMB_DATA_BASE(0));
145
146 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
147 /* ppn ub v s1 s0 c wt */
148 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
149 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
150 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
151 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
152 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
153 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
154 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
155 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
156 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
157 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
158 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
159 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
160}
Bin Meng148c3692016-01-24 21:45:46 -0800161#endif
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900162
163int board_init(void)
164{
165 struct gether_control_regs *gether = GETHER_CONTROL_BASE;
166
167 init_gpio();
Bin Meng148c3692016-01-24 21:45:46 -0800168#if defined(CONFIG_SH_32BIT)
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900169 set_pmb_on_board_init();
Bin Meng148c3692016-01-24 21:45:46 -0800170#endif
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900171
172 /* Sets TXnDLY to B'010 */
173 writel(0x00000202, &gether->gbecont);
174
175 init_usb_phy();
176 init_gether_mdio();
177
178 return 0;
179}
180
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900181int board_mmc_init(bd_t *bis)
182{
183 struct gpio_regs *gpio = GPIO_BASE;
184
185 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
186 writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
187 udelay(1);
188 writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
189 udelay(200);
190
191 return mmcif_mmc_init();
192}
193
194static int get_sh_eth_mac_raw(unsigned char *buf, int size)
195{
Tom Rinicabddb02019-05-29 17:01:36 -0400196#ifdef CONFIG_DEPRECATED
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900197 struct spi_flash *spi;
198 int ret;
199
200 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
201 if (spi == NULL) {
202 printf("%s: spi_flash probe failed.\n", __func__);
203 return 1;
204 }
205
206 ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
207 if (ret) {
208 printf("%s: spi_flash read failed.\n", __func__);
209 spi_flash_free(spi);
210 return 1;
211 }
212 spi_flash_free(spi);
Tom Rinicabddb02019-05-29 17:01:36 -0400213#endif
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900214
215 return 0;
216}
217
218static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
219{
220 memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
221 SH7753EVB_ETHERNET_MAC_SIZE);
222 mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
223
224 return 0;
225}
226
227static void init_ethernet_mac(void)
228{
229 char mac_string[64];
230 char env_string[64];
231 int i;
232 unsigned char *buf;
233
234 buf = malloc(256);
235 if (!buf) {
236 printf("%s: malloc failed.\n", __func__);
237 return;
238 }
239 get_sh_eth_mac_raw(buf, 256);
240
241 /* Gigabit Ethernet */
242 for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
243 get_sh_eth_mac(i, mac_string, buf);
244 if (i == 0)
Simon Glass6a38e412017-08-03 12:22:09 -0600245 env_set("ethaddr", mac_string);
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900246 else {
247 sprintf(env_string, "eth%daddr", i);
Simon Glass6a38e412017-08-03 12:22:09 -0600248 env_set(env_string, mac_string);
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900249 }
250 set_mac_to_sh_giga_eth_register(i, mac_string);
251 }
252
253 free(buf);
254}
255
256int board_late_init(void)
257{
258 init_ethernet_mac();
259
260 return 0;
261}
262
Tom Rinicabddb02019-05-29 17:01:36 -0400263#ifdef CONFIG_DEPRECATED
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900264int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
265{
266 int i, ret;
267 char mac_string[256];
268 struct spi_flash *spi;
269 unsigned char *buf;
270
271 if (argc != 3) {
272 buf = malloc(256);
273 if (!buf) {
274 printf("%s: malloc failed.\n", __func__);
275 return 1;
276 }
277
278 get_sh_eth_mac_raw(buf, 256);
279
280 /* print current MAC address */
281 for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
282 get_sh_eth_mac(i, mac_string, buf);
283 printf("GETHERC ch%d = %s\n", i, mac_string);
284 }
285 free(buf);
286 return 0;
287 }
288
289 /* new setting */
290 memset(mac_string, 0xff, sizeof(mac_string));
291 sprintf(mac_string, "%s\t%s",
292 argv[1], argv[2]);
293
294 /* write MAC data to SPI rom */
295 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
296 if (!spi) {
297 printf("%s: spi_flash probe failed.\n", __func__);
298 return 1;
299 }
300
301 ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
302 SH7753EVB_SPI_SECTOR_SIZE);
303 if (ret) {
304 printf("%s: spi_flash erase failed.\n", __func__);
305 return 1;
306 }
307
308 ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
309 sizeof(mac_string), mac_string);
310 if (ret) {
311 printf("%s: spi_flash write failed.\n", __func__);
312 spi_flash_free(spi);
313 return 1;
314 }
315 spi_flash_free(spi);
316
317 puts("The writing of the MAC address to SPI ROM was completed.\n");
318
319 return 0;
320}
321
322U_BOOT_CMD(
323 write_mac, 3, 1, do_write_mac,
324 "write MAC address for GETHERC",
325 "[GETHERC ch0] [GETHERC ch1]\n"
326);
Tom Rinicabddb02019-05-29 17:01:36 -0400327#endif