blob: 3f7c35b5c951cf26e0da8ff90fad5861c1696690 [file] [log] [blame]
Vabhav Sharma51641912019-06-06 12:35:28 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5#include <common.h>
Simon Glass274e0b02020-05-10 11:39:56 -06006#include <net.h>
Vabhav Sharma51641912019-06-06 12:35:28 +00007#include <asm/io.h>
8#include <netdev.h>
9#include <fm_eth.h>
10#include <fsl_dtsec.h>
11#include <fsl_mdio.h>
12#include <malloc.h>
13
14#include "../common/fman.h"
15
16int board_eth_init(bd_t *bis)
17{
18#ifdef CONFIG_FMAN_ENET
19 struct memac_mdio_info dtsec_mdio_info;
20 struct mii_dev *dev;
21 u32 srds_s1;
22 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
23
24 srds_s1 = in_be32(&gur->rcwsr[4]) &
25 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
26 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
27
28 dtsec_mdio_info.regs =
29 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
30
31 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
32
33 /* Register the 1G MDIO bus */
34 fm_memac_mdio_init(bis, &dtsec_mdio_info);
35
36 /* QSGMII on lane B, MAC 6/5/10/1 */
37 fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
38 fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
39 fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
40 fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
41
42 switch (srds_s1) {
43 case 0x3040:
44 break;
45 default:
46 printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
47 srds_s1);
48 break;
49 }
50
51 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
52 fm_info_set_mdio(FM1_DTSEC6, dev);
53 fm_info_set_mdio(FM1_DTSEC5, dev);
54 fm_info_set_mdio(FM1_DTSEC10, dev);
55 fm_info_set_mdio(FM1_DTSEC1, dev);
56
Pramod Kumar1e0be152019-12-20 11:19:55 +000057 fm_disable_port(FM1_DTSEC9);
58
Vabhav Sharma51641912019-06-06 12:35:28 +000059 cpu_eth_init(bis);
60#endif
61
62 return pci_eth_init(bis);
63}
64
65#ifdef CONFIG_FMAN_ENET
66int fdt_update_ethernet_dt(void *blob)
67{
68 u32 srds_s1;
69 int i, prop;
70 int offset, nodeoff;
71 const char *path;
72 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
73
74 srds_s1 = in_be32(&gur->rcwsr[4]) &
75 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
76 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
77
78 /* Cycle through all aliases */
79 for (prop = 0; ; prop++) {
80 const char *name;
81
82 /* FDT might have been edited, recompute the offset */
83 offset = fdt_first_property_offset(blob,
84 fdt_path_offset(blob,
85 "/aliases")
86 );
87 /* Select property number 'prop' */
88 for (i = 0; i < prop; i++)
89 offset = fdt_next_property_offset(blob, offset);
90
91 if (offset < 0)
92 break;
93
94 path = fdt_getprop_by_offset(blob, offset, &name, NULL);
95 nodeoff = fdt_path_offset(blob, path);
96
97 switch (srds_s1) {
98 case 0x3040:
99 if (!strcmp(name, "ethernet1"))
100 fdt_status_disabled(blob, nodeoff);
101 if (!strcmp(name, "ethernet2"))
102 fdt_status_disabled(blob, nodeoff);
103 if (!strcmp(name, "ethernet3"))
104 fdt_status_disabled(blob, nodeoff);
105 if (!strcmp(name, "ethernet6"))
106 fdt_status_disabled(blob, nodeoff);
107 break;
108 default:
109 printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n",
110 __func__, srds_s1);
111 break;
112 }
113 }
114
115 return 0;
116}
117#endif