Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2000-2002 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * m8xx.c |
| 9 | * |
| 10 | * CPU specific code |
| 11 | * |
| 12 | * written or collected and sometimes rewritten by |
| 13 | * Magnus Damm <damm@bitsmart.com> |
| 14 | * |
| 15 | * minor modifications by |
| 16 | * Wolfgang Denk <wd@denx.de> |
| 17 | */ |
| 18 | |
| 19 | #include <common.h> |
Simon Glass | 1fa70f8 | 2019-11-14 12:57:34 -0700 | [diff] [blame] | 20 | #include <cpu_func.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame^] | 21 | #include <net.h> |
Simon Glass | a9dc068 | 2019-12-28 10:44:59 -0700 | [diff] [blame] | 22 | #include <time.h> |
Simon Glass | f5c208d | 2019-11-14 12:57:20 -0700 | [diff] [blame] | 23 | #include <vsprintf.h> |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 24 | #include <watchdog.h> |
| 25 | #include <command.h> |
| 26 | #include <mpc8xx.h> |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 27 | #include <netdev.h> |
| 28 | #include <asm/cache.h> |
Christophe Leroy | 10ff63a | 2018-03-16 17:20:43 +0100 | [diff] [blame] | 29 | #include <asm/cpm_8xx.h> |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 30 | #include <linux/compiler.h> |
| 31 | #include <asm/io.h> |
| 32 | |
| 33 | #if defined(CONFIG_OF_LIBFDT) |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 34 | #include <linux/libfdt.h> |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 35 | #include <fdt_support.h> |
| 36 | #endif |
| 37 | |
| 38 | DECLARE_GLOBAL_DATA_PTR; |
| 39 | |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 40 | /* ------------------------------------------------------------------------- */ |
| 41 | /* L1 i-cache */ |
| 42 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 43 | int checkicache(void) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 44 | { |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 45 | immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 46 | memctl8xx_t __iomem *memctl = &immap->im_memctl; |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 47 | u32 cacheon = rd_ic_cst() & IDC_ENABLED; |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 48 | /* probe in flash memoryarea */ |
| 49 | u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 50 | u32 m; |
| 51 | u32 lines = -1; |
| 52 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 53 | wr_ic_cst(IDC_UNALL); |
| 54 | wr_ic_cst(IDC_INVALL); |
| 55 | wr_ic_cst(IDC_DISABLE); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 56 | __asm__ volatile ("isync"); |
| 57 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 58 | while (!((m = rd_ic_cst()) & IDC_CERR2)) { |
| 59 | wr_ic_adr(k); |
| 60 | wr_ic_cst(IDC_LDLCK); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 61 | __asm__ volatile ("isync"); |
| 62 | |
| 63 | lines++; |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 64 | k += 0x10; /* the number of bytes in a cacheline */ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 65 | } |
| 66 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 67 | wr_ic_cst(IDC_UNALL); |
| 68 | wr_ic_cst(IDC_INVALL); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 69 | |
| 70 | if (cacheon) |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 71 | wr_ic_cst(IDC_ENABLE); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 72 | else |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 73 | wr_ic_cst(IDC_DISABLE); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 74 | |
| 75 | __asm__ volatile ("isync"); |
| 76 | |
| 77 | return lines << 4; |
| 78 | }; |
| 79 | |
| 80 | /* ------------------------------------------------------------------------- */ |
| 81 | /* L1 d-cache */ |
| 82 | /* call with cache disabled */ |
| 83 | |
Simon Glass | 1ba89d7 | 2019-11-14 12:57:38 -0700 | [diff] [blame] | 84 | static int checkdcache(void) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 85 | { |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 86 | immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 87 | memctl8xx_t __iomem *memctl = &immap->im_memctl; |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 88 | u32 cacheon = rd_dc_cst() & IDC_ENABLED; |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 89 | /* probe in flash memoryarea */ |
| 90 | u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 91 | u32 m; |
| 92 | u32 lines = -1; |
| 93 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 94 | wr_dc_cst(IDC_UNALL); |
| 95 | wr_dc_cst(IDC_INVALL); |
| 96 | wr_dc_cst(IDC_DISABLE); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 97 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 98 | while (!((m = rd_dc_cst()) & IDC_CERR2)) { |
| 99 | wr_dc_adr(k); |
| 100 | wr_dc_cst(IDC_LDLCK); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 101 | lines++; |
| 102 | k += 0x10; /* the number of bytes in a cacheline */ |
| 103 | } |
| 104 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 105 | wr_dc_cst(IDC_UNALL); |
| 106 | wr_dc_cst(IDC_INVALL); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 107 | |
| 108 | if (cacheon) |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 109 | wr_dc_cst(IDC_ENABLE); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 110 | else |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 111 | wr_dc_cst(IDC_DISABLE); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 112 | |
| 113 | return lines << 4; |
| 114 | }; |
| 115 | |
Simon Glass | 1ba89d7 | 2019-11-14 12:57:38 -0700 | [diff] [blame] | 116 | static int check_CPU(long clock, uint pvr, uint immr) |
| 117 | { |
| 118 | immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 119 | uint k; |
| 120 | char buf[32]; |
| 121 | |
| 122 | /* the highest 16 bits should be 0x0050 for a 860 */ |
| 123 | |
| 124 | if (PVR_VER(pvr) != PVR_VER(PVR_8xx)) |
| 125 | return -1; |
| 126 | |
| 127 | k = (immr << 16) | |
| 128 | in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]); |
| 129 | |
| 130 | /* |
| 131 | * Some boards use sockets so different CPUs can be used. |
| 132 | * We have to check chip version in run time. |
| 133 | */ |
| 134 | switch (k) { |
| 135 | /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ |
| 136 | case 0x08010004: /* Rev. A.0 */ |
| 137 | printf("MPC866xxxZPnnA"); |
| 138 | break; |
| 139 | case 0x08000003: /* Rev. 0.3 */ |
| 140 | printf("MPC866xxxZPnn"); |
| 141 | break; |
| 142 | case 0x09000000: /* 870/875/880/885 */ |
| 143 | puts("MPC885ZPnn"); |
| 144 | break; |
| 145 | |
| 146 | default: |
| 147 | printf("unknown MPC86x (0x%08x)", k); |
| 148 | break; |
| 149 | } |
| 150 | |
| 151 | printf(" at %s MHz: ", strmhz(buf, clock)); |
| 152 | |
| 153 | print_size(checkicache(), " I-Cache "); |
| 154 | print_size(checkdcache(), " D-Cache"); |
| 155 | |
| 156 | /* do we have a FEC (860T/P or 852/859/866/885)? */ |
| 157 | |
| 158 | out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678); |
| 159 | if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678) |
| 160 | printf(" FEC present"); |
| 161 | |
| 162 | putc('\n'); |
| 163 | |
| 164 | return 0; |
| 165 | } |
| 166 | |
| 167 | /* ------------------------------------------------------------------------- */ |
| 168 | |
| 169 | int checkcpu(void) |
| 170 | { |
| 171 | ulong clock = gd->cpu_clk; |
| 172 | uint immr = get_immr(); /* Return full IMMR contents */ |
| 173 | uint pvr = get_pvr(); |
| 174 | |
| 175 | puts("CPU: "); |
| 176 | |
| 177 | return check_CPU(clock, pvr, immr); |
| 178 | } |
| 179 | |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 180 | /* ------------------------------------------------------------------------- */ |
| 181 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 182 | void upmconfig(uint upm, uint *table, uint size) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 183 | { |
| 184 | uint i; |
| 185 | uint addr = 0; |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 186 | immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 187 | memctl8xx_t __iomem *memctl = &immap->im_memctl; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 188 | |
| 189 | for (i = 0; i < size; i++) { |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 190 | out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */ |
| 191 | out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 192 | addr++; |
| 193 | } |
| 194 | } |
| 195 | |
| 196 | /* ------------------------------------------------------------------------- */ |
| 197 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 198 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 199 | { |
| 200 | ulong msr, addr; |
| 201 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 202 | immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 203 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 204 | /* Checkstop Reset enable */ |
| 205 | setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 206 | |
| 207 | /* Interrupts and MMU off */ |
| 208 | __asm__ volatile ("mtspr 81, 0"); |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 209 | __asm__ volatile ("mfmsr %0" : "=r" (msr)); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 210 | |
| 211 | msr &= ~0x1030; |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 212 | __asm__ volatile ("mtmsr %0" : : "r" (msr)); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 213 | |
| 214 | /* |
| 215 | * Trying to execute the next instruction at a non-existing address |
| 216 | * should cause a machine check, resulting in reset |
| 217 | */ |
| 218 | #ifdef CONFIG_SYS_RESET_ADDRESS |
| 219 | addr = CONFIG_SYS_RESET_ADDRESS; |
| 220 | #else |
| 221 | /* |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 222 | * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, |
| 223 | * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address. |
| 224 | * Better pick an address known to be invalid on your system and assign |
| 225 | * it to CONFIG_SYS_RESET_ADDRESS. |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 226 | * "(ulong)-1" used to be a good choice for many systems... |
| 227 | */ |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 228 | addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 229 | #endif |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 230 | ((void (*)(void)) addr)(); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 231 | return 1; |
| 232 | } |
| 233 | |
| 234 | /* ------------------------------------------------------------------------- */ |
| 235 | |
| 236 | /* |
| 237 | * Get timebase clock frequency (like cpu_clk in Hz) |
| 238 | * |
| 239 | * See sections 14.2 and 14.6 of the User's Manual |
| 240 | */ |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 241 | unsigned long get_tbclk(void) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 242 | { |
Christophe Leroy | 5c59bdf | 2018-03-16 17:20:33 +0100 | [diff] [blame] | 243 | immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 244 | ulong oscclk, factor, pll; |
| 245 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 246 | if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS) |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 247 | return gd->cpu_clk / 16; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 248 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 249 | pll = in_be32(&immap->im_clkrst.car_plprcr); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 250 | |
| 251 | #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) |
| 252 | |
| 253 | /* |
| 254 | * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication |
| 255 | * factor is calculated as follows: |
| 256 | * |
| 257 | * MFN |
| 258 | * MFI + ------- |
| 259 | * MFD + 1 |
| 260 | * factor = ----------------- |
| 261 | * (PDF + 1) * 2^S |
| 262 | * |
| 263 | */ |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 264 | factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) / |
| 265 | (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S)); |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 266 | |
| 267 | oscclk = gd->cpu_clk / factor; |
| 268 | |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 269 | if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 || |
| 270 | factor > 2) |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 271 | return oscclk / 4; |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 272 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 273 | return oscclk / 16; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 274 | } |
| 275 | |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 276 | /* |
| 277 | * Initializes on-chip ethernet controllers. |
| 278 | * to override, implement board_eth_init() |
| 279 | */ |
| 280 | int cpu_eth_init(bd_t *bis) |
| 281 | { |
Christophe Leroy | 56ef30a | 2017-07-06 10:33:23 +0200 | [diff] [blame] | 282 | #if defined(CONFIG_MPC8XX_FEC) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 283 | fec_initialize(bis); |
| 284 | #endif |
| 285 | return 0; |
| 286 | } |