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Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +02001/*
2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +02009 */
10
11#include <common.h>
12#include <mpc5xxx.h>
Heiko Schocher50219e62009-03-26 07:33:59 +010013#include <net.h>
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020014#include <asm/processor.h>
15
Simon Glass39f90ba2017-03-31 08:40:25 -060016DECLARE_GLOBAL_DATA_PTR;
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010017
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020018#ifndef CONFIG_SYS_RAMBOOT
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020019static void sdram_start(int hi_addr)
20{
21 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
22
23 /* unlock mode register */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010024 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020025 __asm__ volatile ("sync");
26
27 /* precharge all banks */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010028 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020029 __asm__ volatile ("sync");
30
31#if SDRAM_DDR
32 /* set mode register: extended mode */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010033 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020034 __asm__ volatile ("sync");
35
36 /* set mode register: reset DLL */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010037 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020038 __asm__ volatile ("sync");
39#endif /* SDRAM_DDR */
40
41 /* precharge all banks */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010042 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020043 __asm__ volatile ("sync");
44
45 /* auto refresh */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010046 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020047 __asm__ volatile ("sync");
48
49 /* set mode register */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010050 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020051 __asm__ volatile ("sync");
52
53 /* normal operation */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010054 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020055 __asm__ volatile ("sync");
56}
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#endif /* !CONFIG_SYS_RAMBOOT */
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020058
59
Simon Glassd35f3382017-04-06 12:47:05 -060060int dram_init(void)
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020061{
62 ulong dramsize = 0;
63 ulong dramsize2 = 0;
64 uint svr, pvr;
65
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020066#ifndef CONFIG_SYS_RAMBOOT
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020067 ulong test1, test2;
68
69 /* setup SDRAM chip selects */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010070 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
71 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020072 __asm__ volatile ("sync");
73
74 /* setup config registers */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010075 *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
76 *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020077 __asm__ volatile ("sync");
78
79#if SDRAM_DDR
80 /* set tap delay */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +010081 *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020082 __asm__ volatile ("sync");
83#endif /* SDRAM_DDR */
84
85 /* find RAM size using SDRAM CS0 only */
86 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020088 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +020090 if (test1 > test2) {
91 sdram_start(0);
92 dramsize = test1;
93 } else
94 dramsize = test2;
95
96 /* memory smaller than 1MB is impossible */
97 if (dramsize < (1 << 20))
98 dramsize = 0;
99
100 /* set SDRAM CS0 size according to the amount of RAM found */
101 if (dramsize > 0)
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100102 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200103 else
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100104 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200105
106 /* let SDRAM CS1 start right after CS0 */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100107 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200108
109 /* find RAM size using SDRAM CS1 only */
110 if (!dramsize)
111 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112 test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200113 if (!dramsize) {
114 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115 test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200116 }
117 if (test1 > test2) {
118 sdram_start(0);
119 dramsize2 = test1;
120 } else
121 dramsize2 = test2;
122
123 /* memory smaller than 1MB is impossible */
124 if (dramsize2 < (1 << 20))
125 dramsize2 = 0;
126
127 /* set SDRAM CS1 size according to the amount of RAM found */
128 if (dramsize2 > 0)
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100129 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200130 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
131 else
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100132 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200133
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#else /* CONFIG_SYS_RAMBOOT */
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200135
136 /* retrieve size of memory connected to SDRAM CS0 */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100137 dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200138 if (dramsize >= 0x13)
139 dramsize = (1 << (dramsize - 0x13)) << 20;
140 else
141 dramsize = 0;
142
143 /* retrieve size of memory connected to SDRAM CS1 */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100144 dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200145 if (dramsize2 >= 0x13)
146 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
147 else
148 dramsize2 = 0;
149
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#endif /* CONFIG_SYS_RAMBOOT */
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200151
152 /*
153 * On MPC5200B we need to set the special configuration delay in the
154 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
155 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
156 *
157 * "The SDelay should be written to a value of 0x00000004. It is
158 * required to account for changes caused by normal wafer processing
159 * parameters."
160 */
161 svr = get_svr();
162 pvr = get_pvr();
163 if ((SVR_MJREV(svr) >= 2) &&
164 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
165
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100166 *(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200167 __asm__ volatile ("sync");
168 }
169
Simon Glass39f90ba2017-03-31 08:40:25 -0600170 gd->ram_size = dramsize + dramsize2;
171
172 return 0;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200173}
174
175
176int checkboard (void)
177{
178 puts("Board: MarelV38B\n");
179 return 0;
180}
181
Bartlomiej Sieka37e66642006-12-28 19:08:21 +0100182int board_early_init_f(void)
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200183{
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100184#ifdef CONFIG_HW_WATCHDOG
185 /*
186 * Enable and configure the direction (output) of PSC3_9 - watchdog
187 * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
188 * Manual.
189 */
190 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
191 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
192#endif /* CONFIG_HW_WATCHDOG */
Bartlomiej Sieka37e66642006-12-28 19:08:21 +0100193 return 0;
194}
195
196int board_early_init_r(void)
197{
198 /*
199 * Now, when we are in RAM, enable flash write access for the
200 * detection process. Note that CS_BOOT cannot be cleared when
201 * executing in flash.
202 */
203 *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100204
205 /*
206 * Enable GPIO_WKUP_7 to "read the status of the actual power
207 * situation". Default direction is input, so no need to set it
208 * explicitly.
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200209 */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100210 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200211 return 0;
212}
213
Mike Frysinger13e9bb92009-02-16 18:03:14 -0500214extern void board_get_enetaddr(uchar *enetaddr);
215int misc_init_r(void)
216{
217 uchar enetaddr[6];
218
219 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
220 board_get_enetaddr(enetaddr);
Heiko Schocher50219e62009-03-26 07:33:59 +0100221 eth_setenv_enetaddr("ethaddr", enetaddr);
Mike Frysinger13e9bb92009-02-16 18:03:14 -0500222 }
223
224 return 0;
225}
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200226
Simon Glassb569a012017-05-17 03:25:30 -0600227#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200228void init_ide_reset(void)
229{
230 debug("init_ide_reset\n");
231
232 /* Configure PSC1_4 as GPIO output for ATA reset */
233 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100234 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200235 /* Deassert reset */
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100236 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200237}
238
239
240void ide_set_reset(int idereset)
241{
242 debug("ide_reset(%d)\n", idereset);
243
244 if (idereset) {
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100245 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200246 /* Make a delay. MPC5200 spec says 25 usec min */
247 udelay(500000);
248 } else
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100249 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200250}
Jon Loeliger761ea742007-07-10 10:48:22 -0500251#endif
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200252
253
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100254#ifdef CONFIG_HW_WATCHDOG
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200255void hw_watchdog_reset(void)
256{
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100257 /*
258 * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
259 * we need a positive or negative transition on WDI i.e., our PSC3_9.
260 */
261 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
Bartlomiej Sieka2dfa3d22006-10-13 21:09:09 +0200262}
Bartlomiej Sieka252eede2006-11-01 02:04:38 +0100263#endif /* CONFIG_HW_WATCHDOG */