blob: 99b318fd8f747602675a8a873eb655d9b0a94b17 [file] [log] [blame]
Masahiro Yamadafa714412015-07-21 14:04:22 +09001/*
Masahiro Yamada3a67e9d2017-01-15 14:59:07 +09002 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadafa714412015-07-21 14:04:22 +09005 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
Masahiro Yamadafa714412015-07-21 14:04:22 +09009#include <linux/io.h>
Masahiro Yamadaefdf3402016-01-09 01:51:13 +090010
11#include "../init.h"
12#include "bcu-regs.h"
Masahiro Yamadafa714412015-07-21 14:04:22 +090013
14#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
15
Masahiro Yamada3a67e9d2017-01-15 14:59:07 +090016void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
Masahiro Yamadafa714412015-07-21 14:04:22 +090017{
18 int shift;
19
20 writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
21 writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
22 writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
23 /*
24 * 0xe0000000-0xefffffff: Ex-bus
25 * 0xf0000000-0xfbffffff: ASM bus
26 * 0xfc000000-0xffffffff: OCM bus
27 */
28 writel(0x24440000, BCSCR5);
29
30 /* Specify DDR channel */
Masahiro Yamada3dc80972017-02-05 10:52:12 +090031 shift = bd->dram_ch[0].size / 0x04000000 * 4;
Masahiro Yamadafa714412015-07-21 14:04:22 +090032 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
33
34 shift -= 32;
35 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
36
37 shift -= 32;
38 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
Masahiro Yamadafa714412015-07-21 14:04:22 +090039}