blob: f857ef3c0f33c3c747b0812b54084a1b6d583e69 [file] [log] [blame]
Niklaus Giger13f9f1e2007-07-27 11:28:44 +02001/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_ARCH(powerpc)
Niklaus Giger13f9f1e2007-07-27 11:28:44 +020025
26SECTIONS
27{
28 .resetvec 0xFFFFFFFC :
29 {
30 *(.resetvec)
31 } = 0xffff
32
33 .bootpg 0xFFFFF000 :
34 {
35 cpu/ppc4xx/start.o (.bootpg)
36 } = 0xffff
37
38 /* Read-only sections, merged into text segment: */
39 . = + SIZEOF_HEADERS;
40 .interp : { *(.interp) }
41 .hash : { *(.hash) }
42 .dynsym : { *(.dynsym) }
43 .dynstr : { *(.dynstr) }
44 .rel.text : { *(.rel.text) }
Wolfgang Denka1be4762008-05-20 16:00:29 +020045 .rela.text : { *(.rela.text) }
Niklaus Giger13f9f1e2007-07-27 11:28:44 +020046 .rel.data : { *(.rel.data) }
Wolfgang Denka1be4762008-05-20 16:00:29 +020047 .rela.data : { *(.rela.data) }
48 .rel.rodata : { *(.rel.rodata) }
49 .rela.rodata : { *(.rela.rodata) }
Niklaus Giger13f9f1e2007-07-27 11:28:44 +020050 .rel.got : { *(.rel.got) }
51 .rela.got : { *(.rela.got) }
52 .rel.ctors : { *(.rel.ctors) }
53 .rela.ctors : { *(.rela.ctors) }
54 .rel.dtors : { *(.rel.dtors) }
55 .rela.dtors : { *(.rela.dtors) }
56 .rel.bss : { *(.rel.bss) }
57 .rela.bss : { *(.rela.bss) }
58 .rel.plt : { *(.rel.plt) }
59 .rela.plt : { *(.rela.plt) }
60 .init : { *(.init) }
61 .plt : { *(.plt) }
62 .text :
63 {
64 /* WARNING - the following is hand-optimized to fit within */
65 /* the sector layout of our flash chips! XXX FIXME XXX */
66
67 cpu/ppc4xx/start.o (.text)
68
69 *(.text)
70 *(.fixup)
71 *(.got1)
72 }
73 _etext = .;
74 PROVIDE (etext = .);
75 .rodata :
76 {
77 *(.rodata)
78 *(.rodata1)
79 *(.rodata.str1.4)
80 }
81 .fini : { *(.fini) } =0
82 .ctors : { *(.ctors) }
83 .dtors : { *(.dtors) }
84
85 /* Read-write section, merged into data segment: */
86 . = (. + 0x00FF) & 0xFFFFFF00;
87 _erotext = .;
88 PROVIDE (erotext = .);
89 .reloc :
90 {
91 *(.got)
92 _GOT2_TABLE_ = .;
93 *(.got2)
94 _FIXUP_TABLE_ = .;
95 *(.fixup)
96 }
97 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
98 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
99
100 .data :
101 {
102 *(.data)
103 *(.data1)
104 *(.sdata)
105 *(.sdata2)
106 *(.dynamic)
107 CONSTRUCTORS
108 }
109 _edata = .;
110 PROVIDE (edata = .);
111
112 . = .;
113 __u_boot_cmd_start = .;
114 .u_boot_cmd : { *(.u_boot_cmd) }
115 __u_boot_cmd_end = .;
116
117
118 . = .;
119 __start___ex_table = .;
120 __ex_table : { *(__ex_table) }
121 __stop___ex_table = .;
122
123 . = ALIGN(256);
124 __init_begin = .;
125 .text.init : { *(.text.init) }
126 .data.init : { *(.data.init) }
127 . = ALIGN(256);
128 __init_end = .;
129
130 __bss_start = .;
Wolfgang Denk828a9782008-01-12 20:31:39 +0100131 .bss (NOLOAD) :
Niklaus Giger13f9f1e2007-07-27 11:28:44 +0200132 {
133 *(.sbss) *(.scommon)
134 *(.dynbss)
135 *(.bss)
136 *(COMMON)
137 }
138
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139 ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
Niklaus Giger13f9f1e2007-07-27 11:28:44 +0200140
141 _end = . ;
142 PROVIDE (end = .);
143}