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git01.mediatek.com / filogic / uboot / 2717e166102345e6f10f17c6beae2ce35a03d561 / . / arch / arm / include / asm / arch-exynos / power.h
blob: 6444fd04ec12a46bec9cb6a6917e1be664f70285 [file] [log] [blame]
HeungJun, Kimb3717272012-01-16 21:13:04 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __ASM_ARM_ARCH_POWER_H_
25#define __ASM_ARM_ARCH_POWER_H_
26
27#ifndef __ASSEMBLY__
28struct exynos4_power {
29 unsigned int om_stat;
30 unsigned char res1[0x8];
31 unsigned int rtc_clko_sel;
32 unsigned int gnss_rtc_out_ctrl;
33 unsigned char res2[0x1ec];
34 unsigned int system_power_down_ctrl;
35 unsigned char res3[0x1];
36 unsigned int system_power_down_option;
37 unsigned char res4[0x1f4];
38 unsigned int swreset;
39 unsigned int rst_stat;
40 unsigned char res5[0x1f8];
41 unsigned int wakeup_stat;
42 unsigned int eint_wakeup_mask;
43 unsigned int wakeup_mask;
44 unsigned char res6[0xf4];
45 unsigned int hdmi_phy_control;
46 unsigned int usbdevice_phy_control;
47 unsigned int usbhost_phy_control;
48 unsigned int dac_phy_control;
49 unsigned int mipi_phy0_control;
50 unsigned int mipi_phy1_control;
51 unsigned int adc_phy_control;
52 unsigned int pcie_phy_control;
53 unsigned int sata_phy_control;
54 unsigned char res7[0xdc];
55 unsigned int inform0;
56 unsigned int inform1;
57 unsigned int inform2;
58 unsigned int inform3;
59 unsigned int inform4;
60 unsigned int inform5;
61 unsigned int inform6;
62 unsigned int inform7;
63 unsigned char res8[0x1e0];
64 unsigned int pmu_debug;
65 unsigned char res9[0x5fc];
66 unsigned int arm_core0_sys_pwr_reg;
67 unsigned char res10[0xc];
68 unsigned int arm_core1_sys_pwr_reg;
69 unsigned char res11[0x6c];
70 unsigned int arm_common_sys_pwr_reg;
71 unsigned char res12[0x3c];
72 unsigned int arm_cpu_l2_0_sys_pwr_reg;
73 unsigned int arm_cpu_l2_1_sys_pwr_reg;
74 unsigned char res13[0x38];
75 unsigned int cmu_aclkstop_sys_pwr_reg;
76 unsigned int cmu_sclkstop_sys_pwr_reg;
77 unsigned char res14[0x4];
78 unsigned int cmu_reset_sys_pwr_reg;
79 unsigned char res15[0x10];
80 unsigned int apll_sysclk_sys_pwr_reg;
81 unsigned int mpll_sysclk_sys_pwr_reg;
82 unsigned int vpll_sysclk_sys_pwr_reg;
83 unsigned int epll_sysclk_sys_pwr_reg;
84 unsigned char res16[0x8];
85 unsigned int cmu_clkstop_gps_alive_sys_pwr_reg;
86 unsigned int cmu_reset_gps_alive_sys_pwr_reg;
87 unsigned int cmu_clkstop_cam_sys_pwr_reg;
88 unsigned int cmu_clkstop_tv_sys_pwr_reg;
89 unsigned int cmu_clkstop_mfc_sys_pwr_reg;
90 unsigned int cmu_clkstop_g3d_sys_pwr_reg;
91 unsigned int cmu_clkstop_lcd0_sys_pwr_reg;
92 unsigned int cmu_clkstop_lcd1_sys_pwr_reg;
93 unsigned int cmu_clkstop_maudio_sys_pwr_reg;
94 unsigned int cmu_clkstop_gps_sys_pwr_reg;
95 unsigned int cmu_reset_cam_sys_pwr_reg;
96 unsigned int cmu_reset_tv_sys_pwr_reg;
97 unsigned int cmu_reset_mfc_sys_pwr_reg;
98 unsigned int cmu_reset_g3d_sys_pwr_reg;
99 unsigned int cmu_reset_lcd0_sys_pwr_reg;
100 unsigned int cmu_reset_lcd1_sys_pwr_reg;
101 unsigned int cmu_reset_maudio_sys_pwr_reg;
102 unsigned int cmu_reset_gps_sys_pwr_reg;
103 unsigned int top_bus_sys_pwr_reg;
104 unsigned int top_retention_sys_pwr_reg;
105 unsigned int top_pwr_sys_pwr_reg;
106 unsigned char res17[0x1c];
107 unsigned int logic_reset_sys_pwr_reg;
108 unsigned char res18[0x14];
109 unsigned int onenandxl_mem_sys_pwr_reg;
110 unsigned int modemif_mem_sys_pwr_reg;
111 unsigned char res19[0x4];
112 unsigned int usbdevice_mem_sys_pwr_reg;
113 unsigned int sdmmc_mem_sys_pwr_reg;
114 unsigned int cssys_mem_sys_pwr_reg;
115 unsigned int secss_mem_sys_pwr_reg;
116 unsigned char res20[0x4];
117 unsigned int pcie_mem_sys_pwr_reg;
118 unsigned int sata_mem_sys_pwr_reg;
119 unsigned char res21[0x18];
120 unsigned int pad_retention_dram_sys_pwr_reg;
121 unsigned int pad_retention_maudio_sys_pwr_reg;
122 unsigned char res22[0x18];
123 unsigned int pad_retention_gpio_sys_pwr_reg;
124 unsigned int pad_retention_uart_sys_pwr_reg;
125 unsigned int pad_retention_mmca_sys_pwr_reg;
126 unsigned int pad_retention_mmcb_sys_pwr_reg;
127 unsigned int pad_retention_ebia_sys_pwr_reg;
128 unsigned int pad_retention_ebib_sys_pwr_reg;
129 unsigned char res23[0x8];
130 unsigned int pad_isolation_sys_pwr_reg;
131 unsigned char res24[0x1c];
132 unsigned int pad_alv_sel_sys_pwr_reg;
133 unsigned char res25[0x1c];
134 unsigned int xusbxti_sys_pwr_reg;
135 unsigned int xxti_sys_pwr_reg;
136 unsigned char res26[0x38];
137 unsigned int ext_regulator_sys_pwr_reg;
138 unsigned char res27[0x3c];
139 unsigned int gpio_mode_sys_pwr_reg;
140 unsigned char res28[0x3c];
141 unsigned int gpio_mode_maudio_sys_pwr_reg;
142 unsigned char res29[0x3c];
143 unsigned int cam_sys_pwr_reg;
144 unsigned int tv_sys_pwr_reg;
145 unsigned int mfc_sys_pwr_reg;
146 unsigned int g3d_sys_pwr_reg;
147 unsigned int lcd0_sys_pwr_reg;
148 unsigned int lcd1_sys_pwr_reg;
149 unsigned int maudio_sys_pwr_reg;
150 unsigned int gps_sys_pwr_reg;
151 unsigned int gps_alive_sys_pwr_reg;
152 unsigned char res30[0xc5c];
153 unsigned int arm_core0_configuration;
154 unsigned int arm_core0_status;
155 unsigned int arm_core0_option;
156 unsigned char res31[0x74];
157 unsigned int arm_core1_configuration;
158 unsigned int arm_core1_status;
159 unsigned int arm_core1_option;
160 unsigned char res32[0x37c];
161 unsigned int arm_common_option;
162 unsigned char res33[0x1f4];
163 unsigned int arm_cpu_l2_0_configuration;
164 unsigned int arm_cpu_l2_0_status;
165 unsigned char res34[0x18];
166 unsigned int arm_cpu_l2_1_configuration;
167 unsigned int arm_cpu_l2_1_status;
168 unsigned char res35[0xa00];
169 unsigned int pad_retention_maudio_option;
170 unsigned char res36[0xdc];
171 unsigned int pad_retention_gpio_option;
172 unsigned char res37[0x1c];
173 unsigned int pad_retention_uart_option;
174 unsigned char res38[0x1c];
175 unsigned int pad_retention_mmca_option;
176 unsigned char res39[0x1c];
177 unsigned int pad_retention_mmcb_option;
178 unsigned char res40[0x1c];
179 unsigned int pad_retention_ebia_option;
180 unsigned char res41[0x1c];
181 unsigned int pad_retention_ebib_option;
182 unsigned char res42[0x160];
183 unsigned int ps_hold_control;
184 unsigned char res43[0xf0];
185 unsigned int xusbxti_configuration;
186 unsigned int xusbxti_status;
187 unsigned char res44[0x14];
188 unsigned int xusbxti_duration;
189 unsigned int xxti_configuration;
190 unsigned int xxti_status;
191 unsigned char res45[0x14];
192 unsigned int xxti_duration;
193 unsigned char res46[0x1dc];
194 unsigned int ext_regulator_duration;
195 unsigned char res47[0x5e0];
196 unsigned int cam_configuration;
197 unsigned int cam_status;
198 unsigned int cam_option;
199 unsigned char res48[0x14];
200 unsigned int tv_configuration;
201 unsigned int tv_status;
202 unsigned int tv_option;
203 unsigned char res49[0x14];
204 unsigned int mfc_configuration;
205 unsigned int mfc_status;
206 unsigned int mfc_option;
207 unsigned char res50[0x14];
208 unsigned int g3d_configuration;
209 unsigned int g3d_status;
210 unsigned int g3d_option;
211 unsigned char res51[0x14];
212 unsigned int lcd0_configuration;
213 unsigned int lcd0_status;
214 unsigned int lcd0_option;
215 unsigned char res52[0x14];
216 unsigned int lcd1_configuration;
217 unsigned int lcd1_status;
218 unsigned int lcd1_option;
219 unsigned char res53[0x34];
220 unsigned int gps_configuration;
221 unsigned int gps_status;
222 unsigned int gps_option;
223 unsigned char res54[0x14];
224 unsigned int gps_alive_configuration;
225 unsigned int gps_alive_status;
226 unsigned int gps_alive_option;
227};
228#endif /* __ASSEMBLY__ */
229
Donghwa Lee09552712012-04-05 19:36:10 +0000[diff] [blame]230void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
231
232#define EXYNOS_MIPI_PHY_ENABLE (1 << 0)
233#define EXYNOS_MIPI_PHY_SRESETN (1 << 1)
234#define EXYNOS_MIPI_PHY_MRESETN (1 << 2)
235
HeungJun, Kimb3717272012-01-16 21:13:04 +0000[diff] [blame]236#endif