blob: d349531261ed09695fdd88c58c7c67d697a35861 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stephen Warrena844b012014-03-25 11:39:33 -06002/*
3 * (C) Copyright 2014
4 * NVIDIA Corporation <www.nvidia.com>
Stephen Warrena844b012014-03-25 11:39:33 -06005 */
6
7#include <common.h>
Simon Glassb3d2ed32017-07-25 08:30:12 -06008#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Thierry Reding0f4c83b2014-12-09 22:25:21 -070010#include <power/as3722.h>
Simon Glassb3d2ed32017-07-25 08:30:12 -060011#include <power/pmic.h>
Thierry Reding0f4c83b2014-12-09 22:25:21 -070012
Stephen Warrenfa2a1232014-04-22 14:37:55 -060013#include <asm/arch/gpio.h>
Stephen Warrena844b012014-03-25 11:39:33 -060014#include <asm/arch/pinmux.h>
Thierry Reding0f4c83b2014-12-09 22:25:21 -070015
Stephen Warrena844b012014-03-25 11:39:33 -060016#include "pinmux-config-jetson-tk1.h"
17
18/*
19 * Routine: pinmux_init
20 * Description: Do individual peripheral pinmux configs
21 */
22void pinmux_init(void)
23{
Stephen Warren2516bef2015-02-18 13:27:04 -070024 pinmux_clear_tristate_input_clamping();
Stephen Warrenf16f64f2014-04-22 14:37:56 -060025
Stephen Warrenfa2a1232014-04-22 14:37:55 -060026 gpio_config_table(jetson_tk1_gpio_inits,
27 ARRAY_SIZE(jetson_tk1_gpio_inits));
28
Stephen Warrena844b012014-03-25 11:39:33 -060029 pinmux_config_pingrp_table(jetson_tk1_pingrps,
30 ARRAY_SIZE(jetson_tk1_pingrps));
31
32 pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
33 ARRAY_SIZE(jetson_tk1_drvgrps));
Stephen Warren8e7c1be2016-04-21 16:03:37 -060034
35 pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
36 ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
Stephen Warrena844b012014-03-25 11:39:33 -060037}
Thierry Reding0f4c83b2014-12-09 22:25:21 -070038
39#ifdef CONFIG_PCI_TEGRA
Simon Glassb3d2ed32017-07-25 08:30:12 -060040/* TODO: Convert to driver model */
41static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
Thierry Reding0f4c83b2014-12-09 22:25:21 -070042{
Thierry Reding0f4c83b2014-12-09 22:25:21 -070043 int err;
44
Simon Glassb3d2ed32017-07-25 08:30:12 -060045 if (sd > 6)
46 return -EINVAL;
47
48 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
Thierry Reding0f4c83b2014-12-09 22:25:21 -070049 if (err) {
Masahiro Yamada81e10422017-09-16 14:10:41 +090050 pr_err("failed to update SD control register: %d", err);
Thierry Reding0f4c83b2014-12-09 22:25:21 -070051 return err;
52 }
53
Simon Glassb3d2ed32017-07-25 08:30:12 -060054 return 0;
55}
56
57int tegra_pcie_board_init(void)
58{
59 struct udevice *dev;
60 int ret;
61
62 ret = uclass_get_device_by_driver(UCLASS_PMIC,
Simon Glass65130cd2020-12-28 20:34:56 -070063 DM_DRIVER_GET(pmic_as3722), &dev);
Simon Glassb3d2ed32017-07-25 08:30:12 -060064 if (ret) {
65 debug("%s: Failed to find PMIC\n", __func__);
66 return ret;
Thierry Reding0f4c83b2014-12-09 22:25:21 -070067 }
68
Simon Glassb3d2ed32017-07-25 08:30:12 -060069 ret = as3722_sd_enable(dev, 4);
70 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +090071 pr_err("failed to enable SD4: %d\n", ret);
Simon Glassb3d2ed32017-07-25 08:30:12 -060072 return ret;
73 }
74
75 ret = as3722_sd_set_voltage(dev, 4, 0x24);
76 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +090077 pr_err("failed to set SD4 voltage: %d\n", ret);
Simon Glassb3d2ed32017-07-25 08:30:12 -060078 return ret;
Thierry Reding0f4c83b2014-12-09 22:25:21 -070079 }
80
Thierry Reding0f4c83b2014-12-09 22:25:21 -070081 return 0;
82}
Thierry Reding0f4c83b2014-12-09 22:25:21 -070083#endif /* PCI */