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git01.mediatek.com / filogic / uboot / 26f5130fdbb30c280e10d649ccb31bd1e201ff1d / . / drivers / pinctrl / renesas / pfc-r8a77980.c
blob: 14a4b4dc731be64a23e2873299b0014c44ae4123 [file] [log] [blame]
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A77980 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 *
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]15#include <dm.h>
16#include <errno.h>
17#include <dm/pinctrl.h>
18#include <linux/kernel.h>
19
20#include "sh_pfc.h"
21
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]22#define CPU_ALL_GP(fn, sfx) \
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]23 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]24 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]25 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
26 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]27 PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
28 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
29
30#define CPU_ALL_NOGP(fn) \
31 PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
32 PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
33 PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
34 PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
35 PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
36 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
37 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
38 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]39 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
40 PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
41 PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]42
43/*
44 * F_() : just information
45 * FM() : macro for FN_xxx / xxx_MARK
46 */
47
48/* GPSR0 */
49#define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
50#define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
51#define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
52#define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
53#define GPSR0_17 F_(DU_DB7, IP2_7_4)
54#define GPSR0_16 F_(DU_DB6, IP2_3_0)
55#define GPSR0_15 F_(DU_DB5, IP1_31_28)
56#define GPSR0_14 F_(DU_DB4, IP1_27_24)
57#define GPSR0_13 F_(DU_DB3, IP1_23_20)
58#define GPSR0_12 F_(DU_DB2, IP1_19_16)
59#define GPSR0_11 F_(DU_DG7, IP1_15_12)
60#define GPSR0_10 F_(DU_DG6, IP1_11_8)
61#define GPSR0_9 F_(DU_DG5, IP1_7_4)
62#define GPSR0_8 F_(DU_DG4, IP1_3_0)
63#define GPSR0_7 F_(DU_DG3, IP0_31_28)
64#define GPSR0_6 F_(DU_DG2, IP0_27_24)
65#define GPSR0_5 F_(DU_DR7, IP0_23_20)
66#define GPSR0_4 F_(DU_DR6, IP0_19_16)
67#define GPSR0_3 F_(DU_DR5, IP0_15_12)
68#define GPSR0_2 F_(DU_DR4, IP0_11_8)
69#define GPSR0_1 F_(DU_DR3, IP0_7_4)
70#define GPSR0_0 F_(DU_DR2, IP0_3_0)
71
72/* GPSR1 */
73#define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
74#define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
75#define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
76#define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
77#define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
78#define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
79#define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
80#define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
81#define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
82#define GPSR1_18 FM(AVB_LINK)
83#define GPSR1_17 FM(AVB_PHY_INT)
84#define GPSR1_16 FM(AVB_MAGIC)
85#define GPSR1_15 FM(AVB_MDC)
86#define GPSR1_14 FM(AVB_MDIO)
87#define GPSR1_13 FM(AVB_TXCREFCLK)
88#define GPSR1_12 FM(AVB_TD3)
89#define GPSR1_11 FM(AVB_TD2)
90#define GPSR1_10 FM(AVB_TD1)
91#define GPSR1_9 FM(AVB_TD0)
92#define GPSR1_8 FM(AVB_TXC)
93#define GPSR1_7 FM(AVB_TX_CTL)
94#define GPSR1_6 FM(AVB_RD3)
95#define GPSR1_5 FM(AVB_RD2)
96#define GPSR1_4 FM(AVB_RD1)
97#define GPSR1_3 FM(AVB_RD0)
98#define GPSR1_2 FM(AVB_RXC)
99#define GPSR1_1 FM(AVB_RX_CTL)
100#define GPSR1_0 F_(IRQ0, IP2_27_24)
101
102/* GPSR2 */
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]103#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]104#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
105#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
106#define GPSR2_26 F_(SDA3, IP10_7_4)
107#define GPSR2_25 F_(SCL3, IP10_3_0)
108#define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
109#define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
110#define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
111#define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
112#define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
113#define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
114#define GPSR2_18 F_(IRQ5, IP9_7_4)
115#define GPSR2_17 F_(IRQ4, IP9_3_0)
116#define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
117#define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
118#define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
119#define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
120#define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
121#define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
122#define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
123#define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
124#define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
125#define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
126#define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
127#define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
128#define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
129#define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
130#define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
131#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
132#define GPSR2_0 F_(VI0_CLK, IP2_31_28)
133
134/* GPSR3 */
135#define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
136#define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
137#define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
138#define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
139#define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
140#define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
141#define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
142#define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
143#define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
144#define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
145#define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
146#define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
147#define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
148#define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
149#define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
150#define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
151#define GPSR3_0 F_(VI1_CLK, IP5_3_0)
152
153/* GPSR4 */
154#define GPSR4_24 FM(GETHER_LINK_A)
155#define GPSR4_23 FM(GETHER_PHY_INT_A)
156#define GPSR4_22 FM(GETHER_MAGIC)
157#define GPSR4_21 FM(GETHER_MDC_A)
158#define GPSR4_20 FM(GETHER_MDIO_A)
159#define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
160#define GPSR4_18 FM(GETHER_TXCREFCLK)
161#define GPSR4_17 FM(GETHER_TD3)
162#define GPSR4_16 FM(GETHER_TD2)
163#define GPSR4_15 FM(GETHER_TD1)
164#define GPSR4_14 FM(GETHER_TD0)
165#define GPSR4_13 FM(GETHER_TXC)
166#define GPSR4_12 FM(GETHER_TX_CTL)
167#define GPSR4_11 FM(GETHER_RD3)
168#define GPSR4_10 FM(GETHER_RD2)
169#define GPSR4_9 FM(GETHER_RD1)
170#define GPSR4_8 FM(GETHER_RD0)
171#define GPSR4_7 FM(GETHER_RXC)
172#define GPSR4_6 FM(GETHER_RX_CTL)
173#define GPSR4_5 F_(SDA2, IP7_27_24)
174#define GPSR4_4 F_(SCL2, IP7_23_20)
175#define GPSR4_3 F_(SDA1, IP7_19_16)
176#define GPSR4_2 F_(SCL1, IP7_15_12)
177#define GPSR4_1 F_(SDA0, IP7_11_8)
178#define GPSR4_0 F_(SCL0, IP7_7_4)
179
180/* GPSR5 */
181#define GPSR5_14 FM(RPC_INT_N)
182#define GPSR5_13 FM(RPC_WP_N)
183#define GPSR5_12 FM(RPC_RESET_N)
184#define GPSR5_11 FM(QSPI1_SSL)
185#define GPSR5_10 FM(QSPI1_IO3)
186#define GPSR5_9 FM(QSPI1_IO2)
187#define GPSR5_8 FM(QSPI1_MISO_IO1)
188#define GPSR5_7 FM(QSPI1_MOSI_IO0)
189#define GPSR5_6 FM(QSPI1_SPCLK)
190#define GPSR5_5 FM(QSPI0_SSL)
191#define GPSR5_4 FM(QSPI0_IO3)
192#define GPSR5_3 FM(QSPI0_IO2)
193#define GPSR5_2 FM(QSPI0_MISO_IO1)
194#define GPSR5_1 FM(QSPI0_MOSI_IO0)
195#define GPSR5_0 FM(QSPI0_SPCLK)
196
197
198/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
199#define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201#define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203#define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]268#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]269#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]272#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]273#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]284
285#define PINMUX_GPSR \
286\
287 GPSR2_29 \
288 GPSR2_28 \
289 GPSR1_27 GPSR2_27 \
290 GPSR1_26 GPSR2_26 \
291 GPSR1_25 GPSR2_25 \
292 GPSR1_24 GPSR2_24 GPSR4_24 \
293 GPSR1_23 GPSR2_23 GPSR4_23 \
294 GPSR1_22 GPSR2_22 GPSR4_22 \
295GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
296GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
297GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
298GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
299GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
300GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
301GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
302GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
303GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
304GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
305GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
306GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
307GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
308GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
309GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
310GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
311GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
312GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
313GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
314GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
315GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
316GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
317
318#define PINMUX_IPSR \
319\
320FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
321FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
322FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
323FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
324FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
325FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
326FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
327FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
328\
329FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
330FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
331FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
332FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
333FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
334FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
335FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
336FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
337\
338FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
339FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
340FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
341FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
342FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]343FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 \
344FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 \
345FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]346
347/* MOD_SEL0 */ /* 0 */ /* 1 */
348#define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
349#define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
350#define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
351#define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
352#define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
353#define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
354#define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
355#define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
356#define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
357#define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
358#define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
359
360#define PINMUX_MOD_SELS \
361\
362MOD_SEL0_11 \
363MOD_SEL0_10 \
364MOD_SEL0_9 \
365MOD_SEL0_8 \
366MOD_SEL0_7 \
367MOD_SEL0_6 \
368MOD_SEL0_5 \
369MOD_SEL0_4 \
370MOD_SEL0_2 \
371MOD_SEL0_1 \
372MOD_SEL0_0
373
374enum {
375 PINMUX_RESERVED = 0,
376
377 PINMUX_DATA_BEGIN,
378 GP_ALL(DATA),
379 PINMUX_DATA_END,
380
381#define F_(x, y)
382#define FM(x) FN_##x,
383 PINMUX_FUNCTION_BEGIN,
384 GP_ALL(FN),
385 PINMUX_GPSR
386 PINMUX_IPSR
387 PINMUX_MOD_SELS
388 PINMUX_FUNCTION_END,
389#undef F_
390#undef FM
391
392#define F_(x, y)
393#define FM(x) x##_MARK,
394 PINMUX_MARK_BEGIN,
395 PINMUX_GPSR
396 PINMUX_IPSR
397 PINMUX_MOD_SELS
398 PINMUX_MARK_END,
399#undef F_
400#undef FM
401};
402
403static const u16 pinmux_data[] = {
404 PINMUX_DATA_GP_ALL(),
405
406 PINMUX_SINGLE(AVB_RX_CTL),
407 PINMUX_SINGLE(AVB_RXC),
408 PINMUX_SINGLE(AVB_RD0),
409 PINMUX_SINGLE(AVB_RD1),
410 PINMUX_SINGLE(AVB_RD2),
411 PINMUX_SINGLE(AVB_RD3),
412 PINMUX_SINGLE(AVB_TX_CTL),
413 PINMUX_SINGLE(AVB_TXC),
414 PINMUX_SINGLE(AVB_TD0),
415 PINMUX_SINGLE(AVB_TD1),
416 PINMUX_SINGLE(AVB_TD2),
417 PINMUX_SINGLE(AVB_TD3),
418 PINMUX_SINGLE(AVB_TXCREFCLK),
419 PINMUX_SINGLE(AVB_MDIO),
420 PINMUX_SINGLE(AVB_MDC),
421 PINMUX_SINGLE(AVB_MAGIC),
422 PINMUX_SINGLE(AVB_PHY_INT),
423 PINMUX_SINGLE(AVB_LINK),
424
425 PINMUX_SINGLE(GETHER_RX_CTL),
426 PINMUX_SINGLE(GETHER_RXC),
427 PINMUX_SINGLE(GETHER_RD0),
428 PINMUX_SINGLE(GETHER_RD1),
429 PINMUX_SINGLE(GETHER_RD2),
430 PINMUX_SINGLE(GETHER_RD3),
431 PINMUX_SINGLE(GETHER_TX_CTL),
432 PINMUX_SINGLE(GETHER_TXC),
433 PINMUX_SINGLE(GETHER_TD0),
434 PINMUX_SINGLE(GETHER_TD1),
435 PINMUX_SINGLE(GETHER_TD2),
436 PINMUX_SINGLE(GETHER_TD3),
437 PINMUX_SINGLE(GETHER_TXCREFCLK),
438 PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
439 PINMUX_SINGLE(GETHER_MDIO_A),
440 PINMUX_SINGLE(GETHER_MDC_A),
441 PINMUX_SINGLE(GETHER_MAGIC),
442 PINMUX_SINGLE(GETHER_PHY_INT_A),
443 PINMUX_SINGLE(GETHER_LINK_A),
444
445 PINMUX_SINGLE(QSPI0_SPCLK),
446 PINMUX_SINGLE(QSPI0_MOSI_IO0),
447 PINMUX_SINGLE(QSPI0_MISO_IO1),
448 PINMUX_SINGLE(QSPI0_IO2),
449 PINMUX_SINGLE(QSPI0_IO3),
450 PINMUX_SINGLE(QSPI0_SSL),
451 PINMUX_SINGLE(QSPI1_SPCLK),
452 PINMUX_SINGLE(QSPI1_MOSI_IO0),
453 PINMUX_SINGLE(QSPI1_MISO_IO1),
454 PINMUX_SINGLE(QSPI1_IO2),
455 PINMUX_SINGLE(QSPI1_IO3),
456 PINMUX_SINGLE(QSPI1_SSL),
457 PINMUX_SINGLE(RPC_RESET_N),
458 PINMUX_SINGLE(RPC_WP_N),
459 PINMUX_SINGLE(RPC_INT_N),
460
461 /* IPSR0 */
462 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
463 PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
464 PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
465 PINMUX_IPSR_GPSR(IP0_3_0, A0),
466
467 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
468 PINMUX_IPSR_GPSR(IP0_7_4, RX4),
469 PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
470 PINMUX_IPSR_GPSR(IP0_7_4, A1),
471
472 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
473 PINMUX_IPSR_GPSR(IP0_11_8, TX4),
474 PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
475 PINMUX_IPSR_GPSR(IP0_11_8, A2),
476
477 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
478 PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
479 PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
480 PINMUX_IPSR_GPSR(IP0_15_12, A3),
481
482 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
483 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
484 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
485 PINMUX_IPSR_GPSR(IP0_19_16, A4),
486
487 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
488 PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
489 PINMUX_IPSR_GPSR(IP0_23_20, A5),
490
491 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
492 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
493 PINMUX_IPSR_GPSR(IP0_27_24, A6),
494
495 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
496 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
497 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
498 PINMUX_IPSR_GPSR(IP0_31_28, A7),
499 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
500
501 /* IPSR1 */
502 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
503 PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
504 PINMUX_IPSR_GPSR(IP1_3_0, A8),
505
506 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
507 PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
508 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
509 PINMUX_IPSR_GPSR(IP1_7_4, A9),
510
511 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
512 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
513 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
514 PINMUX_IPSR_GPSR(IP1_11_8, A10),
515
516 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
517 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
518 PINMUX_IPSR_GPSR(IP1_15_12, A11),
519
520 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
521 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
522 PINMUX_IPSR_GPSR(IP1_19_16, A12),
523 PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
524
525 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
526 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
527 PINMUX_IPSR_GPSR(IP1_23_20, A13),
528 PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
529
530 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
531 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
532 PINMUX_IPSR_GPSR(IP1_27_24, A14),
533 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
534
535 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
536 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
537 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
538 PINMUX_IPSR_GPSR(IP1_31_28, A15),
539
540 /* IPSR2 */
541 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
542 PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
543 PINMUX_IPSR_GPSR(IP2_3_0, A16),
544
545 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
546 PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
547 PINMUX_IPSR_GPSR(IP2_7_4, A17),
548
549 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
550 PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
551 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
552 PINMUX_IPSR_GPSR(IP2_11_8, A18),
553
554 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
555 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
556 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
557 PINMUX_IPSR_GPSR(IP2_15_12, A19),
558 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
559
560 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
561 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
562 PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
563
564 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
565 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
566
567 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
568
569 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
570 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
571 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
572 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
573
574 /* IPSR3 */
575 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
576 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
577 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
578 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
579 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
580
581 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
582 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
583 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
584 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
585
586 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
587 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
588 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
589 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
590
591 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
592 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
593 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
594 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
595
596 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
597 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
598 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
599 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
600
601 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
602 PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
603
604 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
605 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
606
607 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
608 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
609 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
610
611 /* IPSR4 */
612 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
613 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
614 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
615
616 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
617 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
618 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
619
620 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
621 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
622 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
623
624 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
625 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
626
627 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
628 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
629 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
630
631 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
632 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
633 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
634
635 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
636 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
637 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
638
639 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
640 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
641 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
642 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
643
644 /* IPSR5 */
645 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
646 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
647 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
648
649 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
650 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
651 PINMUX_IPSR_GPSR(IP5_7_4, D0),
652
653 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
654 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
655 PINMUX_IPSR_GPSR(IP5_11_8, D1),
656
657 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
658 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
659 PINMUX_IPSR_GPSR(IP5_15_12, D2),
660
661 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
662 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
663 PINMUX_IPSR_GPSR(IP5_19_16, D3),
664 PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
665
666 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
667 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
668 PINMUX_IPSR_GPSR(IP5_23_20, D4),
669 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
670
671 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
672 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
673 PINMUX_IPSR_GPSR(IP5_27_24, D5),
674 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
675
676 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
677 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
678 PINMUX_IPSR_GPSR(IP5_31_28, D6),
679 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
680
681 /* IPSR6 */
682 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
683 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
684 PINMUX_IPSR_GPSR(IP6_3_0, D7),
685 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
686
687 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
688 PINMUX_IPSR_GPSR(IP6_7_4, D8),
689 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
690
691 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
692 PINMUX_IPSR_GPSR(IP6_11_8, D9),
693 PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
694
695 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
696 PINMUX_IPSR_GPSR(IP6_15_12, D10),
697 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
698
699 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
700 PINMUX_IPSR_GPSR(IP6_19_16, D11),
701 PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
702
703 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
704 PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
705 PINMUX_IPSR_GPSR(IP6_23_20, D12),
706 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
707
708 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
709 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
710 PINMUX_IPSR_GPSR(IP6_27_24, D13),
711 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
712
713 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
714 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
715 PINMUX_IPSR_GPSR(IP6_31_28, D14),
716 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
717
718 /* IPSR7 */
719 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
720 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
721 PINMUX_IPSR_GPSR(IP7_3_0, D15),
722 PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
723
724 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
725 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
726
727 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
728 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
729 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
730 PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
731
732 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
733 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
734 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
735 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
736 PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
737
738 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
739 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
740 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
741 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
742 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
743
744 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
745 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
746 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
747 PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
748
749 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
750 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
751 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
752 PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
753
754 PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
755 PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
756
757 /* IPSR8 */
758 PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
759 PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
760
761 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
762 PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
763 PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
764 PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
765
766 PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
767 PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
768 PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
769 PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
770
771 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
772 PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
773 PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
774 PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
775 PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
776
777 PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
778 PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
779 PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
780 PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
781 PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
782
783 PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
784 PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
785 PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
786 PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
787 PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
788
789 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
790 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
791
792 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
793 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
794
795 /* IPSR9 */
796 PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
797 PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
798
799 PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
800 PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
801
802 PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
803 PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
804 PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
805
806 PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
807 PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
808 PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
809
810 PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
811 PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
812 PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
813
814 PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
815 PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
816 PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
817
818 PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
819 PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
820 PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
821 PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
822
823 PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
824 PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
825 PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
826 PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
827
828 /* IPSR10 */
829 PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
830 PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
831
832 PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
833 PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
834
835 PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
836 PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
837
838 PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
839 PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
840
841 PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
842};
843
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]844/*
845 * Pins not associated with a GPIO port.
846 */
847enum {
848 GP_ASSIGN_LAST(),
849 NOGP_ALL(),
850};
851
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]852static const struct sh_pfc_pin pinmux_pins[] = {
853 PINMUX_GPIO_GP_ALL(),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]854 PINMUX_NOGP_ALL(),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]855};
856
857/* - AVB -------------------------------------------------------------------- */
858static const unsigned int avb_link_pins[] = {
859 /* AVB_LINK */
860 RCAR_GP_PIN(1, 18),
861};
862static const unsigned int avb_link_mux[] = {
863 AVB_LINK_MARK,
864};
865static const unsigned int avb_magic_pins[] = {
866 /* AVB_MAGIC */
867 RCAR_GP_PIN(1, 16),
868};
869static const unsigned int avb_magic_mux[] = {
870 AVB_MAGIC_MARK,
871};
872static const unsigned int avb_phy_int_pins[] = {
873 /* AVB_PHY_INT */
874 RCAR_GP_PIN(1, 17),
875};
876static const unsigned int avb_phy_int_mux[] = {
877 AVB_PHY_INT_MARK,
878};
879static const unsigned int avb_mdio_pins[] = {
880 /* AVB_MDC, AVB_MDIO */
881 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
882};
883static const unsigned int avb_mdio_mux[] = {
884 AVB_MDC_MARK, AVB_MDIO_MARK,
885};
886static const unsigned int avb_rgmii_pins[] = {
887 /*
888 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
889 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
890 */
891 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
892 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
893 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
894 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
895 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
896 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
897};
898static const unsigned int avb_rgmii_mux[] = {
899 AVB_TX_CTL_MARK, AVB_TXC_MARK,
900 AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
901 AVB_RX_CTL_MARK, AVB_RXC_MARK,
902 AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
903};
904static const unsigned int avb_txcrefclk_pins[] = {
905 /* AVB_TXCREFCLK */
906 RCAR_GP_PIN(1, 13),
907};
908static const unsigned int avb_txcrefclk_mux[] = {
909 AVB_TXCREFCLK_MARK,
910};
911static const unsigned int avb_avtp_pps_pins[] = {
912 /* AVB_AVTP_PPS */
913 RCAR_GP_PIN(2, 6),
914};
915static const unsigned int avb_avtp_pps_mux[] = {
916 AVB_AVTP_PPS_MARK,
917};
918static const unsigned int avb_avtp_capture_pins[] = {
919 /* AVB_AVTP_CAPTURE */
920 RCAR_GP_PIN(1, 20),
921};
922static const unsigned int avb_avtp_capture_mux[] = {
923 AVB_AVTP_CAPTURE_MARK,
924};
925static const unsigned int avb_avtp_match_pins[] = {
926 /* AVB_AVTP_MATCH */
927 RCAR_GP_PIN(1, 19),
928};
929static const unsigned int avb_avtp_match_mux[] = {
930 AVB_AVTP_MATCH_MARK,
931};
932
933/* - CANFD0 ----------------------------------------------------------------- */
934static const unsigned int canfd0_data_a_pins[] = {
935 /* CANFD0_TX, CANFD0_RX */
936 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
937};
938static const unsigned int canfd0_data_a_mux[] = {
939 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
940};
941static const unsigned int canfd0_data_b_pins[] = {
942 /* CANFD0_TX, CANFD0_RX */
943 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
944};
945static const unsigned int canfd0_data_b_mux[] = {
946 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
947};
948
949/* - CANFD1 ----------------------------------------------------------------- */
950static const unsigned int canfd1_data_pins[] = {
951 /* CANFD1_TX, CANFD1_RX */
952 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
953};
954static const unsigned int canfd1_data_mux[] = {
955 CANFD1_TX_MARK, CANFD1_RX_MARK,
956};
957
958/* - CANFD Clock ------------------------------------------------------------ */
959static const unsigned int canfd_clk_a_pins[] = {
960 /* CANFD_CLK */
961 RCAR_GP_PIN(1, 25),
962};
963static const unsigned int canfd_clk_a_mux[] = {
964 CANFD_CLK_A_MARK,
965};
966static const unsigned int canfd_clk_b_pins[] = {
967 /* CANFD_CLK */
968 RCAR_GP_PIN(3, 8),
969};
970static const unsigned int canfd_clk_b_mux[] = {
971 CANFD_CLK_B_MARK,
972};
973
974/* - DU --------------------------------------------------------------------- */
975static const unsigned int du_rgb666_pins[] = {
976 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
977 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
978 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
979 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
980 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
981 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
982 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
983};
984static const unsigned int du_rgb666_mux[] = {
985 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
986 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
987 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
988 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
989 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
990 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
991};
992static const unsigned int du_rgb888_pins[] = {
993 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
994 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
995 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
996 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
997 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
998 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
999 RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1000 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
1001 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
1002 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
1003};
1004static const unsigned int du_rgb888_mux[] = {
1005 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
1006 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
1007 DU_DR1_MARK, DU_DR0_MARK,
1008 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
1009 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
1010 DU_DG1_MARK, DU_DG0_MARK,
1011 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
1012 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
1013 DU_DB1_MARK, DU_DB0_MARK,
1014};
1015static const unsigned int du_clk_out_pins[] = {
1016 /* DU_DOTCLKOUT */
1017 RCAR_GP_PIN(0, 18),
1018};
1019static const unsigned int du_clk_out_mux[] = {
1020 DU_DOTCLKOUT_MARK,
1021};
1022static const unsigned int du_sync_pins[] = {
1023 /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
1024 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1025};
1026static const unsigned int du_sync_mux[] = {
1027 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1028};
1029static const unsigned int du_oddf_pins[] = {
1030 /* DU_EXODDF/DU_ODDF/DISP/CDE */
1031 RCAR_GP_PIN(0, 21),
1032};
1033static const unsigned int du_oddf_mux[] = {
1034 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1035};
1036static const unsigned int du_cde_pins[] = {
1037 /* DU_CDE */
1038 RCAR_GP_PIN(1, 22),
1039};
1040static const unsigned int du_cde_mux[] = {
1041 DU_CDE_MARK,
1042};
1043static const unsigned int du_disp_pins[] = {
1044 /* DU_DISP */
1045 RCAR_GP_PIN(1, 21),
1046};
1047static const unsigned int du_disp_mux[] = {
1048 DU_DISP_MARK,
1049};
1050
1051/* - GETHER ----------------------------------------------------------------- */
1052static const unsigned int gether_link_a_pins[] = {
1053 /* GETHER_LINK */
1054 RCAR_GP_PIN(4, 24),
1055};
1056static const unsigned int gether_link_a_mux[] = {
1057 GETHER_LINK_A_MARK,
1058};
1059static const unsigned int gether_phy_int_a_pins[] = {
1060 /* GETHER_PHY_INT */
1061 RCAR_GP_PIN(4, 23),
1062};
1063static const unsigned int gether_phy_int_a_mux[] = {
1064 GETHER_PHY_INT_A_MARK,
1065};
1066static const unsigned int gether_mdio_a_pins[] = {
1067 /* GETHER_MDC, GETHER_MDIO */
1068 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1069};
1070static const unsigned int gether_mdio_a_mux[] = {
1071 GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
1072};
1073static const unsigned int gether_link_b_pins[] = {
1074 /* GETHER_LINK */
1075 RCAR_GP_PIN(0, 18),
1076};
1077static const unsigned int gether_link_b_mux[] = {
1078 GETHER_LINK_B_MARK,
1079};
1080static const unsigned int gether_phy_int_b_pins[] = {
1081 /* GETHER_PHY_INT */
1082 RCAR_GP_PIN(0, 19),
1083};
1084static const unsigned int gether_phy_int_b_mux[] = {
1085 GETHER_PHY_INT_B_MARK,
1086};
1087static const unsigned int gether_mdio_b_mux[] = {
1088 GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
1089};
1090static const unsigned int gether_mdio_b_pins[] = {
1091 /* GETHER_MDC, GETHER_MDIO */
1092 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1093};
1094static const unsigned int gether_magic_pins[] = {
1095 /* GETHER_MAGIC */
1096 RCAR_GP_PIN(4, 22),
1097};
1098static const unsigned int gether_magic_mux[] = {
1099 GETHER_MAGIC_MARK,
1100};
1101static const unsigned int gether_rgmii_pins[] = {
1102 /*
1103 * GETHER_TX_CTL, GETHER_TXC,
1104 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
1105 * GETHER_RX_CTL, GETHER_RXC,
1106 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
1107 */
1108 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1109 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1110 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1111 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1112 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1113 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1114};
1115static const unsigned int gether_rgmii_mux[] = {
1116 GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
1117 GETHER_TD0_MARK, GETHER_TD1_MARK,
1118 GETHER_TD2_MARK, GETHER_TD3_MARK,
1119 GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
1120 GETHER_RD0_MARK, AVB_RD1_MARK,
1121 GETHER_RD2_MARK, AVB_RD3_MARK,
1122};
1123static const unsigned int gether_txcrefclk_pins[] = {
1124 /* GETHER_TXCREFCLK */
1125 RCAR_GP_PIN(4, 18),
1126};
1127static const unsigned int gether_txcrefclk_mux[] = {
1128 GETHER_TXCREFCLK_MARK,
1129};
1130static const unsigned int gether_txcrefclk_mega_pins[] = {
1131 /* GETHER_TXCREFCLK_MEGA */
1132 RCAR_GP_PIN(4, 19),
1133};
1134static const unsigned int gether_txcrefclk_mega_mux[] = {
1135 GETHER_TXCREFCLK_MEGA_MARK,
1136};
1137static const unsigned int gether_rmii_pins[] = {
1138 /*
1139 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
1140 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
1141 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
1142 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
1143 */
1144 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1145 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1146 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1147 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
1148};
1149static const unsigned int gether_rmii_mux[] = {
1150 GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
1151 GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
1152 GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
1153 GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
1154};
1155
1156/* - HSCIF0 ----------------------------------------------------------------- */
1157static const unsigned int hscif0_data_a_pins[] = {
1158 /* HRX0, HTX0 */
1159 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
1160};
1161static const unsigned int hscif0_data_a_mux[] = {
1162 HRX0_A_MARK, HTX0_A_MARK,
1163};
1164static const unsigned int hscif0_clk_a_pins[] = {
1165 /* HSCK0 */
1166 RCAR_GP_PIN(0, 12),
1167};
1168static const unsigned int hscif0_clk_a_mux[] = {
1169 HSCK0_A_MARK,
1170};
1171static const unsigned int hscif0_ctrl_a_pins[] = {
1172 /* HRTS0#, HCTS0# */
1173 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1174};
1175static const unsigned int hscif0_ctrl_a_mux[] = {
1176 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1177};
1178static const unsigned int hscif0_data_b_pins[] = {
1179 /* HRX0, HTX0 */
1180 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1181};
1182static const unsigned int hscif0_data_b_mux[] = {
1183 HRX0_B_MARK, HTX0_B_MARK,
1184};
1185static const unsigned int hscif0_clk_b_pins[] = {
1186 /* HSCK0 */
1187 RCAR_GP_PIN(4, 1),
1188};
1189static const unsigned int hscif0_clk_b_mux[] = {
1190 HSCK0_B_MARK,
1191};
1192static const unsigned int hscif0_ctrl_b_pins[] = {
1193 /* HRTS0#, HCTS0# */
1194 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1195};
1196static const unsigned int hscif0_ctrl_b_mux[] = {
1197 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1198};
1199
1200/* - HSCIF1 ----------------------------------------------------------------- */
1201static const unsigned int hscif1_data_pins[] = {
1202 /* HRX1, HTX1 */
1203 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1204};
1205static const unsigned int hscif1_data_mux[] = {
1206 HRX1_MARK, HTX1_MARK,
1207};
1208static const unsigned int hscif1_clk_pins[] = {
1209 /* HSCK1 */
1210 RCAR_GP_PIN(2, 7),
1211};
1212static const unsigned int hscif1_clk_mux[] = {
1213 HSCK1_MARK,
1214};
1215static const unsigned int hscif1_ctrl_pins[] = {
1216 /* HRTS1#, HCTS1# */
1217 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1218};
1219static const unsigned int hscif1_ctrl_mux[] = {
1220 HRTS1_N_MARK, HCTS1_N_MARK,
1221};
1222
1223/* - HSCIF2 ----------------------------------------------------------------- */
1224static const unsigned int hscif2_data_pins[] = {
1225 /* HRX2, HTX2 */
1226 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1227};
1228static const unsigned int hscif2_data_mux[] = {
1229 HRX2_MARK, HTX2_MARK,
1230};
1231static const unsigned int hscif2_clk_pins[] = {
1232 /* HSCK2 */
1233 RCAR_GP_PIN(2, 12),
1234};
1235static const unsigned int hscif2_clk_mux[] = {
1236 HSCK2_MARK,
1237};
1238static const unsigned int hscif2_ctrl_pins[] = {
1239 /* HRTS2#, HCTS2# */
1240 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1241};
1242static const unsigned int hscif2_ctrl_mux[] = {
1243 HRTS2_N_MARK, HCTS2_N_MARK,
1244};
1245
1246/* - HSCIF3 ----------------------------------------------------------------- */
1247static const unsigned int hscif3_data_pins[] = {
1248 /* HRX3, HTX3 */
1249 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1250};
1251static const unsigned int hscif3_data_mux[] = {
1252 HRX3_MARK, HTX3_MARK,
1253};
1254static const unsigned int hscif3_clk_pins[] = {
1255 /* HSCK3 */
1256 RCAR_GP_PIN(2, 0),
1257};
1258static const unsigned int hscif3_clk_mux[] = {
1259 HSCK3_MARK,
1260};
1261static const unsigned int hscif3_ctrl_pins[] = {
1262 /* HRTS3#, HCTS3# */
1263 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1264};
1265static const unsigned int hscif3_ctrl_mux[] = {
1266 HRTS3_N_MARK, HCTS3_N_MARK,
1267};
1268
1269/* - I2C0 ------------------------------------------------------------------- */
1270static const unsigned int i2c0_pins[] = {
1271 /* SDA0, SCL0 */
1272 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1273};
1274static const unsigned int i2c0_mux[] = {
1275 SDA0_MARK, SCL0_MARK,
1276};
1277
1278/* - I2C1 ------------------------------------------------------------------- */
1279static const unsigned int i2c1_pins[] = {
1280 /* SDA1, SCL1 */
1281 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1282};
1283static const unsigned int i2c1_mux[] = {
1284 SDA1_MARK, SCL1_MARK,
1285};
1286
1287/* - I2C2 ------------------------------------------------------------------- */
1288static const unsigned int i2c2_pins[] = {
1289 /* SDA2, SCL2 */
1290 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1291};
1292static const unsigned int i2c2_mux[] = {
1293 SDA2_MARK, SCL2_MARK,
1294};
1295
1296/* - I2C3 ------------------------------------------------------------------- */
1297static const unsigned int i2c3_pins[] = {
1298 /* SDA3, SCL3 */
1299 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1300};
1301static const unsigned int i2c3_mux[] = {
1302 SDA3_MARK, SCL3_MARK,
1303};
1304
1305/* - I2C4 ------------------------------------------------------------------- */
1306static const unsigned int i2c4_pins[] = {
1307 /* SDA4, SCL4 */
1308 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1309};
1310static const unsigned int i2c4_mux[] = {
1311 SDA4_MARK, SCL4_MARK,
1312};
1313
1314/* - I2C5 ------------------------------------------------------------------- */
1315static const unsigned int i2c5_pins[] = {
1316 /* SDA5, SCL5 */
1317 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1318};
1319static const unsigned int i2c5_mux[] = {
1320 SDA5_MARK, SCL5_MARK,
1321};
1322
1323/* - INTC-EX ---------------------------------------------------------------- */
1324static const unsigned int intc_ex_irq0_pins[] = {
1325 /* IRQ0 */
1326 RCAR_GP_PIN(1, 0),
1327};
1328static const unsigned int intc_ex_irq0_mux[] = {
1329 IRQ0_MARK,
1330};
1331static const unsigned int intc_ex_irq1_pins[] = {
1332 /* IRQ1 */
1333 RCAR_GP_PIN(0, 12),
1334};
1335static const unsigned int intc_ex_irq1_mux[] = {
1336 IRQ1_MARK,
1337};
1338static const unsigned int intc_ex_irq2_pins[] = {
1339 /* IRQ2 */
1340 RCAR_GP_PIN(0, 13),
1341};
1342static const unsigned int intc_ex_irq2_mux[] = {
1343 IRQ2_MARK,
1344};
1345static const unsigned int intc_ex_irq3_pins[] = {
1346 /* IRQ3 */
1347 RCAR_GP_PIN(0, 14),
1348};
1349static const unsigned int intc_ex_irq3_mux[] = {
1350 IRQ3_MARK,
1351};
1352static const unsigned int intc_ex_irq4_pins[] = {
1353 /* IRQ4 */
1354 RCAR_GP_PIN(2, 17),
1355};
1356static const unsigned int intc_ex_irq4_mux[] = {
1357 IRQ4_MARK,
1358};
1359static const unsigned int intc_ex_irq5_pins[] = {
1360 /* IRQ5 */
1361 RCAR_GP_PIN(2, 18),
1362};
1363static const unsigned int intc_ex_irq5_mux[] = {
1364 IRQ5_MARK,
1365};
1366
1367/* - MMC -------------------------------------------------------------------- */
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1368static const unsigned int mmc_data_pins[] = {
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1369 /* MMC_D[0:7] */
1370 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1371 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1372 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1373 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1374};
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1375static const unsigned int mmc_data_mux[] = {
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1376 MMC_D0_MARK, MMC_D1_MARK,
1377 MMC_D2_MARK, MMC_D3_MARK,
1378 MMC_D4_MARK, MMC_D5_MARK,
1379 MMC_D6_MARK, MMC_D7_MARK,
1380};
1381static const unsigned int mmc_ctrl_pins[] = {
1382 /* MMC_CLK, MMC_CMD */
1383 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
1384};
1385static const unsigned int mmc_ctrl_mux[] = {
1386 MMC_CLK_MARK, MMC_CMD_MARK,
1387};
1388static const unsigned int mmc_cd_pins[] = {
1389 /* MMC_CD */
1390 RCAR_GP_PIN(3, 5),
1391};
1392static const unsigned int mmc_cd_mux[] = {
1393 MMC_CD_MARK,
1394};
1395static const unsigned int mmc_wp_pins[] = {
1396 /* MMC_WP */
1397 RCAR_GP_PIN(3, 4),
1398};
1399static const unsigned int mmc_wp_mux[] = {
1400 MMC_WP_MARK,
1401};
1402static const unsigned int mmc_ds_pins[] = {
1403 /* MMC_DS */
1404 RCAR_GP_PIN(3, 6),
1405};
1406static const unsigned int mmc_ds_mux[] = {
1407 MMC_DS_MARK,
1408};
1409
1410/* - MSIOF0 ----------------------------------------------------------------- */
1411static const unsigned int msiof0_clk_pins[] = {
1412 /* MSIOF0_SCK */
1413 RCAR_GP_PIN(2, 21),
1414};
1415static const unsigned int msiof0_clk_mux[] = {
1416 MSIOF0_SCK_MARK,
1417};
1418static const unsigned int msiof0_sync_pins[] = {
1419 /* MSIOF0_SYNC */
1420 RCAR_GP_PIN(2, 22),
1421};
1422static const unsigned int msiof0_sync_mux[] = {
1423 MSIOF0_SYNC_MARK,
1424};
1425static const unsigned int msiof0_ss1_pins[] = {
1426 /* MSIOF0_SS1 */
1427 RCAR_GP_PIN(2, 23),
1428};
1429static const unsigned int msiof0_ss1_mux[] = {
1430 MSIOF0_SS1_MARK,
1431};
1432static const unsigned int msiof0_ss2_pins[] = {
1433 /* MSIOF0_SS2 */
1434 RCAR_GP_PIN(2, 24),
1435};
1436static const unsigned int msiof0_ss2_mux[] = {
1437 MSIOF0_SS2_MARK,
1438};
1439static const unsigned int msiof0_txd_pins[] = {
1440 /* MSIOF0_TXD */
1441 RCAR_GP_PIN(2, 20),
1442};
1443static const unsigned int msiof0_txd_mux[] = {
1444 MSIOF0_TXD_MARK,
1445};
1446static const unsigned int msiof0_rxd_pins[] = {
1447 /* MSIOF0_RXD */
1448 RCAR_GP_PIN(2, 19),
1449};
1450static const unsigned int msiof0_rxd_mux[] = {
1451 MSIOF0_RXD_MARK,
1452};
1453
1454/* - MSIOF1 ----------------------------------------------------------------- */
1455static const unsigned int msiof1_clk_pins[] = {
1456 /* MSIOF1_SCK */
1457 RCAR_GP_PIN(3, 2),
1458};
1459static const unsigned int msiof1_clk_mux[] = {
1460 MSIOF1_SCK_MARK,
1461};
1462static const unsigned int msiof1_sync_pins[] = {
1463 /* MSIOF1_SYNC */
1464 RCAR_GP_PIN(3, 3),
1465};
1466static const unsigned int msiof1_sync_mux[] = {
1467 MSIOF1_SYNC_MARK,
1468};
1469static const unsigned int msiof1_ss1_pins[] = {
1470 /* MSIOF1_SS1 */
1471 RCAR_GP_PIN(3, 4),
1472};
1473static const unsigned int msiof1_ss1_mux[] = {
1474 MSIOF1_SS1_MARK,
1475};
1476static const unsigned int msiof1_ss2_pins[] = {
1477 /* MSIOF1_SS2 */
1478 RCAR_GP_PIN(3, 5),
1479};
1480static const unsigned int msiof1_ss2_mux[] = {
1481 MSIOF1_SS2_MARK,
1482};
1483static const unsigned int msiof1_txd_pins[] = {
1484 /* MSIOF1_TXD */
1485 RCAR_GP_PIN(3, 1),
1486};
1487static const unsigned int msiof1_txd_mux[] = {
1488 MSIOF1_TXD_MARK,
1489};
1490static const unsigned int msiof1_rxd_pins[] = {
1491 /* MSIOF1_RXD */
1492 RCAR_GP_PIN(3, 0),
1493};
1494static const unsigned int msiof1_rxd_mux[] = {
1495 MSIOF1_RXD_MARK,
1496};
1497
1498/* - MSIOF2 ----------------------------------------------------------------- */
1499static const unsigned int msiof2_clk_pins[] = {
1500 /* MSIOF2_SCK */
1501 RCAR_GP_PIN(2, 0),
1502};
1503static const unsigned int msiof2_clk_mux[] = {
1504 MSIOF2_SCK_MARK,
1505};
1506static const unsigned int msiof2_sync_pins[] = {
1507 /* MSIOF2_SYNC */
1508 RCAR_GP_PIN(2, 3),
1509};
1510static const unsigned int msiof2_sync_mux[] = {
1511 MSIOF2_SYNC_MARK,
1512};
1513static const unsigned int msiof2_ss1_pins[] = {
1514 /* MSIOF2_SS1 */
1515 RCAR_GP_PIN(2, 4),
1516};
1517static const unsigned int msiof2_ss1_mux[] = {
1518 MSIOF2_SS1_MARK,
1519};
1520static const unsigned int msiof2_ss2_pins[] = {
1521 /* MSIOF2_SS2 */
1522 RCAR_GP_PIN(2, 5),
1523};
1524static const unsigned int msiof2_ss2_mux[] = {
1525 MSIOF2_SS2_MARK,
1526};
1527static const unsigned int msiof2_txd_pins[] = {
1528 /* MSIOF2_TXD */
1529 RCAR_GP_PIN(2, 2),
1530};
1531static const unsigned int msiof2_txd_mux[] = {
1532 MSIOF2_TXD_MARK,
1533};
1534static const unsigned int msiof2_rxd_pins[] = {
1535 /* MSIOF2_RXD */
1536 RCAR_GP_PIN(2, 1),
1537};
1538static const unsigned int msiof2_rxd_mux[] = {
1539 MSIOF2_RXD_MARK,
1540};
1541
1542/* - MSIOF3 ----------------------------------------------------------------- */
1543static const unsigned int msiof3_clk_pins[] = {
1544 /* MSIOF3_SCK */
1545 RCAR_GP_PIN(0, 20),
1546};
1547static const unsigned int msiof3_clk_mux[] = {
1548 MSIOF3_SCK_MARK,
1549};
1550static const unsigned int msiof3_sync_pins[] = {
1551 /* MSIOF3_SYNC */
1552 RCAR_GP_PIN(0, 21),
1553};
1554static const unsigned int msiof3_sync_mux[] = {
1555 MSIOF3_SYNC_MARK,
1556};
1557static const unsigned int msiof3_ss1_pins[] = {
1558 /* MSIOF3_SS1 */
1559 RCAR_GP_PIN(0, 18),
1560};
1561static const unsigned int msiof3_ss1_mux[] = {
1562 MSIOF3_SS1_MARK,
1563};
1564static const unsigned int msiof3_ss2_pins[] = {
1565 /* MSIOF3_SS2 */
1566 RCAR_GP_PIN(0, 19),
1567};
1568static const unsigned int msiof3_ss2_mux[] = {
1569 MSIOF3_SS2_MARK,
1570};
1571static const unsigned int msiof3_txd_pins[] = {
1572 /* MSIOF3_TXD */
1573 RCAR_GP_PIN(0, 17),
1574};
1575static const unsigned int msiof3_txd_mux[] = {
1576 MSIOF3_TXD_MARK,
1577};
1578static const unsigned int msiof3_rxd_pins[] = {
1579 /* MSIOF3_RXD */
1580 RCAR_GP_PIN(0, 16),
1581};
1582static const unsigned int msiof3_rxd_mux[] = {
1583 MSIOF3_RXD_MARK,
1584};
1585
1586/* - PWM0 ------------------------------------------------------------------- */
1587static const unsigned int pwm0_a_pins[] = {
1588 /* PWM0 */
1589 RCAR_GP_PIN(0, 15),
1590};
1591static const unsigned int pwm0_a_mux[] = {
1592 PWM0_A_MARK,
1593};
1594static const unsigned int pwm0_b_pins[] = {
1595 /* PWM0 */
1596 RCAR_GP_PIN(1, 21),
1597};
1598static const unsigned int pwm0_b_mux[] = {
1599 PWM0_B_MARK,
1600};
1601
1602/* - PWM1 ------------------------------------------------------------------- */
1603static const unsigned int pwm1_a_pins[] = {
1604 /* PWM1 */
1605 RCAR_GP_PIN(2, 13),
1606};
1607static const unsigned int pwm1_a_mux[] = {
1608 PWM1_A_MARK,
1609};
1610static const unsigned int pwm1_b_pins[] = {
1611 /* PWM1 */
1612 RCAR_GP_PIN(1, 22),
1613};
1614static const unsigned int pwm1_b_mux[] = {
1615 PWM1_B_MARK,
1616};
1617
1618/* - PWM2 ------------------------------------------------------------------- */
1619static const unsigned int pwm2_a_pins[] = {
1620 /* PWM2 */
1621 RCAR_GP_PIN(2, 14),
1622};
1623static const unsigned int pwm2_a_mux[] = {
1624 PWM2_A_MARK,
1625};
1626static const unsigned int pwm2_b_pins[] = {
1627 /* PWM2 */
1628 RCAR_GP_PIN(1, 23),
1629};
1630static const unsigned int pwm2_b_mux[] = {
1631 PWM2_B_MARK,
1632};
1633
1634/* - PWM3 ------------------------------------------------------------------- */
1635static const unsigned int pwm3_a_pins[] = {
1636 /* PWM3 */
1637 RCAR_GP_PIN(2, 15),
1638};
1639static const unsigned int pwm3_a_mux[] = {
1640 PWM3_A_MARK,
1641};
1642static const unsigned int pwm3_b_pins[] = {
1643 /* PWM3 */
1644 RCAR_GP_PIN(1, 24),
1645};
1646static const unsigned int pwm3_b_mux[] = {
1647 PWM3_B_MARK,
1648};
1649
1650/* - PWM4 ------------------------------------------------------------------- */
1651static const unsigned int pwm4_a_pins[] = {
1652 /* PWM4 */
1653 RCAR_GP_PIN(2, 16),
1654};
1655static const unsigned int pwm4_a_mux[] = {
1656 PWM4_A_MARK,
1657};
1658static const unsigned int pwm4_b_pins[] = {
1659 /* PWM4 */
1660 RCAR_GP_PIN(1, 25),
1661};
1662static const unsigned int pwm4_b_mux[] = {
1663 PWM4_B_MARK,
1664};
1665
1666/* - QSPI0 ------------------------------------------------------------------ */
1667static const unsigned int qspi0_ctrl_pins[] = {
1668 /* SPCLK, SSL */
1669 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1670};
1671static const unsigned int qspi0_ctrl_mux[] = {
1672 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1673};
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1674
1675/* - QSPI1 ------------------------------------------------------------------ */
1676static const unsigned int qspi1_ctrl_pins[] = {
1677 /* SPCLK, SSL */
1678 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1679};
1680static const unsigned int qspi1_ctrl_mux[] = {
1681 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1682};
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1683
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1684/* - RPC -------------------------------------------------------------------- */
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1685static const unsigned int rpc_clk_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1686 /* Octal-SPI flash: C/SCLK */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1687 /* HyperFlash: CK, CK# */
1688 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1689};
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1690static const unsigned int rpc_clk_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1691 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1692};
1693static const unsigned int rpc_ctrl_pins[] = {
1694 /* Octal-SPI flash: S#/CS, DQS */
1695 /* HyperFlash: CS#, RDS */
1696 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1697};
1698static const unsigned int rpc_ctrl_mux[] = {
1699 QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1700};
1701static const unsigned int rpc_data_pins[] = {
1702 /* DQ[0:7] */
1703 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1704 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1705 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1706 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1707};
1708static const unsigned int rpc_data_mux[] = {
1709 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1710 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1711 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1712 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1713};
1714static const unsigned int rpc_reset_pins[] = {
1715 /* RPC_RESET# */
1716 RCAR_GP_PIN(5, 12),
1717};
1718static const unsigned int rpc_reset_mux[] = {
1719 RPC_RESET_N_MARK,
1720};
1721static const unsigned int rpc_int_pins[] = {
1722 /* RPC_INT# */
1723 RCAR_GP_PIN(5, 14),
1724};
1725static const unsigned int rpc_int_mux[] = {
1726 RPC_INT_N_MARK,
1727};
1728static const unsigned int rpc_wp_pins[] = {
1729 /* RPC_WP# */
1730 RCAR_GP_PIN(5, 13),
1731};
1732static const unsigned int rpc_wp_mux[] = {
1733 RPC_WP_N_MARK,
1734};
1735
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1736/* - SCIF0 ------------------------------------------------------------------ */
1737static const unsigned int scif0_data_pins[] = {
1738 /* RX0, TX0 */
1739 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1740};
1741static const unsigned int scif0_data_mux[] = {
1742 RX0_MARK, TX0_MARK,
1743};
1744static const unsigned int scif0_clk_pins[] = {
1745 /* SCK0 */
1746 RCAR_GP_PIN(4, 1),
1747};
1748static const unsigned int scif0_clk_mux[] = {
1749 SCK0_MARK,
1750};
1751static const unsigned int scif0_ctrl_pins[] = {
1752 /* RTS0#, CTS0# */
1753 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1754};
1755static const unsigned int scif0_ctrl_mux[] = {
1756 RTS0_N_MARK, CTS0_N_MARK,
1757};
1758
1759/* - SCIF1 ------------------------------------------------------------------ */
1760static const unsigned int scif1_data_a_pins[] = {
1761 /* RX1, TX1 */
1762 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1763};
1764static const unsigned int scif1_data_a_mux[] = {
1765 RX1_A_MARK, TX1_A_MARK,
1766};
1767static const unsigned int scif1_clk_pins[] = {
1768 /* SCK1 */
1769 RCAR_GP_PIN(2, 5),
1770};
1771static const unsigned int scif1_clk_mux[] = {
1772 SCK1_MARK,
1773};
1774static const unsigned int scif1_ctrl_pins[] = {
1775 /* RTS1#, CTS1# */
1776 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1777};
1778static const unsigned int scif1_ctrl_mux[] = {
1779 RTS1_N_MARK, CTS1_N_MARK,
1780};
1781static const unsigned int scif1_data_b_pins[] = {
1782 /* RX1, TX1 */
1783 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1784};
1785static const unsigned int scif1_data_b_mux[] = {
1786 RX1_B_MARK, TX1_B_MARK,
1787};
1788
1789/* - SCIF3 ------------------------------------------------------------------ */
1790static const unsigned int scif3_data_pins[] = {
1791 /* RX3, TX3 */
1792 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1793};
1794static const unsigned int scif3_data_mux[] = {
1795 RX3_MARK, TX3_MARK,
1796};
1797static const unsigned int scif3_clk_pins[] = {
1798 /* SCK3 */
1799 RCAR_GP_PIN(2, 0),
1800};
1801static const unsigned int scif3_clk_mux[] = {
1802 SCK3_MARK,
1803};
1804static const unsigned int scif3_ctrl_pins[] = {
1805 /* RTS3#, CTS3# */
1806 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1807};
1808static const unsigned int scif3_ctrl_mux[] = {
1809 RTS3_N_MARK, CTS3_N_MARK,
1810};
1811
1812/* - SCIF4 ------------------------------------------------------------------ */
1813static const unsigned int scif4_data_pins[] = {
1814 /* RX4, TX4 */
1815 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1816};
1817static const unsigned int scif4_data_mux[] = {
1818 RX4_MARK, TX4_MARK,
1819};
1820static const unsigned int scif4_clk_pins[] = {
1821 /* SCK4 */
1822 RCAR_GP_PIN(0, 0),
1823};
1824static const unsigned int scif4_clk_mux[] = {
1825 SCK4_MARK,
1826};
1827static const unsigned int scif4_ctrl_pins[] = {
1828 /* RTS4#, CTS4# */
1829 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1830};
1831static const unsigned int scif4_ctrl_mux[] = {
1832 RTS4_N_MARK, CTS4_N_MARK,
1833};
1834
1835/* - SCIF Clock ------------------------------------------------------------- */
1836static const unsigned int scif_clk_a_pins[] = {
1837 /* SCIF_CLK */
1838 RCAR_GP_PIN(0, 10),
1839};
1840static const unsigned int scif_clk_a_mux[] = {
1841 SCIF_CLK_A_MARK,
1842};
1843static const unsigned int scif_clk_b_pins[] = {
1844 /* SCIF_CLK */
1845 RCAR_GP_PIN(1, 25),
1846};
1847static const unsigned int scif_clk_b_mux[] = {
1848 SCIF_CLK_B_MARK,
1849};
1850
1851/* - TMU -------------------------------------------------------------------- */
1852static const unsigned int tmu_tclk1_a_pins[] = {
1853 /* TCLK1 */
1854 RCAR_GP_PIN(3, 13),
1855};
1856static const unsigned int tmu_tclk1_a_mux[] = {
1857 TCLK1_A_MARK,
1858};
1859static const unsigned int tmu_tclk1_b_pins[] = {
1860 /* TCLK1 */
1861 RCAR_GP_PIN(1, 23),
1862};
1863static const unsigned int tmu_tclk1_b_mux[] = {
1864 TCLK1_B_MARK,
1865};
1866static const unsigned int tmu_tclk2_a_pins[] = {
1867 /* TCLK2 */
1868 RCAR_GP_PIN(3, 14),
1869};
1870static const unsigned int tmu_tclk2_a_mux[] = {
1871 TCLK2_A_MARK,
1872};
1873static const unsigned int tmu_tclk2_b_pins[] = {
1874 /* TCLK2 */
1875 RCAR_GP_PIN(1, 24),
1876};
1877static const unsigned int tmu_tclk2_b_mux[] = {
1878 TCLK2_B_MARK,
1879};
1880
1881/* - TPU ------------------------------------------------------------------- */
1882static const unsigned int tpu_to0_pins[] = {
1883 /* TPU0TO0 */
1884 RCAR_GP_PIN(1, 19),
1885};
1886static const unsigned int tpu_to0_mux[] = {
1887 TPU0TO0_MARK,
1888};
1889static const unsigned int tpu_to1_pins[] = {
1890 /* TPU0TO1 */
1891 RCAR_GP_PIN(1, 20),
1892};
1893static const unsigned int tpu_to1_mux[] = {
1894 TPU0TO1_MARK,
1895};
1896static const unsigned int tpu_to2_pins[] = {
1897 /* TPU0TO2 */
1898 RCAR_GP_PIN(4, 2),
1899};
1900static const unsigned int tpu_to2_mux[] = {
1901 TPU0TO2_MARK,
1902};
1903static const unsigned int tpu_to3_pins[] = {
1904 /* TPU0TO3 */
1905 RCAR_GP_PIN(4, 3),
1906};
1907static const unsigned int tpu_to3_mux[] = {
1908 TPU0TO3_MARK,
1909};
1910
1911/* - VIN0 ------------------------------------------------------------------- */
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1912static const unsigned int vin0_data_pins[] = {
1913 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1914 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1915 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1916 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1917 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1918 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1919 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1920 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1921 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1922 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1923 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1924 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1925};
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1926static const unsigned int vin0_data_mux[] = {
1927 VI0_DATA0_MARK, VI0_DATA1_MARK,
1928 VI0_DATA2_MARK, VI0_DATA3_MARK,
1929 VI0_DATA4_MARK, VI0_DATA5_MARK,
1930 VI0_DATA6_MARK, VI0_DATA7_MARK,
1931 VI0_DATA8_MARK, VI0_DATA9_MARK,
1932 VI0_DATA10_MARK, VI0_DATA11_MARK,
1933 VI0_DATA12_MARK, VI0_DATA13_MARK,
1934 VI0_DATA14_MARK, VI0_DATA15_MARK,
1935 VI0_DATA16_MARK, VI0_DATA17_MARK,
1936 VI0_DATA18_MARK, VI0_DATA19_MARK,
1937 VI0_DATA20_MARK, VI0_DATA21_MARK,
1938 VI0_DATA22_MARK, VI0_DATA23_MARK,
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1939};
1940static const unsigned int vin0_data18_pins[] = {
1941 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1942 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1943 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1944 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1945 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1946 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1947 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1948 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1949 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1950};
1951static const unsigned int vin0_data18_mux[] = {
1952 VI0_DATA2_MARK, VI0_DATA3_MARK,
1953 VI0_DATA4_MARK, VI0_DATA5_MARK,
1954 VI0_DATA6_MARK, VI0_DATA7_MARK,
1955 VI0_DATA10_MARK, VI0_DATA11_MARK,
1956 VI0_DATA12_MARK, VI0_DATA13_MARK,
1957 VI0_DATA14_MARK, VI0_DATA15_MARK,
1958 VI0_DATA18_MARK, VI0_DATA19_MARK,
1959 VI0_DATA20_MARK, VI0_DATA21_MARK,
1960 VI0_DATA22_MARK, VI0_DATA23_MARK,
1961};
1962static const unsigned int vin0_sync_pins[] = {
1963 /* VI0_VSYNC#, VI0_HSYNC# */
1964 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1965};
1966static const unsigned int vin0_sync_mux[] = {
1967 VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
1968};
1969static const unsigned int vin0_field_pins[] = {
1970 /* VI0_FIELD */
1971 RCAR_GP_PIN(2, 16),
1972};
1973static const unsigned int vin0_field_mux[] = {
1974 VI0_FIELD_MARK,
1975};
1976static const unsigned int vin0_clkenb_pins[] = {
1977 /* VI0_CLKENB */
1978 RCAR_GP_PIN(2, 1),
1979};
1980static const unsigned int vin0_clkenb_mux[] = {
1981 VI0_CLKENB_MARK,
1982};
1983static const unsigned int vin0_clk_pins[] = {
1984 /* VI0_CLK */
1985 RCAR_GP_PIN(2, 0),
1986};
1987static const unsigned int vin0_clk_mux[] = {
1988 VI0_CLK_MARK,
1989};
1990
1991/* - VIN1 ------------------------------------------------------------------- */
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]1992static const unsigned int vin1_data_pins[] = {
1993 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1994 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1995 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1996 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1997 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1998 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]1999};
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2000static const unsigned int vin1_data_mux[] = {
2001 VI1_DATA0_MARK, VI1_DATA1_MARK,
2002 VI1_DATA2_MARK, VI1_DATA3_MARK,
2003 VI1_DATA4_MARK, VI1_DATA5_MARK,
2004 VI1_DATA6_MARK, VI1_DATA7_MARK,
2005 VI1_DATA8_MARK, VI1_DATA9_MARK,
2006 VI1_DATA10_MARK, VI1_DATA11_MARK,
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2007};
2008static const unsigned int vin1_sync_pins[] = {
2009 /* VI1_VSYNC#, VI1_HSYNC# */
2010 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2011};
2012static const unsigned int vin1_sync_mux[] = {
2013 VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
2014};
2015static const unsigned int vin1_field_pins[] = {
2016 /* VI1_FIELD */
2017 RCAR_GP_PIN(3, 16),
2018};
2019static const unsigned int vin1_field_mux[] = {
2020 VI1_FIELD_MARK,
2021};
2022static const unsigned int vin1_clkenb_pins[] = {
2023 /* VI1_CLKENB */
2024 RCAR_GP_PIN(3, 1),
2025};
2026static const unsigned int vin1_clkenb_mux[] = {
2027 VI1_CLKENB_MARK,
2028};
2029static const unsigned int vin1_clk_pins[] = {
2030 /* VI1_CLK */
2031 RCAR_GP_PIN(3, 0),
2032};
2033static const unsigned int vin1_clk_mux[] = {
2034 VI1_CLK_MARK,
2035};
2036
2037static const struct sh_pfc_pin_group pinmux_groups[] = {
2038 SH_PFC_PIN_GROUP(avb_link),
2039 SH_PFC_PIN_GROUP(avb_magic),
2040 SH_PFC_PIN_GROUP(avb_phy_int),
2041 SH_PFC_PIN_GROUP(avb_mdio),
2042 SH_PFC_PIN_GROUP(avb_rgmii),
2043 SH_PFC_PIN_GROUP(avb_txcrefclk),
2044 SH_PFC_PIN_GROUP(avb_avtp_pps),
2045 SH_PFC_PIN_GROUP(avb_avtp_capture),
2046 SH_PFC_PIN_GROUP(avb_avtp_match),
2047 SH_PFC_PIN_GROUP(canfd0_data_a),
2048 SH_PFC_PIN_GROUP(canfd0_data_b),
2049 SH_PFC_PIN_GROUP(canfd1_data),
2050 SH_PFC_PIN_GROUP(canfd_clk_a),
2051 SH_PFC_PIN_GROUP(canfd_clk_b),
2052 SH_PFC_PIN_GROUP(du_rgb666),
2053 SH_PFC_PIN_GROUP(du_rgb888),
2054 SH_PFC_PIN_GROUP(du_clk_out),
2055 SH_PFC_PIN_GROUP(du_sync),
2056 SH_PFC_PIN_GROUP(du_oddf),
2057 SH_PFC_PIN_GROUP(du_cde),
2058 SH_PFC_PIN_GROUP(du_disp),
2059 SH_PFC_PIN_GROUP(gether_link_a),
2060 SH_PFC_PIN_GROUP(gether_phy_int_a),
2061 SH_PFC_PIN_GROUP(gether_mdio_a),
2062 SH_PFC_PIN_GROUP(gether_link_b),
2063 SH_PFC_PIN_GROUP(gether_phy_int_b),
2064 SH_PFC_PIN_GROUP(gether_mdio_b),
2065 SH_PFC_PIN_GROUP(gether_magic),
2066 SH_PFC_PIN_GROUP(gether_rgmii),
2067 SH_PFC_PIN_GROUP(gether_txcrefclk),
2068 SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
2069 SH_PFC_PIN_GROUP(gether_rmii),
2070 SH_PFC_PIN_GROUP(hscif0_data_a),
2071 SH_PFC_PIN_GROUP(hscif0_clk_a),
2072 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
2073 SH_PFC_PIN_GROUP(hscif0_data_b),
2074 SH_PFC_PIN_GROUP(hscif0_clk_b),
2075 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2076 SH_PFC_PIN_GROUP(hscif1_data),
2077 SH_PFC_PIN_GROUP(hscif1_clk),
2078 SH_PFC_PIN_GROUP(hscif1_ctrl),
2079 SH_PFC_PIN_GROUP(hscif2_data),
2080 SH_PFC_PIN_GROUP(hscif2_clk),
2081 SH_PFC_PIN_GROUP(hscif2_ctrl),
2082 SH_PFC_PIN_GROUP(hscif3_data),
2083 SH_PFC_PIN_GROUP(hscif3_clk),
2084 SH_PFC_PIN_GROUP(hscif3_ctrl),
2085 SH_PFC_PIN_GROUP(i2c0),
2086 SH_PFC_PIN_GROUP(i2c1),
2087 SH_PFC_PIN_GROUP(i2c2),
2088 SH_PFC_PIN_GROUP(i2c3),
2089 SH_PFC_PIN_GROUP(i2c4),
2090 SH_PFC_PIN_GROUP(i2c5),
2091 SH_PFC_PIN_GROUP(intc_ex_irq0),
2092 SH_PFC_PIN_GROUP(intc_ex_irq1),
2093 SH_PFC_PIN_GROUP(intc_ex_irq2),
2094 SH_PFC_PIN_GROUP(intc_ex_irq3),
2095 SH_PFC_PIN_GROUP(intc_ex_irq4),
2096 SH_PFC_PIN_GROUP(intc_ex_irq5),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2097 BUS_DATA_PIN_GROUP(mmc_data, 1),
2098 BUS_DATA_PIN_GROUP(mmc_data, 4),
2099 BUS_DATA_PIN_GROUP(mmc_data, 8),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2100 SH_PFC_PIN_GROUP(mmc_ctrl),
2101 SH_PFC_PIN_GROUP(mmc_cd),
2102 SH_PFC_PIN_GROUP(mmc_wp),
2103 SH_PFC_PIN_GROUP(mmc_ds),
2104 SH_PFC_PIN_GROUP(msiof0_clk),
2105 SH_PFC_PIN_GROUP(msiof0_sync),
2106 SH_PFC_PIN_GROUP(msiof0_ss1),
2107 SH_PFC_PIN_GROUP(msiof0_ss2),
2108 SH_PFC_PIN_GROUP(msiof0_txd),
2109 SH_PFC_PIN_GROUP(msiof0_rxd),
2110 SH_PFC_PIN_GROUP(msiof1_clk),
2111 SH_PFC_PIN_GROUP(msiof1_sync),
2112 SH_PFC_PIN_GROUP(msiof1_ss1),
2113 SH_PFC_PIN_GROUP(msiof1_ss2),
2114 SH_PFC_PIN_GROUP(msiof1_txd),
2115 SH_PFC_PIN_GROUP(msiof1_rxd),
2116 SH_PFC_PIN_GROUP(msiof2_clk),
2117 SH_PFC_PIN_GROUP(msiof2_sync),
2118 SH_PFC_PIN_GROUP(msiof2_ss1),
2119 SH_PFC_PIN_GROUP(msiof2_ss2),
2120 SH_PFC_PIN_GROUP(msiof2_txd),
2121 SH_PFC_PIN_GROUP(msiof2_rxd),
2122 SH_PFC_PIN_GROUP(msiof3_clk),
2123 SH_PFC_PIN_GROUP(msiof3_sync),
2124 SH_PFC_PIN_GROUP(msiof3_ss1),
2125 SH_PFC_PIN_GROUP(msiof3_ss2),
2126 SH_PFC_PIN_GROUP(msiof3_txd),
2127 SH_PFC_PIN_GROUP(msiof3_rxd),
2128 SH_PFC_PIN_GROUP(pwm0_a),
2129 SH_PFC_PIN_GROUP(pwm0_b),
2130 SH_PFC_PIN_GROUP(pwm1_a),
2131 SH_PFC_PIN_GROUP(pwm1_b),
2132 SH_PFC_PIN_GROUP(pwm2_a),
2133 SH_PFC_PIN_GROUP(pwm2_b),
2134 SH_PFC_PIN_GROUP(pwm3_a),
2135 SH_PFC_PIN_GROUP(pwm3_b),
2136 SH_PFC_PIN_GROUP(pwm4_a),
2137 SH_PFC_PIN_GROUP(pwm4_b),
2138 SH_PFC_PIN_GROUP(qspi0_ctrl),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2139 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
2140 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2141 SH_PFC_PIN_GROUP(qspi1_ctrl),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2142 SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
2143 SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
2144 BUS_DATA_PIN_GROUP(rpc_clk, 1),
2145 BUS_DATA_PIN_GROUP(rpc_clk, 2),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]2146 SH_PFC_PIN_GROUP(rpc_ctrl),
2147 SH_PFC_PIN_GROUP(rpc_data),
2148 SH_PFC_PIN_GROUP(rpc_reset),
2149 SH_PFC_PIN_GROUP(rpc_int),
2150 SH_PFC_PIN_GROUP(rpc_wp),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2151 SH_PFC_PIN_GROUP(scif0_data),
2152 SH_PFC_PIN_GROUP(scif0_clk),
2153 SH_PFC_PIN_GROUP(scif0_ctrl),
2154 SH_PFC_PIN_GROUP(scif1_data_a),
2155 SH_PFC_PIN_GROUP(scif1_clk),
2156 SH_PFC_PIN_GROUP(scif1_ctrl),
2157 SH_PFC_PIN_GROUP(scif1_data_b),
2158 SH_PFC_PIN_GROUP(scif3_data),
2159 SH_PFC_PIN_GROUP(scif3_clk),
2160 SH_PFC_PIN_GROUP(scif3_ctrl),
2161 SH_PFC_PIN_GROUP(scif4_data),
2162 SH_PFC_PIN_GROUP(scif4_clk),
2163 SH_PFC_PIN_GROUP(scif4_ctrl),
2164 SH_PFC_PIN_GROUP(scif_clk_a),
2165 SH_PFC_PIN_GROUP(scif_clk_b),
2166 SH_PFC_PIN_GROUP(tmu_tclk1_a),
2167 SH_PFC_PIN_GROUP(tmu_tclk1_b),
2168 SH_PFC_PIN_GROUP(tmu_tclk2_a),
2169 SH_PFC_PIN_GROUP(tmu_tclk2_b),
2170 SH_PFC_PIN_GROUP(tpu_to0),
2171 SH_PFC_PIN_GROUP(tpu_to1),
2172 SH_PFC_PIN_GROUP(tpu_to2),
2173 SH_PFC_PIN_GROUP(tpu_to3),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2174 BUS_DATA_PIN_GROUP(vin0_data, 8),
2175 BUS_DATA_PIN_GROUP(vin0_data, 10),
2176 BUS_DATA_PIN_GROUP(vin0_data, 12),
2177 BUS_DATA_PIN_GROUP(vin0_data, 16),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2178 SH_PFC_PIN_GROUP(vin0_data18),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2179 BUS_DATA_PIN_GROUP(vin0_data, 20),
2180 BUS_DATA_PIN_GROUP(vin0_data, 24),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2181 SH_PFC_PIN_GROUP(vin0_sync),
2182 SH_PFC_PIN_GROUP(vin0_field),
2183 SH_PFC_PIN_GROUP(vin0_clkenb),
2184 SH_PFC_PIN_GROUP(vin0_clk),
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2185 BUS_DATA_PIN_GROUP(vin1_data, 8),
2186 BUS_DATA_PIN_GROUP(vin1_data, 10),
2187 BUS_DATA_PIN_GROUP(vin1_data, 12),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2188 SH_PFC_PIN_GROUP(vin1_sync),
2189 SH_PFC_PIN_GROUP(vin1_field),
2190 SH_PFC_PIN_GROUP(vin1_clkenb),
2191 SH_PFC_PIN_GROUP(vin1_clk),
2192};
2193
2194static const char * const avb_groups[] = {
2195 "avb_link",
2196 "avb_magic",
2197 "avb_phy_int",
2198 "avb_mdio",
2199 "avb_rgmii",
2200 "avb_txcrefclk",
2201 "avb_avtp_pps",
2202 "avb_avtp_capture",
2203 "avb_avtp_match",
2204};
2205
2206static const char * const canfd0_groups[] = {
2207 "canfd0_data_a",
2208 "canfd0_data_b",
2209};
2210
2211static const char * const canfd1_groups[] = {
2212 "canfd1_data",
2213};
2214
2215static const char * const canfd_clk_groups[] = {
2216 "canfd_clk_a",
2217 "canfd_clk_b",
2218};
2219
2220static const char * const du_groups[] = {
2221 "du_rgb666",
2222 "du_rgb888",
2223 "du_clk_out",
2224 "du_sync",
2225 "du_oddf",
2226 "du_cde",
2227 "du_disp",
2228};
2229
2230static const char * const gether_groups[] = {
2231 "gether_link_a",
2232 "gether_phy_int_a",
2233 "gether_mdio_a",
2234 "gether_link_b",
2235 "gether_phy_int_b",
2236 "gether_mdio_b",
2237 "gether_magic",
2238 "gether_rgmii",
2239 "gether_txcrefclk",
2240 "gether_txcrefclk_mega",
2241 "gether_rmii",
2242};
2243
2244static const char * const hscif0_groups[] = {
2245 "hscif0_data_a",
2246 "hscif0_clk_a",
2247 "hscif0_ctrl_a",
2248 "hscif0_data_b",
2249 "hscif0_clk_b",
2250 "hscif0_ctrl_b",
2251};
2252
2253static const char * const hscif1_groups[] = {
2254 "hscif1_data",
2255 "hscif1_clk",
2256 "hscif1_ctrl",
2257};
2258
2259static const char * const hscif2_groups[] = {
2260 "hscif2_data",
2261 "hscif2_clk",
2262 "hscif2_ctrl",
2263};
2264
2265static const char * const hscif3_groups[] = {
2266 "hscif3_data",
2267 "hscif3_clk",
2268 "hscif3_ctrl",
2269};
2270
2271static const char * const i2c0_groups[] = {
2272 "i2c0",
2273};
2274
2275static const char * const i2c1_groups[] = {
2276 "i2c1",
2277};
2278
2279static const char * const i2c2_groups[] = {
2280 "i2c2",
2281};
2282
2283static const char * const i2c3_groups[] = {
2284 "i2c3",
2285};
2286
2287static const char * const i2c4_groups[] = {
2288 "i2c4",
2289};
2290
2291static const char * const i2c5_groups[] = {
2292 "i2c5",
2293};
2294
2295static const char * const intc_ex_groups[] = {
2296 "intc_ex_irq0",
2297 "intc_ex_irq1",
2298 "intc_ex_irq2",
2299 "intc_ex_irq3",
2300 "intc_ex_irq4",
2301 "intc_ex_irq5",
2302};
2303
2304static const char * const mmc_groups[] = {
2305 "mmc_data1",
2306 "mmc_data4",
2307 "mmc_data8",
2308 "mmc_ctrl",
2309 "mmc_cd",
2310 "mmc_wp",
2311 "mmc_ds",
2312};
2313
2314static const char * const msiof0_groups[] = {
2315 "msiof0_clk",
2316 "msiof0_sync",
2317 "msiof0_ss1",
2318 "msiof0_ss2",
2319 "msiof0_txd",
2320 "msiof0_rxd",
2321};
2322
2323static const char * const msiof1_groups[] = {
2324 "msiof1_clk",
2325 "msiof1_sync",
2326 "msiof1_ss1",
2327 "msiof1_ss2",
2328 "msiof1_txd",
2329 "msiof1_rxd",
2330};
2331
2332static const char * const msiof2_groups[] = {
2333 "msiof2_clk",
2334 "msiof2_sync",
2335 "msiof2_ss1",
2336 "msiof2_ss2",
2337 "msiof2_txd",
2338 "msiof2_rxd",
2339};
2340
2341static const char * const msiof3_groups[] = {
2342 "msiof3_clk",
2343 "msiof3_sync",
2344 "msiof3_ss1",
2345 "msiof3_ss2",
2346 "msiof3_txd",
2347 "msiof3_rxd",
2348};
2349
2350static const char * const pwm0_groups[] = {
2351 "pwm0_a",
2352 "pwm0_b",
2353};
2354
2355static const char * const pwm1_groups[] = {
2356 "pwm1_a",
2357 "pwm1_b",
2358};
2359
2360static const char * const pwm2_groups[] = {
2361 "pwm2_a",
2362 "pwm2_b",
2363};
2364
2365static const char * const pwm3_groups[] = {
2366 "pwm3_a",
2367 "pwm3_b",
2368};
2369
2370static const char * const pwm4_groups[] = {
2371 "pwm4_a",
2372 "pwm4_b",
2373};
2374
2375static const char * const qspi0_groups[] = {
2376 "qspi0_ctrl",
2377 "qspi0_data2",
2378 "qspi0_data4",
2379};
2380
2381static const char * const qspi1_groups[] = {
2382 "qspi1_ctrl",
2383 "qspi1_data2",
2384 "qspi1_data4",
2385};
2386
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]2387static const char * const rpc_groups[] = {
2388 "rpc_clk1",
2389 "rpc_clk2",
2390 "rpc_ctrl",
2391 "rpc_data",
2392 "rpc_reset",
2393 "rpc_int",
2394 "rpc_wp",
2395};
2396
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2397static const char * const scif0_groups[] = {
2398 "scif0_data",
2399 "scif0_clk",
2400 "scif0_ctrl",
2401};
2402
2403static const char * const scif1_groups[] = {
2404 "scif1_data_a",
2405 "scif1_clk",
2406 "scif1_ctrl",
2407 "scif1_data_b",
2408};
2409
2410static const char * const scif3_groups[] = {
2411 "scif3_data",
2412 "scif3_clk",
2413 "scif3_ctrl",
2414};
2415
2416static const char * const scif4_groups[] = {
2417 "scif4_data",
2418 "scif4_clk",
2419 "scif4_ctrl",
2420};
2421
2422static const char * const scif_clk_groups[] = {
2423 "scif_clk_a",
2424 "scif_clk_b",
2425};
2426
2427static const char * const tmu_groups[] = {
2428 "tmu_tclk1_a",
2429 "tmu_tclk1_b",
2430 "tmu_tclk2_a",
2431 "tmu_tclk2_b",
2432};
2433
2434static const char * const tpu_groups[] = {
2435 "tpu_to0",
2436 "tpu_to1",
2437 "tpu_to2",
2438 "tpu_to3",
2439};
2440
2441static const char * const vin0_groups[] = {
2442 "vin0_data8",
2443 "vin0_data10",
2444 "vin0_data12",
2445 "vin0_data16",
2446 "vin0_data18",
2447 "vin0_data20",
2448 "vin0_data24",
2449 "vin0_sync",
2450 "vin0_field",
2451 "vin0_clkenb",
2452 "vin0_clk",
2453};
2454
2455static const char * const vin1_groups[] = {
2456 "vin1_data8",
2457 "vin1_data10",
2458 "vin1_data12",
2459 "vin1_sync",
2460 "vin1_field",
2461 "vin1_clkenb",
2462 "vin1_clk",
2463};
2464
2465static const struct sh_pfc_function pinmux_functions[] = {
2466 SH_PFC_FUNCTION(avb),
2467 SH_PFC_FUNCTION(canfd0),
2468 SH_PFC_FUNCTION(canfd1),
2469 SH_PFC_FUNCTION(canfd_clk),
2470 SH_PFC_FUNCTION(du),
2471 SH_PFC_FUNCTION(gether),
2472 SH_PFC_FUNCTION(hscif0),
2473 SH_PFC_FUNCTION(hscif1),
2474 SH_PFC_FUNCTION(hscif2),
2475 SH_PFC_FUNCTION(hscif3),
2476 SH_PFC_FUNCTION(i2c0),
2477 SH_PFC_FUNCTION(i2c1),
2478 SH_PFC_FUNCTION(i2c2),
2479 SH_PFC_FUNCTION(i2c3),
2480 SH_PFC_FUNCTION(i2c4),
2481 SH_PFC_FUNCTION(i2c5),
2482 SH_PFC_FUNCTION(intc_ex),
2483 SH_PFC_FUNCTION(mmc),
2484 SH_PFC_FUNCTION(msiof0),
2485 SH_PFC_FUNCTION(msiof1),
2486 SH_PFC_FUNCTION(msiof2),
2487 SH_PFC_FUNCTION(msiof3),
2488 SH_PFC_FUNCTION(pwm0),
2489 SH_PFC_FUNCTION(pwm1),
2490 SH_PFC_FUNCTION(pwm2),
2491 SH_PFC_FUNCTION(pwm3),
2492 SH_PFC_FUNCTION(pwm4),
2493 SH_PFC_FUNCTION(qspi0),
2494 SH_PFC_FUNCTION(qspi1),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]2495 SH_PFC_FUNCTION(rpc),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2496 SH_PFC_FUNCTION(scif0),
2497 SH_PFC_FUNCTION(scif1),
2498 SH_PFC_FUNCTION(scif3),
2499 SH_PFC_FUNCTION(scif4),
2500 SH_PFC_FUNCTION(scif_clk),
2501 SH_PFC_FUNCTION(tmu),
2502 SH_PFC_FUNCTION(tpu),
2503 SH_PFC_FUNCTION(vin0),
2504 SH_PFC_FUNCTION(vin1),
2505};
2506
2507static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2508#define F_(x, y) FN_##y
2509#define FM(x) FN_##x
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2510 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2511 GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2512 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2513 GROUP(
2514 /* GP0_31_22 RESERVED */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2515 GP_0_21_FN, GPSR0_21,
2516 GP_0_20_FN, GPSR0_20,
2517 GP_0_19_FN, GPSR0_19,
2518 GP_0_18_FN, GPSR0_18,
2519 GP_0_17_FN, GPSR0_17,
2520 GP_0_16_FN, GPSR0_16,
2521 GP_0_15_FN, GPSR0_15,
2522 GP_0_14_FN, GPSR0_14,
2523 GP_0_13_FN, GPSR0_13,
2524 GP_0_12_FN, GPSR0_12,
2525 GP_0_11_FN, GPSR0_11,
2526 GP_0_10_FN, GPSR0_10,
2527 GP_0_9_FN, GPSR0_9,
2528 GP_0_8_FN, GPSR0_8,
2529 GP_0_7_FN, GPSR0_7,
2530 GP_0_6_FN, GPSR0_6,
2531 GP_0_5_FN, GPSR0_5,
2532 GP_0_4_FN, GPSR0_4,
2533 GP_0_3_FN, GPSR0_3,
2534 GP_0_2_FN, GPSR0_2,
2535 GP_0_1_FN, GPSR0_1,
2536 GP_0_0_FN, GPSR0_0, ))
2537 },
2538 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2539 0, 0,
2540 0, 0,
2541 0, 0,
2542 0, 0,
2543 GP_1_27_FN, GPSR1_27,
2544 GP_1_26_FN, GPSR1_26,
2545 GP_1_25_FN, GPSR1_25,
2546 GP_1_24_FN, GPSR1_24,
2547 GP_1_23_FN, GPSR1_23,
2548 GP_1_22_FN, GPSR1_22,
2549 GP_1_21_FN, GPSR1_21,
2550 GP_1_20_FN, GPSR1_20,
2551 GP_1_19_FN, GPSR1_19,
2552 GP_1_18_FN, GPSR1_18,
2553 GP_1_17_FN, GPSR1_17,
2554 GP_1_16_FN, GPSR1_16,
2555 GP_1_15_FN, GPSR1_15,
2556 GP_1_14_FN, GPSR1_14,
2557 GP_1_13_FN, GPSR1_13,
2558 GP_1_12_FN, GPSR1_12,
2559 GP_1_11_FN, GPSR1_11,
2560 GP_1_10_FN, GPSR1_10,
2561 GP_1_9_FN, GPSR1_9,
2562 GP_1_8_FN, GPSR1_8,
2563 GP_1_7_FN, GPSR1_7,
2564 GP_1_6_FN, GPSR1_6,
2565 GP_1_5_FN, GPSR1_5,
2566 GP_1_4_FN, GPSR1_4,
2567 GP_1_3_FN, GPSR1_3,
2568 GP_1_2_FN, GPSR1_2,
2569 GP_1_1_FN, GPSR1_1,
2570 GP_1_0_FN, GPSR1_0, ))
2571 },
2572 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2573 0, 0,
2574 0, 0,
2575 GP_2_29_FN, GPSR2_29,
2576 GP_2_28_FN, GPSR2_28,
2577 GP_2_27_FN, GPSR2_27,
2578 GP_2_26_FN, GPSR2_26,
2579 GP_2_25_FN, GPSR2_25,
2580 GP_2_24_FN, GPSR2_24,
2581 GP_2_23_FN, GPSR2_23,
2582 GP_2_22_FN, GPSR2_22,
2583 GP_2_21_FN, GPSR2_21,
2584 GP_2_20_FN, GPSR2_20,
2585 GP_2_19_FN, GPSR2_19,
2586 GP_2_18_FN, GPSR2_18,
2587 GP_2_17_FN, GPSR2_17,
2588 GP_2_16_FN, GPSR2_16,
2589 GP_2_15_FN, GPSR2_15,
2590 GP_2_14_FN, GPSR2_14,
2591 GP_2_13_FN, GPSR2_13,
2592 GP_2_12_FN, GPSR2_12,
2593 GP_2_11_FN, GPSR2_11,
2594 GP_2_10_FN, GPSR2_10,
2595 GP_2_9_FN, GPSR2_9,
2596 GP_2_8_FN, GPSR2_8,
2597 GP_2_7_FN, GPSR2_7,
2598 GP_2_6_FN, GPSR2_6,
2599 GP_2_5_FN, GPSR2_5,
2600 GP_2_4_FN, GPSR2_4,
2601 GP_2_3_FN, GPSR2_3,
2602 GP_2_2_FN, GPSR2_2,
2603 GP_2_1_FN, GPSR2_1,
2604 GP_2_0_FN, GPSR2_0, ))
2605 },
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2606 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2607 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2608 1, 1, 1, 1, 1, 1),
2609 GROUP(
2610 /* GP3_31_17 RESERVED */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2611 GP_3_16_FN, GPSR3_16,
2612 GP_3_15_FN, GPSR3_15,
2613 GP_3_14_FN, GPSR3_14,
2614 GP_3_13_FN, GPSR3_13,
2615 GP_3_12_FN, GPSR3_12,
2616 GP_3_11_FN, GPSR3_11,
2617 GP_3_10_FN, GPSR3_10,
2618 GP_3_9_FN, GPSR3_9,
2619 GP_3_8_FN, GPSR3_8,
2620 GP_3_7_FN, GPSR3_7,
2621 GP_3_6_FN, GPSR3_6,
2622 GP_3_5_FN, GPSR3_5,
2623 GP_3_4_FN, GPSR3_4,
2624 GP_3_3_FN, GPSR3_3,
2625 GP_3_2_FN, GPSR3_2,
2626 GP_3_1_FN, GPSR3_1,
2627 GP_3_0_FN, GPSR3_0, ))
2628 },
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2629 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2630 GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2631 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2632 1, 1),
2633 GROUP(
2634 /* GP4_31_25 RESERVED */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2635 GP_4_24_FN, GPSR4_24,
2636 GP_4_23_FN, GPSR4_23,
2637 GP_4_22_FN, GPSR4_22,
2638 GP_4_21_FN, GPSR4_21,
2639 GP_4_20_FN, GPSR4_20,
2640 GP_4_19_FN, GPSR4_19,
2641 GP_4_18_FN, GPSR4_18,
2642 GP_4_17_FN, GPSR4_17,
2643 GP_4_16_FN, GPSR4_16,
2644 GP_4_15_FN, GPSR4_15,
2645 GP_4_14_FN, GPSR4_14,
2646 GP_4_13_FN, GPSR4_13,
2647 GP_4_12_FN, GPSR4_12,
2648 GP_4_11_FN, GPSR4_11,
2649 GP_4_10_FN, GPSR4_10,
2650 GP_4_9_FN, GPSR4_9,
2651 GP_4_8_FN, GPSR4_8,
2652 GP_4_7_FN, GPSR4_7,
2653 GP_4_6_FN, GPSR4_6,
2654 GP_4_5_FN, GPSR4_5,
2655 GP_4_4_FN, GPSR4_4,
2656 GP_4_3_FN, GPSR4_3,
2657 GP_4_2_FN, GPSR4_2,
2658 GP_4_1_FN, GPSR4_1,
2659 GP_4_0_FN, GPSR4_0, ))
2660 },
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2661 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2662 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2663 1, 1, 1, 1),
2664 GROUP(
2665 /* GP5_31_15 RESERVED */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2666 GP_5_14_FN, GPSR5_14,
2667 GP_5_13_FN, GPSR5_13,
2668 GP_5_12_FN, GPSR5_12,
2669 GP_5_11_FN, GPSR5_11,
2670 GP_5_10_FN, GPSR5_10,
2671 GP_5_9_FN, GPSR5_9,
2672 GP_5_8_FN, GPSR5_8,
2673 GP_5_7_FN, GPSR5_7,
2674 GP_5_6_FN, GPSR5_6,
2675 GP_5_5_FN, GPSR5_5,
2676 GP_5_4_FN, GPSR5_4,
2677 GP_5_3_FN, GPSR5_3,
2678 GP_5_2_FN, GPSR5_2,
2679 GP_5_1_FN, GPSR5_1,
2680 GP_5_0_FN, GPSR5_0, ))
2681 },
2682#undef F_
2683#undef FM
2684
2685#define F_(x, y) x,
2686#define FM(x) FN_##x,
2687 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2688 IP0_31_28
2689 IP0_27_24
2690 IP0_23_20
2691 IP0_19_16
2692 IP0_15_12
2693 IP0_11_8
2694 IP0_7_4
2695 IP0_3_0 ))
2696 },
2697 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2698 IP1_31_28
2699 IP1_27_24
2700 IP1_23_20
2701 IP1_19_16
2702 IP1_15_12
2703 IP1_11_8
2704 IP1_7_4
2705 IP1_3_0 ))
2706 },
2707 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2708 IP2_31_28
2709 IP2_27_24
2710 IP2_23_20
2711 IP2_19_16
2712 IP2_15_12
2713 IP2_11_8
2714 IP2_7_4
2715 IP2_3_0 ))
2716 },
2717 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2718 IP3_31_28
2719 IP3_27_24
2720 IP3_23_20
2721 IP3_19_16
2722 IP3_15_12
2723 IP3_11_8
2724 IP3_7_4
2725 IP3_3_0 ))
2726 },
2727 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2728 IP4_31_28
2729 IP4_27_24
2730 IP4_23_20
2731 IP4_19_16
2732 IP4_15_12
2733 IP4_11_8
2734 IP4_7_4
2735 IP4_3_0 ))
2736 },
2737 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2738 IP5_31_28
2739 IP5_27_24
2740 IP5_23_20
2741 IP5_19_16
2742 IP5_15_12
2743 IP5_11_8
2744 IP5_7_4
2745 IP5_3_0 ))
2746 },
2747 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2748 IP6_31_28
2749 IP6_27_24
2750 IP6_23_20
2751 IP6_19_16
2752 IP6_15_12
2753 IP6_11_8
2754 IP6_7_4
2755 IP6_3_0 ))
2756 },
2757 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2758 IP7_31_28
2759 IP7_27_24
2760 IP7_23_20
2761 IP7_19_16
2762 IP7_15_12
2763 IP7_11_8
2764 IP7_7_4
2765 IP7_3_0 ))
2766 },
2767 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2768 IP8_31_28
2769 IP8_27_24
2770 IP8_23_20
2771 IP8_19_16
2772 IP8_15_12
2773 IP8_11_8
2774 IP8_7_4
2775 IP8_3_0 ))
2776 },
2777 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2778 IP9_31_28
2779 IP9_27_24
2780 IP9_23_20
2781 IP9_19_16
2782 IP9_15_12
2783 IP9_11_8
2784 IP9_7_4
2785 IP9_3_0 ))
2786 },
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2787 { PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
2788 GROUP(-12, 4, 4, 4, 4, 4),
2789 GROUP(
2790 /* IP10_31_20 RESERVED */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2791 IP10_19_16
2792 IP10_15_12
2793 IP10_11_8
2794 IP10_7_4
2795 IP10_3_0 ))
2796 },
2797#undef F_
2798#undef FM
2799
2800#define F_(x, y) x,
2801#define FM(x) FN_##x,
2802 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2803 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1),
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2804 GROUP(
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2805 /* RESERVED 31-12 */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2806 MOD_SEL0_11
2807 MOD_SEL0_10
2808 MOD_SEL0_9
2809 MOD_SEL0_8
2810 MOD_SEL0_7
2811 MOD_SEL0_6
2812 MOD_SEL0_5
2813 MOD_SEL0_4
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2814 /* RESERVED 3 */
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2815 MOD_SEL0_2
2816 MOD_SEL0_1
2817 MOD_SEL0_0 ))
2818 },
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2819 { /* sentinel */ }
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2820};
2821
2822enum ioctrl_regs {
2823 POCCTRL0,
2824 POCCTRL1,
2825 POCCTRL2,
2826 POCCTRL3,
2827 TDSELCTRL,
2828};
2829
2830static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2831 [POCCTRL0] = { 0xe6060380, },
2832 [POCCTRL1] = { 0xe6060384, },
2833 [POCCTRL2] = { 0xe6060388, },
2834 [POCCTRL3] = { 0xe606038c, },
2835 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2836 { /* sentinel */ }
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2837};
2838
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2839static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2840{
2841 int bit = pin & 0x1f;
2842
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2843 switch (pin) {
2844 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
2845 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2846 return bit;
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2847
2848 case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
2849 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2850 return bit + 22;
2851
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2852 case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
2853 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2854 return bit - 10;
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2855
2856 case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
2857 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
2858 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2859 return bit + 7;
2860
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2861 case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
2862 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2863 return pin - 25;
2864
Marek Vasut3234b752023-09-17 16:08:44 +0200[diff] [blame]2865 case PIN_VDDQ_AVB:
2866 *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
2867 return 0;
2868
2869 case PIN_VDDQ_GE:
2870 *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
2871 return 1;
2872
2873 default:
2874 return -EINVAL;
2875 }
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]2876}
2877
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]2878static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2879 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2880 [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
2881 [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
2882 [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
2883 [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
2884 [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
2885 [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
2886 [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
2887 [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
2888 [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
2889 [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
2890 [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
2891 [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
2892 [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
2893 [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
2894 [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
2895 [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
2896 [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
2897 [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
2898 [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
2899 [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
2900 [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
2901 [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
2902 [22] = SH_PFC_PIN_NONE,
2903 [23] = SH_PFC_PIN_NONE,
2904 [24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
2905 [25] = SH_PFC_PIN_NONE,
2906 [26] = PIN_PRESETOUT_N, /* PRESETOUT# */
2907 [27] = SH_PFC_PIN_NONE,
2908 [28] = SH_PFC_PIN_NONE,
2909 [29] = SH_PFC_PIN_NONE,
2910 [30] = PIN_EXTALR, /* EXTALR */
2911 [31] = PIN_FSCLKST_N, /* FSCLKST# */
2912 } },
2913 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2914 [ 0] = PIN_FSCLKST, /* FSCLKST */
2915 [ 1] = SH_PFC_PIN_NONE,
2916 [ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */
2917 [ 3] = PIN_DCUTRST_N, /* DCUTRST# */
2918 [ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */
2919 [ 5] = PIN_DCUTMS, /* DCUTMS */
2920 [ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */
2921 [ 7] = SH_PFC_PIN_NONE,
2922 [ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
2923 [ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
2924 [10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
2925 [11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
2926 [12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
2927 [13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
2928 [14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
2929 [15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
2930 [16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
2931 [17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
2932 [18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
2933 [19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
2934 [20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
2935 [21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
2936 [22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
2937 [23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
2938 [24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
2939 [25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
2940 [26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
2941 [27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
2942 [28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
2943 [29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
2944 [30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
2945 [31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
2946 } },
2947 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2948 [ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
2949 [ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
2950 [ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
2951 [ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
2952 [ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
2953 [ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
2954 [ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
2955 [ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
2956 [ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
2957 [ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
2958 [10] = RCAR_GP_PIN(4, 0), /* SCL0 */
2959 [11] = RCAR_GP_PIN(4, 1), /* SDA0 */
2960 [12] = RCAR_GP_PIN(4, 2), /* SCL1 */
2961 [13] = RCAR_GP_PIN(4, 3), /* SDA1 */
2962 [14] = RCAR_GP_PIN(4, 4), /* SCL2 */
2963 [15] = RCAR_GP_PIN(4, 5), /* SDA2 */
2964 [16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */
2965 [17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */
2966 [18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */
2967 [19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */
2968 [20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */
2969 [21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */
2970 [22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */
2971 [23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */
2972 [24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */
2973 [25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */
2974 [26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */
2975 [27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */
2976 [28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */
2977 [29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */
2978 [30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */
2979 [31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */
2980 } },
2981 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2982 [ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */
2983 [ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */
2984 [ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */
2985 [ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */
2986 [ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */
2987 [ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */
2988 [ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */
2989 [ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */
2990 [ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */
2991 [ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */
2992 [10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */
2993 [11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */
2994 [12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */
2995 [13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */
2996 [14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */
2997 [15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */
2998 [16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */
2999 [17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */
3000 [18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */
3001 [19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */
3002 [20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */
3003 [21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */
3004 [22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */
3005 [23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
3006 [24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
3007 [25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
3008 [26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
3009 [27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */
3010 [28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
3011 [29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
3012 [30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
3013 [31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
3014 } },
3015 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
3016 [ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
3017 [ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
3018 [ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
3019 [ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
3020 [ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
3021 [ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
3022 [ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
3023 [ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
3024 [ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
3025 [ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
3026 [10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
3027 [11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
3028 [12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
3029 [13] = RCAR_GP_PIN(2, 17), /* IRQ4 */
3030 [14] = RCAR_GP_PIN(2, 18), /* IRQ5 */
3031 [15] = RCAR_GP_PIN(2, 25), /* SCL3 */
3032 [16] = RCAR_GP_PIN(2, 26), /* SDA3 */
3033 [17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */
3034 [18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */
3035 [19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */
3036 [20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */
3037 [21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */
3038 [22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */
3039 [23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */
3040 [24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */
3041 [25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */
3042 [26] = SH_PFC_PIN_NONE,
3043 [27] = SH_PFC_PIN_NONE,
3044 [28] = SH_PFC_PIN_NONE,
3045 [29] = SH_PFC_PIN_NONE,
3046 [30] = SH_PFC_PIN_NONE,
3047 [31] = SH_PFC_PIN_NONE,
3048 } },
3049 { /* sentinel */ }
3050};
3051
3052static const struct sh_pfc_soc_operations r8a77980_pfc_ops = {
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]3053 .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]3054 .get_bias = rcar_pinmux_get_bias,
3055 .set_bias = rcar_pinmux_set_bias,
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]3056};
3057
3058const struct sh_pfc_soc_info r8a77980_pinmux_info = {
3059 .name = "r8a77980_pfc",
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]3060 .ops = &r8a77980_pfc_ops,
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]3061 .unlock_reg = 0xe6060000, /* PMMR */
3062
3063 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3064
3065 .pins = pinmux_pins,
3066 .nr_pins = ARRAY_SIZE(pinmux_pins),
3067 .groups = pinmux_groups,
3068 .nr_groups = ARRAY_SIZE(pinmux_groups),
3069 .functions = pinmux_functions,
3070 .nr_functions = ARRAY_SIZE(pinmux_functions),
3071
3072 .cfg_regs = pinmux_config_regs,
Marek Vasutbad67e62023-01-26 21:01:44 +0100[diff] [blame]3073 .bias_regs = pinmux_bias_regs,
Marek Vasuta6a7f482019-07-29 19:59:44 +0200[diff] [blame]3074 .ioctrl_regs = pinmux_ioctrl_regs,
3075
3076 .pinmux_data = pinmux_data,
3077 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3078};