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git01.mediatek.com / filogic / uboot / 26f5130fdbb30c280e10d649ccb31bd1e201ff1d / . / drivers / pinctrl / mediatek / pinctrl-mt8518.c
blob: 66fcfdff14491ba8f619d8f66305d21975b7a4cb [file] [log] [blame]
developerc3aeb812019-11-07 19:28:43 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Author: Mingming Lee <mingming.lee@mediatek.com>
5 */
6
7#include <dm.h>
8
9#include "pinctrl-mtk-common.h"
10
11#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
12 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
13 _x_bits, 16, false)
14
15static const struct mtk_pin_field_calc mt8518_pin_mode_range[] = {
16 PIN_FIELD_CALC(0, 119, 0x300, 0x10, 0, 3, 15, false),
17};
18
19static const struct mtk_pin_field_calc mt8518_pin_dir_range[] = {
20 PIN_FIELD(0, 119, 0x0, 0x10, 0, 1),
21};
22
23static const struct mtk_pin_field_calc mt8518_pin_di_range[] = {
24 PIN_FIELD(0, 119, 0x200, 0x10, 0, 1),
25};
26
27static const struct mtk_pin_field_calc mt8518_pin_do_range[] = {
28 PIN_FIELD(0, 119, 0x100, 0x10, 0, 1),
29};
30
31static const struct mtk_pin_field_calc mt8518_pin_ies_range[] = {
32 PIN_FIELD(0, 2, 0x900, 0x10, 0, 1),
33 PIN_FIELD(3, 3, 0x920, 0x10, 9, 1),
34 PIN_FIELD(4, 4, 0x920, 0x10, 8, 1),
35 PIN_FIELD(5, 5, 0x920, 0x10, 7, 1),
36 PIN_FIELD(6, 6, 0x920, 0x10, 6, 1),
37 PIN_FIELD(7, 7, 0x920, 0x10, 10, 1),
38 PIN_FIELD(8, 8, 0x920, 0x10, 1, 1),
39 PIN_FIELD(9, 9, 0x920, 0x10, 0, 1),
40 PIN_FIELD(10, 10, 0x920, 0x10, 5, 1),
41 PIN_FIELD(11, 11, 0x920, 0x10, 4, 1),
42 PIN_FIELD(12, 12, 0x920, 0x10, 3, 1),
43 PIN_FIELD(13, 13, 0x920, 0x10, 2, 1),
44 PIN_FIELD(14, 14, 0x900, 0x10, 1, 1),
45 PIN_FIELD(15, 15, 0x900, 0x10, 2, 1),
46 PIN_FIELD(16, 16, 0x900, 0x10, 3, 1),
47 PIN_FIELD(17, 20, 0x900, 0x10, 4, 1),
48 PIN_FIELD(21, 22, 0x900, 0x10, 5, 1),
49 PIN_FIELD(23, 27, 0x910, 0x10, 15, 1),
50 PIN_FIELD(28, 28, 0x900, 0x10, 6, 1),
51 PIN_FIELD(29, 29, 0x930, 0x10, 2, 1),
52 PIN_FIELD(30, 30, 0x930, 0x10, 1, 1),
53 PIN_FIELD(31, 31, 0x930, 0x10, 6, 1),
54 PIN_FIELD(32, 32, 0x930, 0x10, 5, 1),
55 PIN_FIELD(33, 33, 0x930, 0x10, 4, 1),
56 PIN_FIELD(34, 35, 0x930, 0x10, 3, 1),
57 PIN_FIELD(36, 39, 0x900, 0x10, 7, 1),
58 PIN_FIELD(40, 41, 0x900, 0x10, 8, 1),
59 PIN_FIELD(42, 44, 0x900, 0x10, 9, 1),
60 PIN_FIELD(45, 47, 0x900, 0x10, 10, 1),
61 PIN_FIELD(48, 51, 0x900, 0x10, 11, 1),
62 PIN_FIELD(52, 55, 0x900, 0x10, 12, 1),
63 PIN_FIELD(56, 56, 0x900, 0x10, 13, 1),
64 PIN_FIELD(57, 57, 0x900, 0x10, 14, 1),
65 PIN_FIELD(58, 58, 0x900, 0x10, 15, 1),
66 PIN_FIELD(59, 60, 0x910, 0x10, 0, 1),
67
68 PIN_FIELD(61, 61, 0x910, 0x10, 1, 1),
69 PIN_FIELD(62, 62, 0x910, 0x10, 2, 1),
70 PIN_FIELD(63, 69, 0x910, 0x10, 3, 1),
71 PIN_FIELD(70, 70, 0x910, 0x10, 4, 1),
72 PIN_FIELD(71, 76, 0x910, 0x10, 5, 1),
73 PIN_FIELD(77, 80, 0x910, 0x10, 6, 1),
74 PIN_FIELD(81, 87, 0x910, 0x10, 7, 1),
75 PIN_FIELD(88, 97, 0x910, 0x10, 8, 1),
76 PIN_FIELD(98, 103, 0x910, 0x10, 9, 1),
77 PIN_FIELD(104, 107, 0x910, 0x10, 10, 1),
78 PIN_FIELD(108, 109, 0x910, 0x10, 11, 1),
79 PIN_FIELD(110, 111, 0x910, 0x10, 12, 1),
80 PIN_FIELD(112, 113, 0x910, 0x10, 13, 1),
81 PIN_FIELD(114, 114, 0x920, 0x10, 12, 1),
82 PIN_FIELD(115, 115, 0x920, 0x10, 11, 1),
83 PIN_FIELD(116, 116, 0x930, 0x10, 0, 1),
84 PIN_FIELD(117, 117, 0x920, 0x10, 15, 1),
85 PIN_FIELD(118, 118, 0x920, 0x10, 14, 1),
86 PIN_FIELD(119, 119, 0x920, 0x10, 13, 1),
87};
88
89static const struct mtk_pin_field_calc mt8518_pin_smt_range[] = {
90 PIN_FIELD(0, 2, 0xA00, 0x10, 0, 1),
91 PIN_FIELD(3, 3, 0xA20, 0x10, 9, 1),
92 PIN_FIELD(4, 4, 0xA20, 0x10, 8, 1),
93 PIN_FIELD(5, 5, 0xA20, 0x10, 7, 1),
94 PIN_FIELD(6, 6, 0xA20, 0x10, 6, 1),
95 PIN_FIELD(7, 7, 0xA20, 0x10, 10, 1),
96 PIN_FIELD(8, 8, 0xA20, 0x10, 1, 1),
97 PIN_FIELD(9, 9, 0xA20, 0x10, 0, 1),
98 PIN_FIELD(10, 10, 0xA20, 0x10, 5, 1),
99 PIN_FIELD(11, 11, 0xA20, 0x10, 4, 1),
100 PIN_FIELD(12, 12, 0xA20, 0x10, 3, 1),
101 PIN_FIELD(13, 13, 0xA20, 0x10, 2, 1),
102 PIN_FIELD(14, 14, 0xA00, 0x10, 1, 1),
103 PIN_FIELD(15, 15, 0xA00, 0x10, 2, 1),
104 PIN_FIELD(16, 16, 0xA00, 0x10, 3, 1),
105 PIN_FIELD(17, 20, 0xA00, 0x10, 4, 1),
106 PIN_FIELD(21, 22, 0xA00, 0x10, 5, 1),
107 PIN_FIELD(23, 27, 0xA10, 0x10, 15, 1),
108 PIN_FIELD(28, 28, 0xA00, 0x10, 6, 1),
109 PIN_FIELD(29, 29, 0xA30, 0x10, 2, 1),
110 PIN_FIELD(30, 30, 0xA30, 0x10, 1, 1),
111 PIN_FIELD(31, 31, 0xA30, 0x10, 6, 1),
112 PIN_FIELD(32, 32, 0xA30, 0x10, 5, 1),
113 PIN_FIELD(33, 33, 0xA30, 0x10, 4, 1),
114 PIN_FIELD(34, 35, 0xA30, 0x10, 3, 1),
115 PIN_FIELD(36, 39, 0xA00, 0x10, 7, 1),
116 PIN_FIELD(40, 41, 0xA00, 0x10, 8, 1),
117 PIN_FIELD(42, 44, 0xA00, 0x10, 9, 1),
118 PIN_FIELD(45, 47, 0xA00, 0x10, 10, 1),
119 PIN_FIELD(48, 51, 0xA00, 0x10, 11, 1),
120 PIN_FIELD(52, 55, 0xA00, 0x10, 12, 1),
121 PIN_FIELD(56, 56, 0xA00, 0x10, 13, 1),
122 PIN_FIELD(57, 57, 0xA00, 0x10, 14, 1),
123 PIN_FIELD(58, 58, 0xA00, 0x10, 15, 1),
124 PIN_FIELD(59, 60, 0xA10, 0x10, 0, 1),
125
126 PIN_FIELD(61, 61, 0xA10, 0x10, 1, 1),
127 PIN_FIELD(62, 62, 0xA10, 0x10, 2, 1),
128 PIN_FIELD(63, 69, 0xA10, 0x10, 3, 1),
129 PIN_FIELD(70, 70, 0xA10, 0x10, 4, 1),
130 PIN_FIELD(71, 76, 0xA10, 0x10, 5, 1),
131 PIN_FIELD(77, 80, 0xA10, 0x10, 6, 1),
132 PIN_FIELD(81, 87, 0xA10, 0x10, 7, 1),
133 PIN_FIELD(88, 97, 0xA10, 0x10, 8, 1),
134 PIN_FIELD(98, 103, 0xA10, 0x10, 9, 1),
135 PIN_FIELD(104, 107, 0xA10, 0x10, 10, 1),
136 PIN_FIELD(108, 109, 0xA10, 0x10, 11, 1),
137 PIN_FIELD(110, 111, 0xA10, 0x10, 12, 1),
138 PIN_FIELD(112, 113, 0xA10, 0x10, 13, 1),
139 PIN_FIELD(114, 114, 0xA20, 0x10, 12, 1),
140 PIN_FIELD(115, 115, 0xA20, 0x10, 11, 1),
141 PIN_FIELD(116, 116, 0xA30, 0x10, 0, 1),
142 PIN_FIELD(117, 117, 0xA20, 0x10, 15, 1),
143 PIN_FIELD(118, 118, 0xA20, 0x10, 14, 1),
144 PIN_FIELD(119, 119, 0xA20, 0x10, 13, 1),
145};
146
147static const struct mtk_pin_field_calc mt8518_pin_pullen_range[] = {
148 PIN_FIELD(14, 15, 0x500, 0x10, 14, 1),
149 PIN_FIELD(16, 28, 0x510, 0x10, 0, 1),
150 PIN_FIELD(36, 47, 0x520, 0x10, 4, 1),
151 PIN_FIELD(48, 63, 0x530, 0x10, 0, 1),
152 PIN_FIELD(64, 79, 0x540, 0x10, 0, 1),
153 PIN_FIELD(80, 95, 0x550, 0x10, 0, 1),
154 PIN_FIELD(96, 111, 0x560, 0x10, 0, 1),
155 PIN_FIELD(112, 113, 0x570, 0x10, 0, 1),
156};
157
158static const struct mtk_pin_field_calc mt8518_pin_pullsel_range[] = {
159 PIN_FIELD(14, 15, 0x600, 0x10, 14, 1),
160 PIN_FIELD(16, 28, 0x610, 0x10, 0, 1),
161 PIN_FIELD(36, 47, 0x620, 0x10, 4, 1),
162 PIN_FIELD(48, 63, 0x630, 0x10, 0, 1),
163 PIN_FIELD(64, 79, 0x640, 0x10, 0, 1),
164 PIN_FIELD(80, 95, 0x650, 0x10, 0, 1),
165 PIN_FIELD(96, 111, 0x660, 0x10, 0, 1),
166 PIN_FIELD(112, 113, 0x670, 0x10, 0, 1),
167};
168
169static const struct mtk_pin_field_calc mt8518_pin_drv_range[] = {
170 PIN_FIELD(0, 2, 0xd70, 0x10, 8, 4),
171 PIN_FIELD(3, 6, 0xd70, 0x10, 0, 4),
172 PIN_FIELD(7, 7, 0xd70, 0x10, 4, 4),
173 PIN_FIELD(8, 8, 0xd60, 0x10, 8, 4),
174 PIN_FIELD(9, 9, 0xd60, 0x10, 12, 4),
175 PIN_FIELD(10, 13, 0xd70, 0x10, 0, 4),
176 PIN_FIELD(14, 14, 0xd50, 0x10, 8, 4),
177 PIN_FIELD(15, 15, 0xd20, 0x10, 4, 4),
178 PIN_FIELD(16, 16, 0xd50, 0x10, 8, 4),
179 PIN_FIELD(17, 20, 0xd20, 0x10, 12, 4),
180 PIN_FIELD(23, 27, 0xd30, 0x10, 8, 4),
181 PIN_FIELD(28, 28, 0xd10, 0x10, 0, 4),
182 PIN_FIELD(29, 29, 0xd40, 0x10, 12, 4),
183 PIN_FIELD(30, 30, 0xd50, 0x10, 0, 4),
184 PIN_FIELD(31, 35, 0xd50, 0x10, 4, 4),
185 PIN_FIELD(36, 41, 0xd00, 0x10, 0, 4),
186 PIN_FIELD(42, 47, 0xd00, 0x10, 4, 4),
187 PIN_FIELD(48, 51, 0xd00, 0x10, 8, 4),
188 PIN_FIELD(52, 55, 0xd10, 0x10, 12, 4),
189 PIN_FIELD(56, 56, 0xdb0, 0x10, 4, 4),
190 PIN_FIELD(57, 58, 0xd00, 0x10, 8, 4),
191 PIN_FIELD(59, 62, 0xd00, 0x10, 12, 4),
192 PIN_FIELD(63, 68, 0xd90, 0x10, 12, 4),
193 PIN_FIELD(69, 69, 0xda0, 0x10, 0, 4),
194 PIN_FIELD(70, 70, 0xda0, 0x10, 12, 4),
195 PIN_FIELD(71, 73, 0xd80, 0x10, 12, 4),
196 PIN_FIELD(74, 76, 0xd90, 0x10, 0, 4),
197 PIN_FIELD(77, 80, 0xd20, 0x10, 0, 4),
198 PIN_FIELD(81, 87, 0xd80, 0x10, 8, 4),
199 PIN_FIELD(88, 97, 0xd30, 0x10, 0, 4),
200 PIN_FIELD(98, 103, 0xd10, 0x10, 4, 4),
201 PIN_FIELD(104, 105, 0xd40, 0x10, 8, 4),
202 PIN_FIELD(106, 107, 0xd10, 0x10, 8, 4),
203 PIN_FIELD(114, 114, 0xd50, 0x10, 12, 4),
204 PIN_FIELD(115, 115, 0xd60, 0x10, 0, 4),
205 PIN_FIELD(116, 119, 0xd60, 0x10, 4, 4),
206};
207
208static const struct mtk_pin_reg_calc mt8518_reg_cals[] = {
209 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8518_pin_mode_range),
210 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8518_pin_dir_range),
211 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8518_pin_di_range),
212 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8518_pin_do_range),
213 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8518_pin_ies_range),
214 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8518_pin_smt_range),
215 [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8518_pin_pullsel_range),
216 [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8518_pin_pullen_range),
217 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8518_pin_drv_range),
218};
219
220static const struct mtk_pin_desc mt8518_pins[] = {
221 MTK_PIN(0, "NFI_NCEB0", DRV_GRP4),
222 MTK_PIN(1, "NFI_NREB", DRV_GRP4),
223 MTK_PIN(2, "NFI_NRNB", DRV_GRP4),
224 MTK_PIN(3, "MSDC0_DAT7", DRV_GRP4),
225 MTK_PIN(4, "MSDC0_DAT6", DRV_GRP4),
226 MTK_PIN(5, "MSDC0_DAT5", DRV_GRP4),
227 MTK_PIN(6, "MSDC0_DAT4", DRV_GRP4),
228 MTK_PIN(7, "MSDC0_RSTB", DRV_GRP4),
229 MTK_PIN(8, "MSDC0_CMD", DRV_GRP4),
230 MTK_PIN(9, "MSDC0_CLK", DRV_GRP4),
231 MTK_PIN(10, "MSDC0_DAT3", DRV_GRP4),
232 MTK_PIN(11, "MSDC0_DAT2", DRV_GRP4),
233 MTK_PIN(12, "MSDC0_DAT1", DRV_GRP4),
234 MTK_PIN(13, "MSDC0_DAT0", DRV_GRP4),
235 MTK_PIN(14, "RTC32K_CK", DRV_GRP2),
236 MTK_PIN(15, "WATCHDOG", DRV_GRP2),
237 MTK_PIN(16, "SUSPEND", DRV_GRP2),
238 MTK_PIN(17, "JTMS", DRV_GRP2),
239 MTK_PIN(18, "JTCK", DRV_GRP2),
240 MTK_PIN(19, "JTDI", DRV_GRP2),
241 MTK_PIN(20, "JTDO", DRV_GRP2),
242 MTK_PIN(21, "SDA3", DRV_GRP2),
243 MTK_PIN(22, "SCL3", DRV_GRP2),
244 MTK_PIN(23, "PWRAP_SPI_CLK", DRV_GRP2),
245 MTK_PIN(24, "PWRAP_SPI_CSN", DRV_GRP2),
246 MTK_PIN(25, "PWRAP_SPI_MOSI", DRV_GRP2),
247 MTK_PIN(26, "PWRAP_SPI_MISO", DRV_GRP2),
248 MTK_PIN(27, "PWRAP_INT", DRV_GRP2),
249 MTK_PIN(28, "EINT22", DRV_GRP2),
250 MTK_PIN(29, "MSDC2_CMD", DRV_GRP4),
251 MTK_PIN(30, "MSDC2_CLK", DRV_GRP4),
252 MTK_PIN(31, "MSDC2_DAT0", DRV_GRP4),
253 MTK_PIN(32, "MSDC2_DAT1", DRV_GRP4),
254 MTK_PIN(33, "MSDC2_DAT2", DRV_GRP4),
255 MTK_PIN(34, "MSDC2_DAT3", DRV_GRP4),
256 MTK_PIN(35, "MSDC2_DS", DRV_GRP4),
257 MTK_PIN(36, "EINT0", DRV_GRP0),
258 MTK_PIN(37, "EINT1", DRV_GRP0),
259 MTK_PIN(38, "EINT2", DRV_GRP0),
260 MTK_PIN(39, "EINT3", DRV_GRP0),
261 MTK_PIN(40, "EINT4", DRV_GRP0),
262 MTK_PIN(41, "EINT5", DRV_GRP0),
263 MTK_PIN(42, "EINT6", DRV_GRP0),
264 MTK_PIN(43, "EINT7", DRV_GRP0),
265 MTK_PIN(44, "EINT8", DRV_GRP0),
266 MTK_PIN(45, "EINT9", DRV_GRP0),
267 MTK_PIN(46, "EINT10", DRV_GRP0),
268 MTK_PIN(47, "EINT11", DRV_GRP0),
269 MTK_PIN(48, "EINT12", DRV_GRP0),
270 MTK_PIN(49, "EINT13", DRV_GRP0),
271 MTK_PIN(50, "EINT14", DRV_GRP0),
272 MTK_PIN(51, "EINT15", DRV_GRP0),
273 MTK_PIN(52, "URXD1", DRV_GRP0),
274 MTK_PIN(53, "UTXD1", DRV_GRP0),
275 MTK_PIN(54, "URTS1", DRV_GRP0),
276 MTK_PIN(55, "UCTS1", DRV_GRP0),
277 MTK_PIN(56, "IR", DRV_GRP0),
278 MTK_PIN(57, "EINT16", DRV_GRP0),
279 MTK_PIN(58, "EINT17", DRV_GRP0),
280 MTK_PIN(59, "EINT18", DRV_GRP0),
281 MTK_PIN(60, "EINT19", DRV_GRP0),
282 MTK_PIN(61, "EINT20", DRV_GRP0),
283 MTK_PIN(62, "EINT21", DRV_GRP0),
284 MTK_PIN(63, "I2SO_MCLK", DRV_GRP0),
285 MTK_PIN(64, "I2SO_BCK", DRV_GRP0),
286 MTK_PIN(65, "I2SO_LRCK", DRV_GRP0),
287 MTK_PIN(66, "I2SO_D0", DRV_GRP0),
288 MTK_PIN(67, "I2SO_D1", DRV_GRP0),
289 MTK_PIN(68, "I2SO_D2", DRV_GRP0),
290 MTK_PIN(69, "I2SO_D3", DRV_GRP0),
291 MTK_PIN(70, "SPDIF_IN0", DRV_GRP0),
292 MTK_PIN(71, "DMIC_CLK0", DRV_GRP0),
293 MTK_PIN(72, "DMIC_CLK1", DRV_GRP0),
294 MTK_PIN(73, "DMIC_DAT0", DRV_GRP0),
295 MTK_PIN(74, "DMIC_DAT1", DRV_GRP0),
296 MTK_PIN(75, "DMIC_DAT2", DRV_GRP0),
297 MTK_PIN(76, "DMIC_DAT3", DRV_GRP0),
298 MTK_PIN(77, "TDM_MCLK", DRV_GRP0),
299 MTK_PIN(78, "TDM_BCK", DRV_GRP0),
300 MTK_PIN(79, "TDM_LRCK", DRV_GRP0),
301 MTK_PIN(80, "TDM_DI", DRV_GRP0),
302 MTK_PIN(81, "I2SIN_D0", DRV_GRP0),
303 MTK_PIN(82, "I2SIN_D1", DRV_GRP0),
304 MTK_PIN(83, "I2SIN_D2", DRV_GRP0),
305 MTK_PIN(84, "I2SIN_D3", DRV_GRP0),
306 MTK_PIN(85, "I2SIN_MCLK", DRV_GRP0),
307 MTK_PIN(86, "I2SIN_BCK", DRV_GRP0),
308 MTK_PIN(87, "I2SIN_LRCK", DRV_GRP0),
309 MTK_PIN(88, "SPI1_CS", DRV_GRP0),
310 MTK_PIN(89, "SPI1_CK", DRV_GRP0),
311 MTK_PIN(90, "SPI1_MI", DRV_GRP0),
312 MTK_PIN(91, "SPI1_MO", DRV_GRP0),
313 MTK_PIN(92, "SPI2_CS", DRV_GRP0),
314 MTK_PIN(93, "SPI2_CK", DRV_GRP0),
315 MTK_PIN(94, "SPI2_MI0", DRV_GRP0),
316 MTK_PIN(95, "SPI2_MI1", DRV_GRP0),
317 MTK_PIN(96, "SPI2_MI2", DRV_GRP0),
318 MTK_PIN(97, "SPI2_MI3", DRV_GRP0),
319 MTK_PIN(98, "SW_RESET_DSP", DRV_GRP0),
320 MTK_PIN(99, "GPIO1", DRV_GRP0),
321 MTK_PIN(100, "GPIO2", DRV_GRP0),
322 MTK_PIN(101, "GPIO3", DRV_GRP0),
323 MTK_PIN(102, "GPIO4", DRV_GRP0),
324 MTK_PIN(103, "RTC32K_DSP", DRV_GRP0),
325 MTK_PIN(104, "URXD0", DRV_GRP2),
326 MTK_PIN(105, "UTXD0", DRV_GRP2),
327 MTK_PIN(106, "URXD2", DRV_GRP2),
328 MTK_PIN(107, "UTXD2", DRV_GRP2),
329 MTK_PIN(108, "SDA1", DRV_GRP4),
330 MTK_PIN(109, "SCL1", DRV_GRP4),
331 MTK_PIN(110, "SDA0", DRV_GRP4),
332 MTK_PIN(111, "SCL0", DRV_GRP4),
333 MTK_PIN(112, "SDA2", DRV_GRP4),
334 MTK_PIN(113, "SCL2", DRV_GRP4),
335 MTK_PIN(114, "MSDC1_CMD", DRV_GRP4),
336 MTK_PIN(115, "MSDC1_CLK", DRV_GRP4),
337 MTK_PIN(116, "MSDC1_DAT0", DRV_GRP4),
338 MTK_PIN(117, "MSDC1_DAT1", DRV_GRP4),
339 MTK_PIN(118, "MSDC1_DAT2", DRV_GRP4),
340 MTK_PIN(119, "MSDC1_DAT3", DRV_GRP4),
341};
342
343/* List all groups consisting of these pins dedicated to the enablement of
344 * certain hardware block and the corresponding mode for all of the pins.
345 * The hardware probably has multiple combinations of these pinouts.
346 */
347
348/* UART */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]349static const int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, };
350static const int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, };
351static const int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, };
352static const int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, };
353static const int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, };
354static const int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, };
developerc3aeb812019-11-07 19:28:43 +0800[diff] [blame]355
356/* Joint those groups owning the same capability in user point of view which
357 * allows that people tend to use through the device tree.
358 */
359static const char *const mt8518_uart_groups[] = { "uart0_0_rxd_txd",
360 "uart1_0_rxd_txd",
361 "uart2_0_rxd_txd", };
362
363/* MMC0 */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]364static const int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
365 12, 13, };
366static const int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
developerc3aeb812019-11-07 19:28:43 +0800[diff] [blame]367
368static const struct mtk_group_desc mt8518_groups[] = {
369 PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd),
370 PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8518_uart1_0_rxd_txd),
371 PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8518_uart2_0_rxd_txd),
372
373 PINCTRL_PIN_GROUP("msdc0", mt8518_msdc0),
374};
375
376static const char *const mt8518_msdc_groups[] = { "msdc0" };
377
378static const struct mtk_function_desc mt8518_functions[] = {
379 {"uart", mt8518_uart_groups, ARRAY_SIZE(mt8518_uart_groups)},
380 {"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)},
381};
382
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]383static const struct mtk_pinctrl_soc mt8518_data = {
developerc3aeb812019-11-07 19:28:43 +0800[diff] [blame]384 .name = "mt8518_pinctrl",
385 .reg_cal = mt8518_reg_cals,
386 .pins = mt8518_pins,
387 .npins = ARRAY_SIZE(mt8518_pins),
388 .grps = mt8518_groups,
389 .ngrps = ARRAY_SIZE(mt8518_groups),
390 .funcs = mt8518_functions,
391 .nfuncs = ARRAY_SIZE(mt8518_functions),
developer74d69012020-01-10 16:30:28 +0800[diff] [blame]392 .gpio_mode = 0,
393 .rev = MTK_PINCTRL_V1,
developerc3aeb812019-11-07 19:28:43 +0800[diff] [blame]394};
395
396static int mtk_pinctrl_mt8518_probe(struct udevice *dev)
397{
398 return mtk_pinctrl_common_probe(dev, &mt8518_data);
399}
400
401static const struct udevice_id mt8518_pctrl_match[] = {
402 { .compatible = "mediatek,mt8518-pinctrl" },
403 { /* sentinel */ }
404};
405
406U_BOOT_DRIVER(mt8518_pinctrl) = {
407 .name = "mt8518_pinctrl",
408 .id = UCLASS_PINCTRL,
409 .of_match = mt8518_pctrl_match,
410 .ops = &mtk_pinctrl_ops,
411 .probe = mtk_pinctrl_mt8518_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]412 .priv_auto = sizeof(struct mtk_pinctrl_priv),
developerc3aeb812019-11-07 19:28:43 +0800[diff] [blame]413};