blob: cdb088c9b153d2f24787a3da6f05cc3a4575fe99 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk1fe2c702003-03-06 21:55:29 +00002/*
3 * (C) Copyright 2001, 2002, 2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Keith Outwater, keith_outwater@mvis.com`
6 * Steven Scholz, steven.scholz@imc-berlin.de
wdenk1fe2c702003-03-06 21:55:29 +00007 */
8
9/*
10 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
Markus Niebel90491f22014-07-21 11:06:16 +020011 * DS1307 and DS1338/9 Real Time Clock (RTC).
wdenk1fe2c702003-03-06 21:55:29 +000012 *
13 * based on ds1337.c
14 */
15
16#include <common.h>
17#include <command.h>
Chris Packham97a3e912017-04-29 15:20:29 +120018#include <dm.h>
wdenk1fe2c702003-03-06 21:55:29 +000019#include <rtc.h>
20#include <i2c.h>
21
Chris Packham97a3e912017-04-29 15:20:29 +120022enum ds_type {
23 ds_1307,
24 ds_1337,
25 ds_1340,
26 mcp794xx,
27};
wdenk1fe2c702003-03-06 21:55:29 +000028
29/*
30 * RTC register addresses
31 */
32#define RTC_SEC_REG_ADDR 0x00
33#define RTC_MIN_REG_ADDR 0x01
34#define RTC_HR_REG_ADDR 0x02
35#define RTC_DAY_REG_ADDR 0x03
36#define RTC_DATE_REG_ADDR 0x04
37#define RTC_MON_REG_ADDR 0x05
38#define RTC_YR_REG_ADDR 0x06
39#define RTC_CTL_REG_ADDR 0x07
40
41#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
42
43#define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */
44#define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */
45#define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */
46#define RTC_CTL_BIT_OUT 0x80 /* Output Control */
47
Andy Flemingb9b8c2f2015-10-21 18:59:06 -050048/* MCP7941X-specific bits */
49#define MCP7941X_BIT_ST 0x80
50#define MCP7941X_BIT_VBATEN 0x08
51
Chris Packham97a3e912017-04-29 15:20:29 +120052#ifndef CONFIG_DM_RTC
53
54#if defined(CONFIG_CMD_DATE)
55
56/*---------------------------------------------------------------------*/
57#undef DEBUG_RTC
58
59#ifdef DEBUG_RTC
60#define DEBUGR(fmt, args...) printf(fmt, ##args)
61#else
62#define DEBUGR(fmt, args...)
63#endif
64/*---------------------------------------------------------------------*/
65
66#ifndef CONFIG_SYS_I2C_RTC_ADDR
67# define CONFIG_SYS_I2C_RTC_ADDR 0x68
68#endif
69
70#if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000)
71# error The DS1307 is specified only up to 100kHz!
72#endif
73
wdenk1fe2c702003-03-06 21:55:29 +000074static uchar rtc_read (uchar reg);
75static void rtc_write (uchar reg, uchar val);
wdenk1fe2c702003-03-06 21:55:29 +000076
77/*
78 * Get the current time from the RTC
79 */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030080int rtc_get (struct rtc_time *tmp)
wdenk1fe2c702003-03-06 21:55:29 +000081{
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030082 int rel = 0;
wdenk1fe2c702003-03-06 21:55:29 +000083 uchar sec, min, hour, mday, wday, mon, year;
84
Andy Flemingb9b8c2f2015-10-21 18:59:06 -050085#ifdef CONFIG_RTC_MCP79411
86read_rtc:
87#endif
wdenk1fe2c702003-03-06 21:55:29 +000088 sec = rtc_read (RTC_SEC_REG_ADDR);
89 min = rtc_read (RTC_MIN_REG_ADDR);
90 hour = rtc_read (RTC_HR_REG_ADDR);
91 wday = rtc_read (RTC_DAY_REG_ADDR);
92 mday = rtc_read (RTC_DATE_REG_ADDR);
93 mon = rtc_read (RTC_MON_REG_ADDR);
94 year = rtc_read (RTC_YR_REG_ADDR);
95
96 DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
97 "hr: %02x min: %02x sec: %02x\n",
98 year, mon, mday, wday, hour, min, sec);
99
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500100#ifdef CONFIG_RTC_DS1307
wdenk1fe2c702003-03-06 21:55:29 +0000101 if (sec & RTC_SEC_BIT_CH) {
102 printf ("### Warning: RTC oscillator has stopped\n");
103 /* clear the CH flag */
104 rtc_write (RTC_SEC_REG_ADDR,
105 rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300106 rel = -1;
wdenk1fe2c702003-03-06 21:55:29 +0000107 }
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500108#endif
109
110#ifdef CONFIG_RTC_MCP79411
111 /* make sure that the backup battery is enabled */
112 if (!(wday & MCP7941X_BIT_VBATEN)) {
113 rtc_write(RTC_DAY_REG_ADDR,
114 wday | MCP7941X_BIT_VBATEN);
115 }
wdenk57b2d802003-06-27 21:31:46 +0000116
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500117 /* clock halted? turn it on, so clock can tick. */
118 if (!(sec & MCP7941X_BIT_ST)) {
119 rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST);
120 printf("Started RTC\n");
121 goto read_rtc;
122 }
123#endif
124
125
wdenk1fe2c702003-03-06 21:55:29 +0000126 tmp->tm_sec = bcd2bin (sec & 0x7F);
127 tmp->tm_min = bcd2bin (min & 0x7F);
128 tmp->tm_hour = bcd2bin (hour & 0x3F);
129 tmp->tm_mday = bcd2bin (mday & 0x3F);
130 tmp->tm_mon = bcd2bin (mon & 0x1F);
131 tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
132 tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
133 tmp->tm_yday = 0;
134 tmp->tm_isdst= 0;
135
136 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
137 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
138 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300139
140 return rel;
wdenk1fe2c702003-03-06 21:55:29 +0000141}
142
143
144/*
145 * Set the RTC
146 */
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200147int rtc_set (struct rtc_time *tmp)
wdenk1fe2c702003-03-06 21:55:29 +0000148{
149 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
150 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
151 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
152
153 if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
154 printf("WARNING: year should be between 1970 and 2069!\n");
wdenk57b2d802003-06-27 21:31:46 +0000155
wdenk1fe2c702003-03-06 21:55:29 +0000156 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
157 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500158#ifdef CONFIG_RTC_MCP79411
159 rtc_write (RTC_DAY_REG_ADDR,
160 bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN);
161#else
wdenk1fe2c702003-03-06 21:55:29 +0000162 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500163#endif
wdenk1fe2c702003-03-06 21:55:29 +0000164 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
165 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
166 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500167#ifdef CONFIG_RTC_MCP79411
168 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST);
169#else
wdenk1fe2c702003-03-06 21:55:29 +0000170 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500171#endif
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200172
173 return 0;
wdenk1fe2c702003-03-06 21:55:29 +0000174}
175
176
177/*
wdenk57b2d802003-06-27 21:31:46 +0000178 * Reset the RTC. We setting the date back to 1970-01-01.
179 * We also enable the oscillator output on the SQW/OUT pin and program
wdenk1fe2c702003-03-06 21:55:29 +0000180 * it for 32,768 Hz output. Note that according to the datasheet, turning
181 * on the square wave output increases the current drain on the backup
182 * battery to something between 480nA and 800nA.
183 */
184void rtc_reset (void)
185{
wdenk1fe2c702003-03-06 21:55:29 +0000186 rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
187 rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0);
wdenk1fe2c702003-03-06 21:55:29 +0000188}
189
190
191/*
192 * Helper functions
193 */
194
195static
196uchar rtc_read (uchar reg)
197{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
wdenk1fe2c702003-03-06 21:55:29 +0000199}
200
201
202static void rtc_write (uchar reg, uchar val)
203{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
wdenk1fe2c702003-03-06 21:55:29 +0000205}
Chris Packham97a3e912017-04-29 15:20:29 +1200206
207#endif /* CONFIG_CMD_DATE*/
208
209#endif /* !CONFIG_DM_RTC */
210
211#ifdef CONFIG_DM_RTC
212static int ds1307_rtc_set(struct udevice *dev, const struct rtc_time *tm)
213{
214 int ret;
215 uchar buf[7];
216 enum ds_type type = dev_get_driver_data(dev);
217
218 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
219 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
220 tm->tm_hour, tm->tm_min, tm->tm_sec);
221
222 if (tm->tm_year < 1970 || tm->tm_year > 2069)
223 printf("WARNING: year should be between 1970 and 2069!\n");
224
225 buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100);
226 buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon);
227 buf[RTC_DAY_REG_ADDR] = bin2bcd(tm->tm_wday + 1);
228 buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday);
229 buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour);
230 buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min);
231 buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec);
232
233 if (type == mcp794xx) {
234 buf[RTC_DAY_REG_ADDR] |= MCP7941X_BIT_VBATEN;
235 buf[RTC_SEC_REG_ADDR] |= MCP7941X_BIT_ST;
236 }
237
238 ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
239 if (ret < 0)
240 return ret;
241
242 return 0;
243}
244
245static int ds1307_rtc_get(struct udevice *dev, struct rtc_time *tm)
246{
247 int ret;
248 uchar buf[7];
249 enum ds_type type = dev_get_driver_data(dev);
250
251read_rtc:
252 ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
253 if (ret < 0)
254 return ret;
255
256 if (type == ds_1307) {
257 if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
258 printf("### Warning: RTC oscillator has stopped\n");
259 /* clear the CH flag */
260 buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
261 dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
262 buf[RTC_SEC_REG_ADDR]);
263 return -1;
264 }
265 }
266
267 if (type == mcp794xx) {
268 /* make sure that the backup battery is enabled */
269 if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) {
270 dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR,
271 buf[RTC_DAY_REG_ADDR] |
272 MCP7941X_BIT_VBATEN);
273 }
274
275 /* clock halted? turn it on, so clock can tick. */
276 if (!(buf[RTC_SEC_REG_ADDR] & MCP7941X_BIT_ST)) {
277 dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
278 MCP7941X_BIT_ST);
279 printf("Started RTC\n");
280 goto read_rtc;
281 }
282 }
283
284 tm->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
285 tm->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
286 tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
287 tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
288 tm->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
289 tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) +
290 (bcd2bin(buf[RTC_YR_REG_ADDR]) >= 70 ?
291 1900 : 2000);
292 tm->tm_wday = bcd2bin((buf[RTC_DAY_REG_ADDR] - 1) & 0x07);
293 tm->tm_yday = 0;
294 tm->tm_isdst = 0;
295
296 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
297 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
298 tm->tm_hour, tm->tm_min, tm->tm_sec);
299
300 return 0;
301}
302
303static int ds1307_rtc_reset(struct udevice *dev)
304{
305 int ret;
Chris Packham97a3e912017-04-29 15:20:29 +1200306
307 /* clear Clock Halt */
308 ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00);
309 if (ret < 0)
310 return ret;
311 ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
312 RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 |
313 RTC_CTL_BIT_RS0);
314 if (ret < 0)
315 return ret;
316
Chris Packham97a3e912017-04-29 15:20:29 +1200317 return 0;
318}
319
320static int ds1307_probe(struct udevice *dev)
321{
322 i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
323 DM_I2C_CHIP_WR_ADDRESS);
324
325 return 0;
326}
327
328static const struct rtc_ops ds1307_rtc_ops = {
329 .get = ds1307_rtc_get,
330 .set = ds1307_rtc_set,
331 .reset = ds1307_rtc_reset,
332};
333
334static const struct udevice_id ds1307_rtc_ids[] = {
335 { .compatible = "dallas,ds1307", .data = ds_1307 },
336 { .compatible = "dallas,ds1337", .data = ds_1337 },
337 { .compatible = "dallas,ds1340", .data = ds_1340 },
338 { .compatible = "microchip,mcp7941x", .data = mcp794xx },
339 { }
340};
341
342U_BOOT_DRIVER(rtc_ds1307) = {
343 .name = "rtc-ds1307",
344 .id = UCLASS_RTC,
345 .probe = ds1307_probe,
346 .of_match = ds1307_rtc_ids,
347 .ops = &ds1307_rtc_ops,
348};
349#endif /* CONFIG_DM_RTC */