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Hao Zhangeb01de22014-07-09 23:44:48 +03001/*
2 * Common configuration header file for all Keystone II EVM platforms
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_KS2_EVM_H
11#define __CONFIG_KS2_EVM_H
12
13#define CONFIG_SOC_KEYSTONE
14
15/* U-Boot Build Configuration */
16#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
17#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
18#define CONFIG_SYS_CONSOLE_INFO_QUIET
19#define CONFIG_BOARD_EARLY_INIT_F
20#define CONFIG_SYS_THUMB_BUILD
21
22/* SoC Configuration */
23#define CONFIG_ARMV7
24#define CONFIG_ARCH_CPU_INIT
25#define CONFIG_SYS_ARCH_TIMER
26#define CONFIG_SYS_HZ 1000
27#define CONFIG_SYS_TEXT_BASE 0x0c001000
28#define CONFIG_SPL_TARGET "u-boot-spi.gph"
29#define CONFIG_SYS_DCACHE_OFF
30
31/* Memory Configuration */
32#define CONFIG_NR_DRAM_BANKS 2
33#define CONFIG_SYS_SDRAM_BASE 0x80000000
34#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
35#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
36#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
37#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */
38#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
39 GENERATED_GBL_DATA_SIZE)
40
41/* SPL SPI Loader Configuration */
42#define CONFIG_SPL_PAD_TO 65536
43#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
44#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
45 CONFIG_SPL_MAX_SIZE)
46#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
47#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
48 CONFIG_SPL_BSS_MAX_SIZE)
49#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
50#define CONFIG_SPL_STACK_SIZE (8 * 1024)
51#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
52 CONFIG_SYS_SPL_MALLOC_SIZE + \
53 CONFIG_SPL_STACK_SIZE - 4)
54#define CONFIG_SPL_LIBCOMMON_SUPPORT
55#define CONFIG_SPL_LIBGENERIC_SUPPORT
56#define CONFIG_SPL_SERIAL_SUPPORT
57#define CONFIG_SPL_SPI_FLASH_SUPPORT
58#define CONFIG_SPL_SPI_SUPPORT
59#define CONFIG_SPL_BOARD_INIT
60#define CONFIG_SPL_SPI_LOAD
Hao Zhangeb01de22014-07-09 23:44:48 +030061#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
62#define CONFIG_SPL_FRAMEWORK
63
64/* UART Configuration */
65#define CONFIG_SYS_NS16550
66#define CONFIG_SYS_NS16550_SERIAL
67#define CONFIG_SYS_NS16550_MEM32
68#define CONFIG_SYS_NS16550_REG_SIZE -4
69#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
70#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
71#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
72#define CONFIG_CONS_INDEX 1
73#define CONFIG_BAUDRATE 115200
74
75/* SPI Configuration */
76#define CONFIG_SPI
77#define CONFIG_SPI_FLASH
78#define CONFIG_SPI_FLASH_STMICRO
79#define CONFIG_DAVINCI_SPI
80#define CONFIG_CMD_SPI
Hao Zhang0ecd31e2014-07-16 00:59:23 +030081#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
Hao Zhangeb01de22014-07-09 23:44:48 +030082#define CONFIG_SF_DEFAULT_SPEED 30000000
83#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
84#define CONFIG_SYS_SPI0
85#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE
86#define CONFIG_SYS_SPI0_NUM_CS 4
87#define CONFIG_SYS_SPI1
88#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
89#define CONFIG_SYS_SPI1_NUM_CS 4
90#define CONFIG_SYS_SPI2
91#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
92#define CONFIG_SYS_SPI2_NUM_CS 4
93
94/* Network Configuration */
95#define CONFIG_MII
96#define CONFIG_BOOTP_DEFAULT
97#define CONFIG_BOOTP_DNS
98#define CONFIG_BOOTP_DNS2
99#define CONFIG_BOOTP_SEND_HOSTNAME
100#define CONFIG_NET_RETRY_COUNT 32
101#define CONFIG_NET_MULTI
102#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5
103#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
104#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
105#define CONFIG_SYS_SGMII_RATESCALE 2
106
107/* AEMIF */
108#define CONFIG_TI_AEMIF
109#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
110
111/* I2C Configuration */
112#define CONFIG_SYS_I2C
113#define CONFIG_SYS_I2C_DAVINCI
114#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
115#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
116#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
117#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
118#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
119#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
120#define I2C_BUS_MAX 3
121
122/* EEPROM definitions */
123#define CONFIG_SYS_I2C_MULTI_EEPROMS
124#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
125#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
126#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
127#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
128#define CONFIG_ENV_EEPROM_IS_ON_I2C
129
130/* NAND Configuration */
131#define CONFIG_NAND_DAVINCI
132#define CONFIG_KEYSTONE_RBL_NAND
133#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
134#define CONFIG_SYS_NAND_MASK_CLE 0x4000
135#define CONFIG_SYS_NAND_MASK_ALE 0x2000
136#define CONFIG_SYS_NAND_CS 2
137#define CONFIG_SYS_NAND_USE_FLASH_BBT
138#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
139
140#define CONFIG_SYS_NAND_LARGEPAGE
141#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
142#define CONFIG_SYS_MAX_NAND_DEVICE 1
143#define CONFIG_SYS_NAND_MAX_CHIPS 1
144#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
145#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
146#define CONFIG_ENV_IS_IN_NAND
147#define CONFIG_ENV_OFFSET 0x100000
148#define CONFIG_MTD_PARTITIONS
149#define CONFIG_MTD_DEVICE
150#define CONFIG_RBTREE
151#define CONFIG_LZO
152#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
153#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
154 "1024k(bootloader)ro,512k(params)ro," \
155 "-(ubifs)"
156
157/* U-Boot command configuration */
158#include <config_cmd_default.h>
159#define CONFIG_CMD_ASKENV
160#define CONFIG_CMD_DHCP
161#define CONFIG_CMD_I2C
162#define CONFIG_CMD_PING
163#define CONFIG_CMD_SAVES
164#define CONFIG_CMD_MTDPARTS
165#define CONFIG_CMD_NAND
166#define CONFIG_CMD_UBI
167#define CONFIG_CMD_UBIFS
168#define CONFIG_CMD_SF
169#define CONFIG_CMD_EEPROM
170
171/* U-Boot general configuration */
172#define CONFIG_SYS_GENERIC_BOARD
173#define CONFIG_SYS_CBSIZE 1024
174#define CONFIG_SYS_PBSIZE 2048
175#define CONFIG_SYS_MAXARGS 16
176#define CONFIG_SYS_HUSH_PARSER
177#define CONFIG_SYS_LONGHELP
178#define CONFIG_CRC32_VERIFY
179#define CONFIG_MX_CYCLIC
180#define CONFIG_CMDLINE_EDITING
181#define CONFIG_VERSION_VARIABLE
182#define CONFIG_TIMESTAMP
183
184/* EDMA3 */
185#define CONFIG_TI_EDMA3
186
187#define CONFIG_BOOTDELAY 3
188#define CONFIG_BOOTFILE "uImage"
189#define CONFIG_EXTRA_ENV_SETTINGS \
190 "boot=ramfs\0" \
191 "tftp_root=/\0" \
192 "nfs_root=/export\0" \
193 "mem_lpae=1\0" \
194 "mem_reserve=512M\0" \
195 "addr_fdt=0x87000000\0" \
196 "addr_kern=0x88000000\0" \
197 KS2_ADDR_MON \
198 "addr_uboot=0x87000000\0" \
199 "addr_fs=0x82000000\0" \
200 "addr_ubi=0x82000000\0" \
201 "addr_secdb_key=0xc000000\0" \
202 "fdt_high=0xffffffff\0" \
203 KS2_FDT_NAME \
204 "name_fs=arago-console-image.cpio.gz\0" \
205 "name_kern=uImage\0" \
206 KS2_NAME_MON \
207 NAME_UBOOT \
208 NAME_UBI \
209 "run_mon=mon_install ${addr_mon}\0" \
210 "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
211 "init_net=run args_all args_net\0" \
212 "init_ubi=run args_all args_ubi; " \
213 "ubi part ubifs; ubifsmount boot;" \
214 "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \
215 "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
216 "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
217 "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
218 "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \
219 "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
220 "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
221 "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \
222 "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
223 "sf write ${addr_uboot} 0 ${filesize}\0" \
224 "burn_uboot_nand=nand erase 0 0x100000; " \
225 "nand write ${addr_uboot} 0 ${filesize}\0" \
226 "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
227 KS2_ARGS_UBI \
228 "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
229 "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
230 "${nfs_options} ip=dhcp\0" \
231 "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
232 "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
233 "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
234 "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
235 "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \
236 "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
237 "burn_ubi=nand erase.part ubifs; " \
238 "nand write ${addr_ubi} ubifs ${filesize}\0" \
239 "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
240 "args_ramfs=setenv bootargs ${bootargs} " \
241 "rdinit=/sbin/init rw root=/dev/ram0 " \
242 "initrd=0x802000000,9M\0" \
243 "no_post=1\0" \
244 "mtdparts=mtdparts=davinci_nand.0:" \
245 "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
246
247#define CONFIG_BOOTCOMMAND \
248 "run init_${boot} get_fdt_${boot} get_mon_${boot} " \
249 "get_kern_${boot} run_mon run_kern"
250
251#define CONFIG_BOOTARGS \
252
253/* Linux interfacing */
254#define CONFIG_CMDLINE_TAG
255#define CONFIG_SETUP_MEMORY_TAGS
256#define CONFIG_OF_LIBFDT 1
257#define CONFIG_OF_BOARD_SETUP
258#define CONFIG_SYS_BARGSIZE 1024
259#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
260#define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
261
262#define CONFIG_SUPPORT_RAW_INITRD
263
264/* we may include files below only after all above definitions */
265#include <asm/arch/hardware.h>
266#include <asm/arch/clock.h>
267#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
268
269/* Maximum memory size for relocated U-boot at the end of the DDR3 memory
270 which is NOT applicable for DDR ECC test */
271#define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */
272
273#endif /* __CONFIG_KS2_EVM_H */