Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 26dc25bad3952204705b4f9893759bab9dc9c6cc / . / board / tqc / tqm8260 / tqm8260.c
blob: c361f188f79e55d027bb029ef9ea49315af9281a [file] [log] [blame]
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]6 */
7
8#include <common.h>
9#include <ioports.h>
10#include <mpc8260.h>
11
12/*
13 * I/O Port configuration table
14 *
15 * if conf is 1, then that port pin will be configured at boot time
16 * according to the five values podr/pdir/ppar/psor/pdat for that entry
17 */
18
19const iop_conf_t iop_conf_tab[4][32] = {
20
21 /* Port A configuration */
22 { /* conf ppar psor pdir podr pdat */
23 /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
24 /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
25 /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
26 /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
27 /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
28 /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
29 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
30 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
31 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
32 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
33 /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
34 /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
35 /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
36 /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
37 /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
38 /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
39 /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
40 /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
41 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
42 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
43 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
44 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
45 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
46 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
47 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
48 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
49 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
50 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
51 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
52 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
53 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
54 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
55 },
56
57 /* Port B configuration */
58 { /* conf ppar psor pdir podr pdat */
59 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
60 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
61 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
62 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
63 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
64 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
65 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
66 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
67 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
68 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
69 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
70 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
71 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
72 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
73 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
74 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
75 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
76 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
77 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
78 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
79 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
80 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
81 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
82 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
83 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
84 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
85 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
86 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
87 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
88 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
89 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
90 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
91 },
92
93 /* Port C */
94 { /* conf ppar psor pdir podr pdat */
95 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
96 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
97 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
98 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
99 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
100 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
101 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
102 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
103 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
104 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
105 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
106 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
107 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
108 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
109 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
110 /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
111 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
112 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
113 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
114 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
115 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
116 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
117 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
118 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
119 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
120 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
121 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
122 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
123 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
124 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
125 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
126 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
127 },
128
129 /* Port D */
130 { /* conf ppar psor pdir podr pdat */
131 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
132 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
133 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
134 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
135 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
136 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
137 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
138 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
139 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
140 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
141 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
142 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
143 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
144 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
145 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
146 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100[diff] [blame]147#if defined(CONFIG_SYS_I2C_SOFT)
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]148 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
149 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
150#else
151#if defined(CONFIG_HARD_I2C)
152 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
153 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
154#else /* normal I/O port pins */
155 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
156 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
157#endif
158#endif
159 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
160 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
161 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
162 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
163 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
164 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
165 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
166 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
167 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
168 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
169 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
170 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
171 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
172 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
173 }
174};
175
176/* ------------------------------------------------------------------------- */
177
178/* Check Board Identity:
179 */
180int checkboard (void)
181{
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +0000[diff] [blame]182 char buf[64];
183 int i = getenv_f("serial#", buf, sizeof(buf));
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]184
185 puts ("Board: ");
186
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +0000[diff] [blame]187 if (i < 0 || strncmp(buf, "TQM82", 5)) {
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]188 puts ("### No HW ID - assuming TQM8260\n");
wdenkbb444c92002-12-07 00:20:59 +0000[diff] [blame]189 return (0);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]190 }
191
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +0000[diff] [blame]192 puts (buf);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]193 putc ('\n');
194
195 return 0;
196}
197
198/* ------------------------------------------------------------------------- */
199
200/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
201 *
202 * This routine performs standard 8260 initialization sequence
203 * and calculates the available memory size. It may be called
204 * several times to try different SDRAM configurations on both
205 * 60x and local buses.
206 */
207static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
208 ulong orx, volatile uchar * base)
209{
210 volatile uchar c = 0xff;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]211 volatile uint *sdmr_ptr;
212 volatile uint *orx_ptr;
wdenkb6c60cb32003-10-29 23:18:55 +0000[diff] [blame]213 ulong maxsize, size;
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]214 int i;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]215
216 /* We must be able to test a location outsize the maximum legal size
217 * to find out THAT we are outside; but this address still has to be
218 * mapped by the controller. That means, that the initial mapping has
219 * to be (at least) twice as large as the maximum expected size.
220 */
221 maxsize = (1 + (~orx | 0x7fff)) / 2;
222
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]223 /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]224 * we are configuring CS1 if base != 0
225 */
226 sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
227 orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
228
229 *orx_ptr = orx;
230
231 /*
232 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
233 *
234 * "At system reset, initialization software must set up the
235 * programmable parameters in the memory controller banks registers
236 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
237 * system software should execute the following initialization sequence
238 * for each SDRAM device.
239 *
240 * 1. Issue a PRECHARGE-ALL-BANKS command
241 * 2. Issue eight CBR REFRESH commands
242 * 3. Issue a MODE-SET command to initialize the mode register
243 *
244 * The initial commands are executed by setting P/LSDMR[OP] and
245 * accessing the SDRAM with a single-byte transaction."
246 *
247 * The appropriate BRx/ORx registers have already been set when we
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]248 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]249 */
250
251 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
252 *base = c;
253
254 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
255 for (i = 0; i < 8; i++)
256 *base = c;
257
258 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]259 *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]260
261 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
262 *base = c;
263
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]264 size = get_ram_size((long *)base, maxsize);
265 *orx_ptr = orx | ~(size - 1);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]266
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]267 return (size);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]268}
269
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]270phys_size_t initdram (int board_type)
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]271{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]272 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]273 volatile memctl8260_t *memctl = &immap->im_memctl;
274
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]275#ifndef CONFIG_SYS_RAMBOOT
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]276 long size8, size9;
277#endif
278 long psize, lsize;
279
280 psize = 16 * 1024 * 1024;
281 lsize = 0;
282
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]283 memctl->memc_psrt = CONFIG_SYS_PSRT;
284 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]285
286#if 0 /* Just for debugging */
287#define prt_br_or(brX,orX) do { \
288 ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
289 ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
290 printf ("\n" \
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]291 #brX " 0x%08x " #orX " 0x%08x " \
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]292 "==> 0x%08lx ... 0x%08lx = %ld MB\n", \
293 memctl->memc_ ## brX, memctl->memc_ ## orX, \
294 start, start+sizem, (sizem+1)>>20); \
295 } while (0)
296 prt_br_or (br0, or0);
297 prt_br_or (br1, or1);
298 prt_br_or (br2, or2);
299 prt_br_or (br3, or3);
300#endif
301
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]302#ifndef CONFIG_SYS_RAMBOOT
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]303 /* 60x SDRAM setup:
304 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]305 size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
306 (uchar *) CONFIG_SYS_SDRAM_BASE);
307 size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
308 (uchar *) CONFIG_SYS_SDRAM_BASE);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]309
310 if (size8 < size9) {
311 psize = size9;
312 printf ("(60x:9COL - %ld MB, ", psize >> 20);
313 } else {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]314 psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
315 (uchar *) CONFIG_SYS_SDRAM_BASE);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]316 printf ("(60x:8COL - %ld MB, ", psize >> 20);
317 }
318
319 /* Local SDRAM setup:
320 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]321#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
322 memctl->memc_lsrt = CONFIG_SYS_LSRT;
323 size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]324 (uchar *) SDRAM_BASE2_PRELIM);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]325 size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]326 (uchar *) SDRAM_BASE2_PRELIM);
327
328 if (size8 < size9) {
329 lsize = size9;
330 printf ("Local:9COL - %ld MB) using ", lsize >> 20);
331 } else {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]332 lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]333 (uchar *) SDRAM_BASE2_PRELIM);
334 printf ("Local:8COL - %ld MB) using ", lsize >> 20);
335 }
336
337#if 0
338 /* Set up BR2 so that the local SDRAM goes
339 * right after the 60x SDRAM
340 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]341 memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
342 (CONFIG_SYS_SDRAM_BASE + psize);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]343#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]344#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
345#endif /* CONFIG_SYS_RAMBOOT */
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]346
347 icache_enable ();
348
349 return (psize);
350}
351
352/* ------------------------------------------------------------------------- */