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git01.mediatek.com / filogic / uboot / 26dc25bad3952204705b4f9893759bab9dc9c6cc / . / board / spear / x600 / x600.c
blob: b8edfcd071fd4ba77443e17054694a2e5c1e602a [file] [log] [blame]
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]1/*
2 * (C) Copyright 2009
3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4 *
5 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]8 */
9
10#include <common.h>
11#include <nand.h>
12#include <netdev.h>
13#include <phy.h>
14#include <rtc.h>
15#include <asm/io.h>
16#include <asm/arch/hardware.h>
17#include <asm/arch/spr_defs.h>
18#include <asm/arch/spr_misc.h>
19#include <linux/mtd/fsmc_nand.h>
20#include "fpga.h"
21
22static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
23
24int board_init(void)
25{
26 /*
27 * X600 is equipped with an M41T82 RTC. This RTC has the
28 * HT bit (Halt Update), which needs to be cleared upon
29 * power-up. Otherwise the RTC is halted.
30 */
31 rtc_reset();
32
33 return spear_board_init(MACH_TYPE_SPEAR600);
34}
35
36int board_late_init(void)
37{
38 /*
39 * Monitor and env protection on by default
40 */
41 flash_protect(FLAG_PROTECT_SET,
42 CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
43 CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
44 2 * CONFIG_ENV_SECT_SIZE - 1,
45 &flash_info[0]);
46
47 /* Init FPGA subsystem */
48 x600_init_fpga();
49
50 return 0;
51}
52
53/*
54 * board_nand_init - Board specific NAND initialization
55 * @nand: mtd private chip structure
56 *
57 * Called by nand_init_chip to initialize the board specific functions
58 */
59
60void board_nand_init(void)
61{
62 struct misc_regs *const misc_regs_p =
63 (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
64 struct nand_chip *nand = &nand_chip[0];
65
66 if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
67 fsmc_nand_init(nand);
68}
69
Alexey Brodkin9a0b1302014-01-22 20:54:06 +0400[diff] [blame]70int board_phy_config(struct phy_device *phydev)
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]71{
72 /* Extended PHY control 1, select GMII */
Alexey Brodkin9a0b1302014-01-22 20:54:06 +0400[diff] [blame]73 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]74
75 /* Software reset necessary after GMII mode selction */
Alexey Brodkin9a0b1302014-01-22 20:54:06 +0400[diff] [blame]76 phy_reset(phydev);
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]77
78 /* Enable extended page register access */
Alexey Brodkin9a0b1302014-01-22 20:54:06 +0400[diff] [blame]79 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]80
81 /* 17e: Enhanced LED behavior, needs to be written twice */
Alexey Brodkin9a0b1302014-01-22 20:54:06 +0400[diff] [blame]82 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
83 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]84
85 /* 16e: Enhanced LED method select */
Alexey Brodkin9a0b1302014-01-22 20:54:06 +0400[diff] [blame]86 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]87
88 /* Disable extended page register access */
Alexey Brodkin9a0b1302014-01-22 20:54:06 +0400[diff] [blame]89 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]90
91 /* Enable clock output pin */
Alexey Brodkin9a0b1302014-01-22 20:54:06 +0400[diff] [blame]92 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
93
94 if (phydev->drv->config)
95 phydev->drv->config(phydev);
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]96
97 return 0;
98}
99
100int board_eth_init(bd_t *bis)
101{
102 int ret = 0;
103
Alexey Brodkin9a0b1302014-01-22 20:54:06 +0400[diff] [blame]104 if (designware_initialize(CONFIG_SPEAR_ETHBASE,
Stefan Roese181e06b2012-05-30 22:59:08 +0000[diff] [blame]105 PHY_INTERFACE_MODE_GMII) >= 0)
106 ret++;
107
108 return ret;
109}