| John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 DENX Software Engineering |
| 3 | * Author: John Rigby <jrigby@gmail.com> |
| 4 | * |
| 5 | * Based on U-Boot and RedBoot sources for several different i.mx |
| 6 | * platforms. |
| 7 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <asm/macro.h> |
| Benoît Thébaudeau | f58c48e | 2012-08-20 09:00:57 +0000 | [diff] [blame] | 12 | #include <asm/arch/macro.h> |
| John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 13 | |
| 14 | .macro init_clocks |
| 15 | /* |
| 16 | * clocks |
| 17 | * |
| 18 | * first enable CLKO debug output |
| 19 | * 0x40000000 enables the debug CLKO signal |
| 20 | * 0x05000000 sets CLKO divider to 6 |
| 21 | * 0x00600000 makes CLKO parent clk the USB clk |
| 22 | */ |
| 23 | write32 0x53f80064, 0x45600000 |
| Benoît Thébaudeau | f58c48e | 2012-08-20 09:00:57 +0000 | [diff] [blame] | 24 | |
| 25 | /* CCTL: ARM = 399 MHz, AHB = 133 MHz */ |
| John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 26 | write32 0x53f80008, 0x20034000 |
| 27 | |
| 28 | /* |
| Benoît Thébaudeau | 9cb0878 | 2012-08-08 03:55:32 +0000 | [diff] [blame] | 29 | * PCDR2: NFC = 33.25 MHz |
| 30 | * This is required for the NAND Flash of this board, which is a Samsung |
| 31 | * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with |
| 32 | * the NFC driver in symmetric (i.e. one-cycle) mode. |
| 33 | */ |
| 34 | write32 0x53f80020, 0x01010103 |
| 35 | |
| 36 | /* |
| John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 37 | * enable all implemented clocks in all three |
| 38 | * clock control registers |
| 39 | */ |
| 40 | write32 0x53f8000c, 0x1fffffff |
| 41 | write32 0x53f80010, 0xffffffff |
| 42 | write32 0x53f80014, 0xfdfff |
| 43 | .endm |
| 44 | |
| 45 | .macro init_ddrtype |
| 46 | /* |
| 47 | * ddr_type is 3.3v SDRAM |
| 48 | */ |
| 49 | write32 0x43fac454, 0x800 |
| 50 | .endm |
| 51 | |
| 52 | /* |
| 53 | * sdram controller init |
| 54 | */ |
| 55 | .macro init_sdram_bank bankaddr, ctl, cfg |
| 56 | ldr r0, =0xb8001000 |
| 57 | ldr r2, =\bankaddr |
| 58 | /* |
| 59 | * reset SDRAM controller |
| 60 | * then wait for initialization to complete |
| 61 | */ |
| 62 | ldr r1, =(1 << 1) |
| 63 | str r1, [r0, #0x10] |
| 64 | 1: ldr r3, [r0, #0x10] |
| 65 | tst r3, #(1 << 31) |
| 66 | beq 1b |
| 67 | |
| 68 | ldr r1, =0x95728 |
| 69 | str r1, [r0, #\cfg] /* config */ |
| 70 | |
| 71 | ldr r1, =0x92116480 /* control | precharge */ |
| 72 | str r1, [r0, #\ctl] /* write command to controller */ |
| 73 | str r1, [r2, #0x400] /* command encoded in address */ |
| 74 | |
| 75 | ldr r1, =0xa2116480 /* auto refresh */ |
| 76 | str r1, [r0, #\ctl] |
| 77 | ldrb r3, [r2] /* read dram twice to auto refresh */ |
| 78 | ldrb r3, [r2] |
| 79 | |
| 80 | ldr r1, =0xb2116480 /* control | load mode */ |
| 81 | str r1, [r0, #\ctl] /* write command to controller */ |
| 82 | strb r1, [r2, #0x33] /* command encoded in address */ |
| 83 | |
| 84 | ldr r1, =0x82116480 /* control | normal (0)*/ |
| 85 | str r1, [r0, #\ctl] /* write command to controller */ |
| 86 | .endm |
| 87 | |
| 88 | .globl lowlevel_init |
| 89 | lowlevel_init: |
| 90 | init_aips |
| 91 | init_max |
| 92 | init_m3if |
| 93 | init_clocks |
| 94 | |
| 95 | init_sdram_bank 0x80000000, 0x0, 0x4 |
| 96 | |
| 97 | init_sdram_bank 0x90000000, 0x8, 0xc |
| 98 | mov pc, lr |