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git01.mediatek.com / filogic / uboot / 26dc25bad3952204705b4f9893759bab9dc9c6cc / . / board / freescale / p2020come / tlb.c
blob: 08a1e3433ac037e4c16657e9f5099cc8c69a7d8d [file] [log] [blame]
Ira W. Snydera07c0512011-11-23 08:25:58 -0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Ira W. Snydera07c0512011-11-23 08:25:58 -0800[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/mmu.h>
9
10struct fsl_e_tlb_entry tlb_table[] = {
11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
13 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
14 MAS3_SW|MAS3_SR, 0,
15 0, 0, BOOKE_PAGESZ_4K, 0),
16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
17 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
18 MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
21 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
22 MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
25 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
26 MAS3_SW|MAS3_SR, 0,
27 0, 0, BOOKE_PAGESZ_4K, 0),
28
29 /* TLB 1 */
30 /* *I*** - Covers boot page */
31 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
32 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
33 0, 0, BOOKE_PAGESZ_4K, 1),
34
35 /* *I*G* - CCSRBAR */
36 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
37 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
38 0, 1, BOOKE_PAGESZ_1M, 1),
39
40#if defined(CONFIG_PCI)
41 /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
42 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
43 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
44 0, 2, BOOKE_PAGESZ_1G, 1),
45
46 /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
47 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
48 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
49 0, 3, BOOKE_PAGESZ_256M, 1),
50
51 /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */
52 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
53 CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
54 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
55 0, 4, BOOKE_PAGESZ_256M, 1),
56
57 /*
58 * *I*G* - PCI I/O
59 *
60 * PCI3 => 0xFFC10000
61 * PCI2 => 0xFFC2,0000
62 * PCI1 => 0xFFC3,0000
63 */
64 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
65 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
66 0, 5, BOOKE_PAGESZ_256K, 1),
67#endif /* #if defined(CONFIG_PCI) */
68
69#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
70 /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */
71 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 0, 6, BOOKE_PAGESZ_256K, 1),
74
75 /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
76 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
77 CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
78 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
79 0, 7, BOOKE_PAGESZ_256K, 1),
80#endif
81};
82
83int num_tlb_entries = ARRAY_SIZE(tlb_table);