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git01.mediatek.com / filogic / uboot / 26c50fbdecae5f9afc7d3132618d6d3efbbbc438 / . / arch / arm / include / asm / fsl_secure_boot.h
blob: d576f2ef45a7f6cc252ffe4bb67939bf0dbe22af [file] [log] [blame]
gaurav ranaf79323c2015-03-10 14:08:50 +0530[diff] [blame]1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __FSL_SECURE_BOOT_H
8#define __FSL_SECURE_BOOT_H
9
10#ifdef CONFIG_SECURE_BOOT
Aneesh Bansal43104702016-01-22 16:37:24 +0530[diff] [blame]11
12#ifndef CONFIG_FIT_SIGNATURE
13#define CONFIG_CHAIN_OF_TRUST
14#endif
15
16#endif
17
18#ifdef CONFIG_CHAIN_OF_TRUST
Aneesh Bansald31bb3e2015-07-31 14:10:03 +0530[diff] [blame]19#define CONFIG_CMD_ESBC_VALIDATE
Aneesh Bansal3322e212016-01-22 16:37:23 +0530[diff] [blame]20#define CONFIG_CMD_BLOB
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]21#define CONFIG_CMD_HASH
Aneesh Bansald31bb3e2015-07-31 14:10:03 +0530[diff] [blame]22#define CONFIG_FSL_SEC_MON
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]23#define CONFIG_SHA_HW_ACCEL
Aneesh Bansald31bb3e2015-07-31 14:10:03 +0530[diff] [blame]24#define CONFIG_SHA_PROG_HW_ACCEL
Aneesh Bansald31bb3e2015-07-31 14:10:03 +0530[diff] [blame]25#define CONFIG_RSA_FREESCALE_EXP
Aneesh Bansalb3e98202015-12-08 13:54:29 +0530[diff] [blame]26
Aneesh Bansald31bb3e2015-07-31 14:10:03 +0530[diff] [blame]27#ifndef CONFIG_FSL_CAAM
28#define CONFIG_FSL_CAAM
29#endif
30
31#define CONFIG_KEY_REVOCATION
32#ifndef CONFIG_SYS_RAMBOOT
33/* The key used for verification of next level images
34 * is picked up from an Extension Table which has
35 * been verified by the ISBC (Internal Secure boot Code)
36 * in boot ROM of the SoC.
37 * The feature is only applicable in case of NOR boot and is
38 * not applicable in case of RAMBOOT (NAND, SD, SPI).
39 */
Saksham Jain6121f082016-03-23 16:24:34 +0530[diff] [blame]40#ifndef CONFIG_ESBC_HDR_LS
41/* Current Key EXT feature not available in LS ESBC Header */
Aneesh Bansald31bb3e2015-07-31 14:10:03 +0530[diff] [blame]42#define CONFIG_FSL_ISBC_KEY_EXT
43#endif
44
Saksham Jain6121f082016-03-23 16:24:34 +0530[diff] [blame]45#endif
46
Saksham Jainc0c38d22016-03-23 16:24:35 +0530[diff] [blame]47#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
48 defined(CONFIG_LS2085A)
49/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
50 * Similiarly for LS2080 and LS2085
51 */
Aneesh Bansal962021a2016-01-22 16:37:22 +0530[diff] [blame]52#define CONFIG_ESBC_ADDR_64BIT
53#endif
54
Saksham Jainf0eb2ca2016-03-23 16:24:38 +0530[diff] [blame]55#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
56#define CONFIG_EXTRA_ENV \
57 "setenv fdt_high 0xa0000000;" \
58 "setenv initrd_high 0xcfffffff;" \
59 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
60#else
gaurav ranaf79323c2015-03-10 14:08:50 +0530[diff] [blame]61#define CONFIG_EXTRA_ENV \
62 "setenv fdt_high 0xcfffffff;" \
63 "setenv initrd_high 0xcfffffff;" \
64 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
Saksham Jainf0eb2ca2016-03-23 16:24:38 +0530[diff] [blame]65#endif
gaurav ranaf79323c2015-03-10 14:08:50 +0530[diff] [blame]66
Saksham Jain503eab92016-03-23 16:24:37 +0530[diff] [blame]67/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
68 * Non-XIP Memory (Nand/SD)*/
69#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\
70 defined(CONFIG_LS2085A)
71#define CONFIG_BOOTSCRIPT_COPY_RAM
72#endif
73/* The address needs to be modified according to NOR and DDR memory map */
Saksham Jain506c2eb2016-03-23 16:24:36 +0530[diff] [blame]74#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
Saksham Jain503eab92016-03-23 16:24:37 +0530[diff] [blame]75#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000
76#define CONFIG_BS_ADDR_FLASH 0x583900000
77#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
78#define CONFIG_BS_ADDR_RAM 0xa3900000
79#else
80#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
81#define CONFIG_BS_ADDR_FLASH 0x60060000
82#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
83#define CONFIG_BS_ADDR_RAM 0xa0060000
84#endif
85
86#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
87#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
88#define CONFIG_BS_HDR_SIZE 0x00002000
89#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
90#define CONFIG_BS_SIZE 0x00001000
Saksham Jain506c2eb2016-03-23 16:24:36 +0530[diff] [blame]91#else
Saksham Jain503eab92016-03-23 16:24:37 +0530[diff] [blame]92#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH
93/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */
Saksham Jain506c2eb2016-03-23 16:24:36 +0530[diff] [blame]94#endif
gaurav ranaf79323c2015-03-10 14:08:50 +0530[diff] [blame]95
Aneesh Bansal43104702016-01-22 16:37:24 +0530[diff] [blame]96#include <config_fsl_chain_trust.h>
97#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
gaurav ranaf79323c2015-03-10 14:08:50 +0530[diff] [blame]98#endif