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git01.mediatek.com / filogic / uboot / 26b5cbac9fe4053b359a9213a29dd5b9dc88cb04 / . / arch / arm / dts / fsl-imx8qm-apalis-u-boot.dtsi
blob: d73be74d2112ff479b9b26ec70a3077a3de62b8b [file] [log] [blame]
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2019 Toradex AG
4 */
5
Emanuele Ghidoli26b5cba2024-02-23 10:11:41 +0100[diff] [blame^]6/ {
7 sysinfo {
8 compatible = "toradex,sysinfo";
9 };
10};
11
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]12&mu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]14};
15
16&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]18};
19
20&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]22};
23
24&pd_lsio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]26};
27
28&pd_lsio_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]30};
31
32&pd_lsio_gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]34};
35
36&pd_lsio_gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]38};
39
40&pd_lsio_gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]42};
43
44&pd_lsio_gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]46};
47
48&pd_lsio_gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]50};
51
52&pd_lsio_gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]54};
55
56&pd_lsio_gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]58};
59
Igor Opaniukff829842020-03-27 12:28:15 +0200[diff] [blame]60&pd_dma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-some-ram;
Igor Opaniukff829842020-03-27 12:28:15 +0200[diff] [blame]62};
63
64&pd_dma_lpuart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-some-ram;
Igor Opaniukff829842020-03-27 12:28:15 +0200[diff] [blame]66};
67
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]68&pd_conn {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]70};
71
72&pd_conn_sdch0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]74};
75
76&pd_conn_sdch1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]78};
79
80&pd_conn_sdch2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]82};
83
84&gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]86};
87
88&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]90};
91
92&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]94};
95
96&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]98};
99
100&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-some-ram;
Andrejs Cainikovsb4c7eb62023-12-12 09:27:25 -0300[diff] [blame]102
103 usbh_en {
104 gpio-hog;
105 gpios = <4 GPIO_ACTIVE_HIGH>;
106 output-high;
107 };
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]108};
109
110&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]112};
113
114&gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]116};
117
118&gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]119 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]120};
121
122&lpuart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]124};
125
126&lpuart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]128};
129
130&lpuart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]131 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]132};
133
134&lpuart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]135 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]136};
137
138&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]139 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]140};
141
142&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]143 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]144};
145
146&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]147 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]148};