blob: abf543232957140af3defaf66b4c5d23ddc65c28 [file] [log] [blame]
Heiko Schocher499c4982013-08-19 16:39:01 +02001/*
2 * board.h
3 *
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
7 * Based on:
8 * TI AM335x boards information header
9 * u-boot:/board/ti/am335x/board.h
10 *
11 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
12 *
13 * SPDX-License-Identifier: GPL-2.0+
14 */
15
16#ifndef _BOARD_H_
17#define _BOARD_H_
18
19#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \
20 settings.ddr3.x, ddr3_default.x
21#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y))
22#define MAGIC_CHIP 0x50494843
23
24/* Automatic generated definition */
Samuel Egli8069bfe2013-11-04 14:05:03 +010025/* Wed, 18 Sep 2013 18:58:27 +0200 */
26/* From file: draco/ddr3-data-micron-v2.txt */
Heiko Schocher499c4982013-08-19 16:39:01 +020027struct ddr3_data {
28 unsigned int magic; /* 0x33524444 */
Samuel Egli8069bfe2013-11-04 14:05:03 +010029 unsigned int version; /* 0x56312e34 */
Heiko Schocher499c4982013-08-19 16:39:01 +020030 unsigned short int ddr3_sratio; /* 0x0100 */
31 unsigned short int iclkout; /* 0x0001 */
32 unsigned short int dt0rdsratio0; /* 0x003A */
33 unsigned short int dt0wdsratio0; /* 0x008A */
34 unsigned short int dt0fwsratio0; /* 0x010B */
35 unsigned short int dt0wrsratio0; /* 0x00C4 */
36 unsigned int sdram_tim1; /* 0x0888A39B */
37 unsigned int sdram_tim2; /* 0x26247FDA */
38 unsigned int sdram_tim3; /* 0x501F821F */
Samuel Egli8069bfe2013-11-04 14:05:03 +010039 unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */
Heiko Schocher499c4982013-08-19 16:39:01 +020040 unsigned int sdram_config; /* 0x61C04AB2 */
41 unsigned int ref_ctrl; /* 0x00000618 */
Samuel Egli8069bfe2013-11-04 14:05:03 +010042 unsigned int ioctr_val; /* 0x0000018B */
Heiko Schocher499c4982013-08-19 16:39:01 +020043};
44
45struct chip_data {
46 unsigned int magic;
47 char sdevname[16];
48 char shwver[7];
49};
50
51struct dxr2_baseboard_id {
52 struct ddr3_data ddr3;
53 struct chip_data chip;
54};
55
56/*
57 * We have three pin mux functions that must exist. We must be able to enable
58 * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
59 * main pinmux function that can be overridden to enable all other pinmux that
60 * is required on the board.
61 */
62void enable_uart0_pin_mux(void);
63void enable_uart1_pin_mux(void);
64void enable_uart2_pin_mux(void);
65void enable_uart3_pin_mux(void);
66void enable_uart4_pin_mux(void);
67void enable_uart5_pin_mux(void);
68void enable_i2c0_pin_mux(void);
69void enable_board_pin_mux(void);
70#endif