| Simon Glass | 0b36ecd | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 1 | # |
| 2 | # From Coreboot src/northbridge/intel/sandybridge/Kconfig |
| 3 | # |
| 4 | # Copyright (C) 2010 Google Inc. |
| 5 | # |
| 6 | # SPDX-License-Identifier: GPL-2.0 |
| 7 | |
| 8 | |
| 9 | config NORTHBRIDGE_INTEL_SANDYBRIDGE |
| 10 | bool |
| 11 | select CACHE_MRC_BIN |
| 12 | select CPU_INTEL_MODEL_206AX |
| 13 | |
| 14 | config NORTHBRIDGE_INTEL_IVYBRIDGE |
| 15 | bool |
| 16 | select CACHE_MRC_BIN |
| 17 | select CPU_INTEL_MODEL_306AX |
| 18 | |
| 19 | if NORTHBRIDGE_INTEL_SANDYBRIDGE |
| 20 | |
| 21 | config VGA_BIOS_ID |
| 22 | string |
| 23 | default "8086,0106" |
| 24 | |
| 25 | config CACHE_MRC_SIZE_KB |
| 26 | int |
| 27 | default 256 |
| 28 | |
| 29 | config MRC_CACHE_BASE |
| 30 | hex |
| 31 | default 0xff800000 |
| 32 | |
| 33 | config MRC_CACHE_LOCATION |
| 34 | hex |
| 35 | depends on !CHROMEOS |
| 36 | default 0x1ec000 |
| 37 | |
| 38 | config MRC_CACHE_SIZE |
| 39 | hex |
| 40 | depends on !CHROMEOS |
| 41 | default 0x10000 |
| 42 | |
| 43 | config DCACHE_RAM_BASE |
| 44 | hex |
| 45 | default 0xff7f0000 |
| 46 | |
| 47 | config DCACHE_RAM_SIZE |
| 48 | hex |
| 49 | default 0x10000 |
| 50 | |
| 51 | endif |
| 52 | |
| 53 | if NORTHBRIDGE_INTEL_IVYBRIDGE |
| 54 | |
| 55 | config VGA_BIOS_ID |
| 56 | string |
| 57 | default "8086,0166" |
| 58 | |
| 59 | config EXTERNAL_MRC_BLOB |
| 60 | bool |
| 61 | default n |
| 62 | |
| 63 | config CACHE_MRC_SIZE_KB |
| 64 | int |
| 65 | default 512 |
| 66 | |
| 67 | config MRC_CACHE_BASE |
| 68 | hex |
| 69 | default 0xff800000 |
| 70 | |
| 71 | config MRC_CACHE_LOCATION |
| 72 | hex |
| 73 | depends on !CHROMEOS |
| 74 | default 0x370000 |
| 75 | |
| 76 | config MRC_CACHE_SIZE |
| 77 | hex |
| 78 | depends on !CHROMEOS |
| 79 | default 0x10000 |
| 80 | |
| 81 | config DCACHE_RAM_BASE |
| 82 | hex |
| 83 | default 0xff7e0000 |
| 84 | |
| 85 | config DCACHE_RAM_SIZE |
| 86 | hex |
| 87 | default 0x20000 |
| 88 | |
| 89 | endif |
| 90 | |
| 91 | if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE |
| 92 | |
| 93 | config HAVE_MRC |
| 94 | bool "Add a System Agent binary" |
| 95 | help |
| 96 | Select this option to add a System Agent binary to |
| 97 | the resulting U-Boot image. MRC stands for Memory Reference Code. |
| 98 | It is a binary blob which U-Boot uses to set up SDRAM. |
| 99 | |
| 100 | Note: Without this binary U-Boot will not be able to set up its |
| 101 | SDRAM so will not boot. |
| 102 | |
| 103 | config DCACHE_RAM_MRC_VAR_SIZE |
| 104 | hex |
| 105 | default 0x4000 |
| 106 | help |
| 107 | This is the amount of CAR (Cache as RAM) reserved for use by the |
| 108 | memory reference code. This should be set to 16KB (0x4000 hex) |
| 109 | so that MRC has enough space to run. |
| 110 | |
| 111 | config MRC_FILE |
| 112 | string "Intel System Agent path and filename" |
| 113 | depends on HAVE_MRC |
| 114 | default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE |
| 115 | default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE |
| 116 | help |
| 117 | The path and filename of the file to use as System Agent |
| 118 | binary. |
| 119 | |
| 120 | config CPU_SPECIFIC_OPTIONS |
| 121 | def_bool y |
| 122 | select SMM_TSEG |
| 123 | select ARCH_BOOTBLOCK_X86_32 |
| 124 | select ARCH_ROMSTAGE_X86_32 |
| 125 | select ARCH_RAMSTAGE_X86_32 |
| 126 | select SMP |
| 127 | select SSE2 |
| 128 | select UDELAY_LAPIC |
| 129 | select CPU_MICROCODE_IN_CBFS |
| 130 | select TSC_SYNC_MFENCE |
| 131 | select HAVE_INTEL_ME |
| Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame^] | 132 | select X86_RAMTEST |
| Simon Glass | 0b36ecd | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 133 | |
| 134 | config SMM_TSEG_SIZE |
| 135 | hex |
| 136 | default 0x800000 |
| 137 | |
| 138 | config ENABLE_VMX |
| 139 | bool "Enable VMX for virtualization" |
| 140 | default n |
| 141 | help |
| 142 | Virtual Machine Extensions are provided in many x86 CPUs. These |
| 143 | provide various facilities for allowing a host OS to provide an |
| 144 | environment where potentially several guest OSes have only |
| 145 | limited access to the underlying hardware. This is achieved |
| 146 | without resorting to software trapping and/or instruction set |
| 147 | emulation (which would be very slow). |
| 148 | |
| 149 | Intel's implementation of this is called VT-x. This option enables |
| 150 | VT-x this so that the OS that is booted by U-Boot can make use of |
| 151 | these facilities. If this option is not enabled, then the host OS |
| 152 | will be unable to support virtualisation, or it will run very |
| 153 | slowly. |
| 154 | |
| 155 | endif |
| 156 | |
| 157 | config CPU_INTEL_SOCKET_RPGA989 |
| 158 | bool |
| 159 | |
| 160 | if CPU_INTEL_SOCKET_RPGA989 |
| 161 | |
| 162 | config SOCKET_SPECIFIC_OPTIONS # dummy |
| 163 | def_bool y |
| 164 | select MMX |
| 165 | select SSE |
| 166 | select CACHE_AS_RAM |
| 167 | |
| 168 | config CACHE_MRC_BIN |
| 169 | bool |
| 170 | default n |
| 171 | |
| 172 | endif |