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git01.mediatek.com / filogic / uboot / 267bb9cb91dbfac12a03560f7df729cb2210dc9c / . / arch / arm / mach-k3 / arm64-mmu.c
blob: 14e7c896f9151d870d55450fd6cc6dbf82ab583c [file] [log] [blame]
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * K3: ARM64 MMU setup
4 *
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]5 * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]6 * Lokesh Vutla <lokeshvutla@ti.com>
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]7 * Suman Anna <s-anna@ti.com>
Michal Simek7f60b232019-01-17 08:22:43 +0100[diff] [blame]8 * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]9 *
10 */
11
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]12#include <asm/system.h>
13#include <asm/armv8/mmu.h>
14
Andrew Davis1be5e972022-07-15 10:25:27 -0500[diff] [blame]15#ifdef CONFIG_SOC_K3_AM654
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]16/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
Suman Annaf359afb2019-09-04 16:01:49 +0530[diff] [blame]17#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]18
19/* ToDo: Add 64bit IO */
20struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
21 {
22 .virt = 0x0UL,
23 .phys = 0x0UL,
24 .size = 0x80000000UL,
25 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
26 PTE_BLOCK_NON_SHARE |
27 PTE_BLOCK_PXN | PTE_BLOCK_UXN
28 }, {
29 .virt = 0x80000000UL,
30 .phys = 0x80000000UL,
Suman Annaf359afb2019-09-04 16:01:49 +0530[diff] [blame]31 .size = 0x20000000UL,
32 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
33 PTE_BLOCK_INNER_SHARE
34 }, {
35 .virt = 0xa0000000UL,
36 .phys = 0xa0000000UL,
37 .size = 0x02100000UL,
38 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
39 PTE_BLOCK_INNER_SHARE
40 }, {
41 .virt = 0xa2100000UL,
42 .phys = 0xa2100000UL,
43 .size = 0x5df00000UL,
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]44 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
45 PTE_BLOCK_INNER_SHARE
46 }, {
47 .virt = 0x880000000UL,
48 .phys = 0x880000000UL,
49 .size = 0x80000000UL,
50 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
51 PTE_BLOCK_INNER_SHARE
52 }, {
Vignesh Raghavendraf2716382020-02-04 11:09:49 +0530[diff] [blame]53 .virt = 0x500000000UL,
54 .phys = 0x500000000UL,
55 .size = 0x400000000UL,
56 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
57 PTE_BLOCK_NON_SHARE |
58 PTE_BLOCK_PXN | PTE_BLOCK_UXN
59 }, {
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]60 /* List terminator */
61 0,
62 }
63};
64
65struct mm_region *mem_map = am654_mem_map;
Andrew Davis1be5e972022-07-15 10:25:27 -0500[diff] [blame]66#endif /* CONFIG_SOC_K3_AM654 */
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]67
68#ifdef CONFIG_SOC_K3_J721E
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]69
70#ifdef CONFIG_TARGET_J721E_A72_EVM
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]71/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
Suman Anna063761b2020-03-10 16:05:55 -0500[diff] [blame]72#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]73
74/* ToDo: Add 64bit IO */
75struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
76 {
77 .virt = 0x0UL,
78 .phys = 0x0UL,
79 .size = 0x80000000UL,
80 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
81 PTE_BLOCK_NON_SHARE |
82 PTE_BLOCK_PXN | PTE_BLOCK_UXN
83 }, {
84 .virt = 0x80000000UL,
85 .phys = 0x80000000UL,
86 .size = 0x20000000UL,
87 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
88 PTE_BLOCK_INNER_SHARE
89 }, {
90 .virt = 0xa0000000UL,
91 .phys = 0xa0000000UL,
Kedar Chitnis0e01e3e2019-09-04 16:01:50 +0530[diff] [blame]92 .size = 0x1bc00000UL,
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]93 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
94 PTE_BLOCK_NON_SHARE
95 }, {
Kedar Chitnis0e01e3e2019-09-04 16:01:50 +0530[diff] [blame]96 .virt = 0xbbc00000UL,
97 .phys = 0xbbc00000UL,
98 .size = 0x44400000UL,
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]99 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
100 PTE_BLOCK_INNER_SHARE
101 }, {
102 .virt = 0x880000000UL,
103 .phys = 0x880000000UL,
104 .size = 0x80000000UL,
105 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
106 PTE_BLOCK_INNER_SHARE
107 }, {
108 .virt = 0x500000000UL,
109 .phys = 0x500000000UL,
110 .size = 0x400000000UL,
111 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
112 PTE_BLOCK_NON_SHARE |
113 PTE_BLOCK_PXN | PTE_BLOCK_UXN
114 }, {
Suman Anna063761b2020-03-10 16:05:55 -0500[diff] [blame]115 .virt = 0x4d80000000UL,
116 .phys = 0x4d80000000UL,
117 .size = 0x0002000000UL,
118 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
119 PTE_BLOCK_INNER_SHARE
120 }, {
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]121 /* List terminator */
122 0,
123 }
124};
125
126struct mm_region *mem_map = j721e_mem_map;
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]127#endif /* CONFIG_TARGET_J721E_A72_EVM */
128
129#ifdef CONFIG_TARGET_J7200_A72_EVM
130#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
131
132/* ToDo: Add 64bit IO */
133struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
134 {
135 .virt = 0x0UL,
136 .phys = 0x0UL,
137 .size = 0x80000000UL,
138 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
139 PTE_BLOCK_NON_SHARE |
140 PTE_BLOCK_PXN | PTE_BLOCK_UXN
141 }, {
142 .virt = 0x80000000UL,
143 .phys = 0x80000000UL,
144 .size = 0x20000000UL,
145 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
146 PTE_BLOCK_INNER_SHARE
147 }, {
148 .virt = 0xa0000000UL,
149 .phys = 0xa0000000UL,
150 .size = 0x04800000UL,
151 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
152 PTE_BLOCK_NON_SHARE
153 }, {
154 .virt = 0xa4800000UL,
155 .phys = 0xa4800000UL,
156 .size = 0x5b800000UL,
157 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
158 PTE_BLOCK_INNER_SHARE
159 }, {
160 .virt = 0x880000000UL,
161 .phys = 0x880000000UL,
162 .size = 0x80000000UL,
163 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
164 PTE_BLOCK_INNER_SHARE
165 }, {
166 .virt = 0x500000000UL,
167 .phys = 0x500000000UL,
168 .size = 0x400000000UL,
169 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
170 PTE_BLOCK_NON_SHARE |
171 PTE_BLOCK_PXN | PTE_BLOCK_UXN
172 }, {
173 /* List terminator */
174 0,
175 }
176};
177
178struct mm_region *mem_map = j7200_mem_map;
179#endif /* CONFIG_TARGET_J7200_A72_EVM */
180
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]181#endif /* CONFIG_SOC_K3_J721E */
Keerthye07dfe52021-04-23 11:27:39 -0500[diff] [blame]182
David Huang61098202022-01-25 20:56:31 +0530[diff] [blame]183#ifdef CONFIG_SOC_K3_J721S2
184#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
185
186/* ToDo: Add 64bit IO */
187struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = {
188 {
189 .virt = 0x0UL,
190 .phys = 0x0UL,
191 .size = 0x80000000UL,
192 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
193 PTE_BLOCK_NON_SHARE |
194 PTE_BLOCK_PXN | PTE_BLOCK_UXN
195 }, {
196 .virt = 0x80000000UL,
197 .phys = 0x80000000UL,
198 .size = 0x80000000UL,
199 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
200 PTE_BLOCK_INNER_SHARE
201 }, {
202 .virt = 0x880000000UL,
203 .phys = 0x880000000UL,
204 .size = 0x80000000UL,
205 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
206 PTE_BLOCK_INNER_SHARE
207 }, {
208 .virt = 0x500000000UL,
209 .phys = 0x500000000UL,
210 .size = 0x400000000UL,
211 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
212 PTE_BLOCK_NON_SHARE |
213 PTE_BLOCK_PXN | PTE_BLOCK_UXN
214 }, {
215 /* List terminator */
216 0,
217 }
218};
219
220struct mm_region *mem_map = j721s2_mem_map;
221
222#endif /* CONFIG_SOC_K3_J721S2 */
223
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]224#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7)
Bryan Brattlofdaa39a62022-11-03 19:13:55 -0500[diff] [blame]225
Keerthye07dfe52021-04-23 11:27:39 -0500[diff] [blame]226/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]227#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4)
Keerthye07dfe52021-04-23 11:27:39 -0500[diff] [blame]228
229/* ToDo: Add 64bit IO */
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]230struct mm_region am62_mem_map[NR_MMU_REGIONS] = {
Keerthye07dfe52021-04-23 11:27:39 -0500[diff] [blame]231 {
232 .virt = 0x0UL,
233 .phys = 0x0UL,
234 .size = 0x80000000UL,
235 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
236 PTE_BLOCK_NON_SHARE |
237 PTE_BLOCK_PXN | PTE_BLOCK_UXN
238 }, {
239 .virt = 0x80000000UL,
240 .phys = 0x80000000UL,
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]241 .size = 0x1E780000UL,
242 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
243 PTE_BLOCK_INNER_SHARE
244 }, {
245 .virt = 0xA0000000UL,
246 .phys = 0xA0000000UL,
247 .size = 0x60000000UL,
248 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
249 PTE_BLOCK_INNER_SHARE
250
251 }, {
252 .virt = 0x880000000UL,
253 .phys = 0x880000000UL,
254 .size = 0x80000000UL,
255 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
256 PTE_BLOCK_INNER_SHARE
257 }, {
258 .virt = 0x500000000UL,
259 .phys = 0x500000000UL,
260 .size = 0x400000000UL,
261 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
262 PTE_BLOCK_NON_SHARE |
263 PTE_BLOCK_PXN | PTE_BLOCK_UXN
264 }, {
265 /* List terminator */
266 0,
267 }
268};
269
270struct mm_region *mem_map = am62_mem_map;
271#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
272
273#ifdef CONFIG_SOC_K3_AM642
274
275/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
276#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4)
277
278/* ToDo: Add 64bit IO */
279struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
280 {
281 .virt = 0x0UL,
282 .phys = 0x0UL,
Keerthye07dfe52021-04-23 11:27:39 -0500[diff] [blame]283 .size = 0x80000000UL,
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]284 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
285 PTE_BLOCK_NON_SHARE |
286 PTE_BLOCK_PXN | PTE_BLOCK_UXN
287 }, {
288 .virt = 0x80000000UL,
289 .phys = 0x80000000UL,
290 .size = 0x1E800000UL,
291 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
292 PTE_BLOCK_INNER_SHARE
293 }, {
294 .virt = 0xA0000000UL,
295 .phys = 0xA0000000UL,
296 .size = 0x60000000UL,
Keerthye07dfe52021-04-23 11:27:39 -0500[diff] [blame]297 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
298 PTE_BLOCK_INNER_SHARE
299 }, {
300 .virt = 0x880000000UL,
301 .phys = 0x880000000UL,
302 .size = 0x80000000UL,
303 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
304 PTE_BLOCK_INNER_SHARE
305 }, {
306 .virt = 0x500000000UL,
307 .phys = 0x500000000UL,
308 .size = 0x400000000UL,
309 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
310 PTE_BLOCK_NON_SHARE |
311 PTE_BLOCK_PXN | PTE_BLOCK_UXN
312 }, {
313 /* List terminator */
314 0,
315 }
316};
317
318struct mm_region *mem_map = am64_mem_map;
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]319#endif /* CONFIG_SOC_K3_AM642 */