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Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * (C) Copyright 2003
7 * Ingo Assmus <ingo.assmus@keymile.com>
8 *
9 * based on - Driver for MV64360X ethernet ports
10 * Copyright (C) 2002 rabeeh@galileo.co.il
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 * MA 02110-1301 USA
29 */
30
31#include <common.h>
32#include <net.h>
33#include <malloc.h>
34#include <miiphy.h>
35#include <asm/errno.h>
36#include <asm/types.h>
37#include <asm/byteorder.h>
38#include <asm/arch/kirkwood.h>
39#include "kirkwood_egiga.h"
40
Simon Kagstromab9ca512009-08-20 10:12:28 +020041#define KIRKWOOD_PHY_ADR_REQUEST 0xee
Siddarth Gore26597a92010-01-19 11:09:07 +053042#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
Simon Kagstromab9ca512009-08-20 10:12:28 +020043
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053044/*
45 * smi_reg_read - miiphy_read callback function.
46 *
47 * Returns 16bit phy register value, or 0xffff on error
48 */
49static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
50{
51 struct eth_device *dev = eth_get_dev_by_name(devname);
52 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
53 struct kwgbe_registers *regs = dkwgbe->regs;
54 u32 smi_reg;
Simon Kagstrom4d0941c2009-07-08 13:03:18 +020055 u32 timeout;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053056
57 /* Phyadr read request */
Simon Kagstromab9ca512009-08-20 10:12:28 +020058 if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
59 reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053060 /* */
61 *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
62 return 0;
63 }
64 /* check parameters */
65 if (phy_adr > PHYADR_MASK) {
66 printf("Err..(%s) Invalid PHY address %d\n",
67 __FUNCTION__, phy_adr);
68 return -EFAULT;
69 }
70 if (reg_ofs > PHYREG_MASK) {
71 printf("Err..(%s) Invalid register offset %d\n",
72 __FUNCTION__, reg_ofs);
73 return -EFAULT;
74 }
75
76 timeout = KWGBE_PHY_SMI_TIMEOUT;
77 /* wait till the SMI is not busy */
78 do {
79 /* read smi register */
Siddarth Gore26597a92010-01-19 11:09:07 +053080 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053081 if (timeout-- == 0) {
82 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
83 return -EFAULT;
84 }
85 } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
86
87 /* fill the phy address and regiser offset and read opcode */
88 smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
89 | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
90 | KWGBE_PHY_SMI_OPCODE_READ;
91
92 /* write the smi register */
Siddarth Gore26597a92010-01-19 11:09:07 +053093 KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +053094
95 /*wait till read value is ready */
96 timeout = KWGBE_PHY_SMI_TIMEOUT;
97
98 do {
99 /* read smi register */
Siddarth Gore26597a92010-01-19 11:09:07 +0530100 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530101 if (timeout-- == 0) {
102 printf("Err..(%s) SMI read ready timeout\n",
103 __FUNCTION__);
104 return -EFAULT;
105 }
106 } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
107
108 /* Wait for the data to update in the SMI register */
109 for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
110
Siddarth Gore26597a92010-01-19 11:09:07 +0530111 *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530112
113 debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
114 reg_ofs, *data);
115
116 return 0;
117}
118
119/*
120 * smi_reg_write - imiiphy_write callback function.
121 *
122 * Returns 0 if write succeed, -EINVAL on bad parameters
123 * -ETIME on timeout
124 */
125static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
126{
127 struct eth_device *dev = eth_get_dev_by_name(devname);
128 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
129 struct kwgbe_registers *regs = dkwgbe->regs;
130 u32 smi_reg;
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200131 u32 timeout;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530132
133 /* Phyadr write request*/
Simon Kagstromab9ca512009-08-20 10:12:28 +0200134 if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
135 reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530136 KWGBEREG_WR(regs->phyadr, data);
137 return 0;
138 }
139
140 /* check parameters */
141 if (phy_adr > PHYADR_MASK) {
142 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
143 return -EINVAL;
144 }
145 if (reg_ofs > PHYREG_MASK) {
146 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
147 return -EINVAL;
148 }
149
150 /* wait till the SMI is not busy */
151 timeout = KWGBE_PHY_SMI_TIMEOUT;
152 do {
153 /* read smi register */
Siddarth Gore26597a92010-01-19 11:09:07 +0530154 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530155 if (timeout-- == 0) {
156 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
157 return -ETIME;
158 }
159 } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
160
161 /* fill the phy addr and reg offset and write opcode and data */
162 smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
163 smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
164 | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
165 smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
166
167 /* write the smi register */
Siddarth Gore26597a92010-01-19 11:09:07 +0530168 KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530169
170 return 0;
171}
172
173/* Stop and checks all queues */
174static void stop_queue(u32 * qreg)
175{
176 u32 reg_data;
177
178 reg_data = readl(qreg);
179
180 if (reg_data & 0xFF) {
181 /* Issue stop command for active channels only */
182 writel((reg_data << 8), qreg);
183
184 /* Wait for all queue activity to terminate. */
185 do {
186 /*
187 * Check port cause register that all queues
188 * are stopped
189 */
190 reg_data = readl(qreg);
191 }
192 while (reg_data & 0xFF);
193 }
194}
195
196/*
197 * set_access_control - Config address decode parameters for Ethernet unit
198 *
199 * This function configures the address decode parameters for the Gigabit
200 * Ethernet Controller according the given parameters struct.
201 *
202 * @regs Register struct pointer.
203 * @param Address decode parameter struct.
204 */
205static void set_access_control(struct kwgbe_registers *regs,
206 struct kwgbe_winparam *param)
207{
208 u32 access_prot_reg;
209
210 /* Set access control register */
211 access_prot_reg = KWGBEREG_RD(regs->epap);
212 /* clear window permission */
213 access_prot_reg &= (~(3 << (param->win * 2)));
214 access_prot_reg |= (param->access_ctrl << (param->win * 2));
215 KWGBEREG_WR(regs->epap, access_prot_reg);
216
217 /* Set window Size reg (SR) */
218 KWGBEREG_WR(regs->barsz[param->win].size,
219 (((param->size / 0x10000) - 1) << 16));
220
221 /* Set window Base address reg (BA) */
222 KWGBEREG_WR(regs->barsz[param->win].bar,
223 (param->target | param->attrib | param->base_addr));
224 /* High address remap reg (HARR) */
225 if (param->win < 4)
226 KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
227
228 /* Base address enable reg (BARER) */
229 if (param->enable == 1)
230 KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
231 else
232 KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
233}
234
235static void set_dram_access(struct kwgbe_registers *regs)
236{
237 struct kwgbe_winparam win_param;
238 int i;
239
240 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
241 /* Set access parameters for DRAM bank i */
242 win_param.win = i; /* Use Ethernet window i */
243 /* Window target - DDR */
244 win_param.target = KWGBE_TARGET_DRAM;
245 /* Enable full access */
246 win_param.access_ctrl = EWIN_ACCESS_FULL;
247 win_param.high_addr = 0;
248 /* Get bank base */
249 win_param.base_addr = kw_sdram_bar(i);
250 win_param.size = kw_sdram_bs(i); /* Get bank size */
251 if (win_param.size == 0)
252 win_param.enable = 0;
253 else
254 win_param.enable = 1; /* Enable the access */
255
256 /* Enable DRAM bank */
257 switch (i) {
258 case 0:
259 win_param.attrib = EBAR_DRAM_CS0;
260 break;
261 case 1:
262 win_param.attrib = EBAR_DRAM_CS1;
263 break;
264 case 2:
265 win_param.attrib = EBAR_DRAM_CS2;
266 break;
267 case 3:
268 win_param.attrib = EBAR_DRAM_CS3;
269 break;
270 default:
271 /* invalide bank, disable access */
272 win_param.enable = 0;
273 win_param.attrib = 0;
274 break;
275 }
276 /* Set the access control for address window(EPAPR) RD/WR */
277 set_access_control(regs, &win_param);
278 }
279}
280
281/*
282 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
283 *
284 * Go through all the DA filter tables (Unicast, Special Multicast & Other
285 * Multicast) and set each entry to 0.
286 */
287static void port_init_mac_tables(struct kwgbe_registers *regs)
288{
289 int table_index;
290
291 /* Clear DA filter unicast table (Ex_dFUT) */
292 for (table_index = 0; table_index < 4; ++table_index)
293 KWGBEREG_WR(regs->dfut[table_index], 0);
294
295 for (table_index = 0; table_index < 64; ++table_index) {
296 /* Clear DA filter special multicast table (Ex_dFSMT) */
297 KWGBEREG_WR(regs->dfsmt[table_index], 0);
298 /* Clear DA filter other multicast table (Ex_dFOMT) */
299 KWGBEREG_WR(regs->dfomt[table_index], 0);
300 }
301}
302
303/*
304 * port_uc_addr - This function Set the port unicast address table
305 *
306 * This function locates the proper entry in the Unicast table for the
307 * specified MAC nibble and sets its properties according to function
308 * parameters.
309 * This function add/removes MAC addresses from the port unicast address
310 * table.
311 *
312 * @uc_nibble Unicast MAC Address last nibble.
313 * @option 0 = Add, 1 = remove address.
314 *
315 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
316 */
317static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
318 int option)
319{
320 u32 unicast_reg;
321 u32 tbl_offset;
322 u32 reg_offset;
323
324 /* Locate the Unicast table entry */
325 uc_nibble = (0xf & uc_nibble);
326 /* Register offset from unicast table base */
327 tbl_offset = (uc_nibble / 4);
328 /* Entry offset within the above register */
329 reg_offset = uc_nibble % 4;
330
331 switch (option) {
332 case REJECT_MAC_ADDR:
333 /*
334 * Clear accepts frame bit at specified unicast
335 * DA table entry
336 */
337 unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
338 unicast_reg &= (0xFF << (8 * reg_offset));
339 KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
340 break;
341 case ACCEPT_MAC_ADDR:
342 /* Set accepts frame bit at unicast DA filter table entry */
343 unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
344 unicast_reg &= (0xFF << (8 * reg_offset));
345 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
346 KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
347 break;
348 default:
349 return 0;
350 }
351 return 1;
352}
353
354/*
355 * port_uc_addr_set - This function Set the port Unicast address.
356 */
357static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
358{
359 u32 mac_h;
360 u32 mac_l;
361
362 mac_l = (p_addr[4] << 8) | (p_addr[5]);
363 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
364 (p_addr[3] << 0);
365
366 KWGBEREG_WR(regs->macal, mac_l);
367 KWGBEREG_WR(regs->macah, mac_h);
368
369 /* Accept frames of this address */
370 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
371}
372
373/*
374 * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
375 */
376static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
377{
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200378 struct kwgbe_rxdesc *p_rx_desc;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530379 int i;
380
381 /* initialize the Rx descriptors ring */
382 p_rx_desc = dkwgbe->p_rxdesc;
383 for (i = 0; i < RINGSZ; i++) {
384 p_rx_desc->cmd_sts =
385 KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
386 p_rx_desc->buf_size = PKTSIZE_ALIGN;
387 p_rx_desc->byte_cnt = 0;
388 p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
389 if (i == (RINGSZ - 1))
390 p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
391 else {
392 p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
393 ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
394 p_rx_desc = p_rx_desc->nxtdesc_p;
395 }
396 }
397 dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
398}
399
400static int kwgbe_init(struct eth_device *dev)
401{
402 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
403 struct kwgbe_registers *regs = dkwgbe->regs;
Prafulla Wadaskar9841dec2009-09-09 15:59:19 +0530404#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
405 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
Simon Kagstrom15cc5a62009-08-20 10:13:06 +0200406 int i;
Prafulla Wadaskar9841dec2009-09-09 15:59:19 +0530407#endif
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530408 /* setup RX rings */
409 kwgbe_init_rx_desc_ring(dkwgbe);
410
411 /* Clear the ethernet port interrupts */
412 KWGBEREG_WR(regs->ic, 0);
413 KWGBEREG_WR(regs->ice, 0);
414 /* Unmask RX buffer and TX end interrupt */
415 KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
416 /* Unmask phy and link status changes interrupts */
417 KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
418
419 set_dram_access(regs);
420 port_init_mac_tables(regs);
421 port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
422
423 /* Assign port configuration and command. */
424 KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
425 KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
426 KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
427 /* Disable port initially */
428 KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
429
430 /* Assign port SDMA configuration */
431 KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
432 KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
433 KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
434 /* Turn off the port/RXUQ bandwidth limitation */
435 KWGBEREG_WR(regs->pmtu, 0);
436
437 /* Set maximum receive buffer to 9700 bytes */
438 KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
439 | (KWGBEREG_RD(regs->psc0) & MRU_MASK));
440
441 /*
442 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
443 * disable the leaky bucket mechanism .
444 */
445 KWGBEREG_WR(regs->pmtu, 0);
446
447 /* Assignment of Rx CRDB of given RXUQ */
448 KWGBEREG_WR(regs->rxcdp[RXUQ].rxcdp, (u32) dkwgbe->p_rxdesc_curr);
449 /* Enable port Rx. */
450 KWGBEREG_WR(regs->rqc, (1 << RXUQ));
451
452#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
453 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
Simon Kagstrom15cc5a62009-08-20 10:13:06 +0200454 /* Wait up to 5s for the link status */
455 for (i = 0; i < 5; i++) {
456 u16 phyadr;
457
458 miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
459 KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
460 /* Return if we get link up */
461 if (miiphy_link(dev->name, phyadr))
462 return 0;
463 udelay(1000000);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530464 }
Simon Kagstrom15cc5a62009-08-20 10:13:06 +0200465
466 printf("No link on %s\n", dev->name);
467 return -1;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530468#endif
469 return 0;
470}
471
472static int kwgbe_halt(struct eth_device *dev)
473{
474 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
475 struct kwgbe_registers *regs = dkwgbe->regs;
476
477 /* Disable all gigE address decoder */
478 KWGBEREG_WR(regs->bare, 0x3f);
479
480 stop_queue(&regs->tqc);
481 stop_queue(&regs->rqc);
482
483 /* Enable port */
484 KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
485 /* Set port is not reset */
486 KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
487#ifdef CONFIG_SYS_MII_MODE
488 /* Set MMI interface up */
489 KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
490#endif
491 /* Disable & mask ethernet port interrupts */
492 KWGBEREG_WR(regs->ic, 0);
493 KWGBEREG_WR(regs->ice, 0);
494 KWGBEREG_WR(regs->pim, 0);
495 KWGBEREG_WR(regs->peim, 0);
496
497 return 0;
498}
499
500static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
501 int datasize)
502{
503 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
504 struct kwgbe_registers *regs = dkwgbe->regs;
505 struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
Simon Kagstrome9220b32009-08-20 10:14:11 +0200506 void *p = (void *)dataptr;
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200507 u32 cmd_sts;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530508
Simon Kagstrome9220b32009-08-20 10:14:11 +0200509 /* Copy buffer if it's misaligned */
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530510 if ((u32) dataptr & 0x07) {
Simon Kagstrome9220b32009-08-20 10:14:11 +0200511 if (datasize > PKTSIZE_ALIGN) {
512 printf("Non-aligned data too large (%d)\n",
513 datasize);
514 return -1;
515 }
516
517 memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
518 p = dkwgbe->p_aligned_txbuf;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530519 }
Simon Kagstrome9220b32009-08-20 10:14:11 +0200520
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530521 p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
522 p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
523 p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
524 p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
Simon Kagstrome9220b32009-08-20 10:14:11 +0200525 p_txdesc->buf_ptr = (u8 *) p;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530526 p_txdesc->byte_cnt = datasize;
527
528 /* Apply send command using zeroth RXUQ */
529 KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
530 KWGBEREG_WR(regs->tqc, (1 << TXUQ));
531
532 /*
533 * wait for packet xmit completion
534 */
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200535 cmd_sts = readl(&p_txdesc->cmd_sts);
536 while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530537 /* return fail if error is detected */
Simon Kagstrom5b12b6f2009-07-08 13:05:11 +0200538 if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
539 (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
540 cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530541 printf("Err..(%s) in xmit packet\n", __FUNCTION__);
542 return -1;
543 }
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200544 cmd_sts = readl(&p_txdesc->cmd_sts);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530545 };
546 return 0;
547}
548
549static int kwgbe_recv(struct eth_device *dev)
550{
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200551 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
552 struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
553 u32 cmd_sts;
554 u32 timeout = 0;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530555
556 /* wait untill rx packet available or timeout */
557 do {
558 if (timeout < KWGBE_PHY_SMI_TIMEOUT)
559 timeout++;
560 else {
561 debug("%s time out...\n", __FUNCTION__);
562 return -1;
563 }
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200564 } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530565
566 if (p_rxdesc_curr->byte_cnt != 0) {
567 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
568 __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
569 (u32) p_rxdesc_curr->buf_ptr,
570 (u32) p_rxdesc_curr->cmd_sts);
571 }
572
573 /*
574 * In case received a packet without first/last bits on
575 * OR the error summary bit is on,
576 * the packets needs to be dropeed.
577 */
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200578 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
579
580 if ((cmd_sts &
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530581 (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
582 != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
583
584 printf("Err..(%s) Dropping packet spread on"
585 " multiple descriptors\n", __FUNCTION__);
586
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200587 } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530588
589 printf("Err..(%s) Dropping packet with errors\n",
590 __FUNCTION__);
591
592 } else {
593 /* !!! call higher layer processing */
594 debug("%s: Sending Received packet to"
595 " upper layer (NetReceive)\n", __FUNCTION__);
596
597 /* let the upper layer handle the packet */
598 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
599 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
600 }
601 /*
602 * free these descriptors and point next in the ring
603 */
604 p_rxdesc_curr->cmd_sts =
605 KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
606 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
607 p_rxdesc_curr->byte_cnt = 0;
608
Simon Kagstrom4d0941c2009-07-08 13:03:18 +0200609 writel((unsigned)p_rxdesc_curr->nxtdesc_p, &dkwgbe->p_rxdesc_curr);
610
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530611 return 0;
612}
613
614int kirkwood_egiga_initialize(bd_t * bis)
615{
616 struct kwgbe_device *dkwgbe;
617 struct eth_device *dev;
618 int devnum;
Prafulla Wadaskarc0343162009-08-10 19:43:06 +0530619 char *s;
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530620 u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
621
622 for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
623 /*skip if port is configured not to use */
624 if (used_ports[devnum] == 0)
625 continue;
626
627 if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
628 goto error1;
629
630 memset(dkwgbe, 0, sizeof(struct kwgbe_device));
631
632 if (!(dkwgbe->p_rxdesc =
633 (struct kwgbe_rxdesc *)memalign(PKTALIGN,
634 KW_RXQ_DESC_ALIGNED_SIZE
635 * RINGSZ + 1)))
636 goto error2;
637
638 if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
639 * PKTSIZE_ALIGN + 1)))
640 goto error3;
641
Simon Kagstrome9220b32009-08-20 10:14:11 +0200642 if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
643 goto error4;
644
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530645 if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
646 memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
Simon Kagstrome9220b32009-08-20 10:14:11 +0200647 free(dkwgbe->p_aligned_txbuf);
648 error4:
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530649 free(dkwgbe->p_rxbuf);
650 error3:
651 free(dkwgbe->p_rxdesc);
652 error2:
653 free(dkwgbe);
654 error1:
655 printf("Err.. %s Failed to allocate memory\n",
656 __FUNCTION__);
657 return -1;
658 }
659
660 dev = &dkwgbe->dev;
661
662 /* must be less than NAMESIZE (16) */
663 sprintf(dev->name, "egiga%d", devnum);
664
665 /* Extract the MAC address from the environment */
666 switch (devnum) {
667 case 0:
668 dkwgbe->regs = (void *)KW_EGIGA0_BASE;
669 s = "ethaddr";
670 break;
671 case 1:
672 dkwgbe->regs = (void *)KW_EGIGA1_BASE;
673 s = "eth1addr";
674 break;
675 default: /* this should never happen */
676 printf("Err..(%s) Invalid device number %d\n",
677 __FUNCTION__, devnum);
678 return -1;
679 }
680
681 while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
Prafulla Wadaskarc0343162009-08-10 19:43:06 +0530682 /* Generate Random Private MAC addr if not set */
683 dev->enetaddr[0] = 0x02;
684 dev->enetaddr[1] = 0x50;
685 dev->enetaddr[2] = 0x43;
686 dev->enetaddr[3] = get_random_hex();
687 dev->enetaddr[4] = get_random_hex();
688 dev->enetaddr[5] = get_random_hex();
689 eth_setenv_enetaddr(s, dev->enetaddr);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530690 }
691
692 dev->init = (void *)kwgbe_init;
693 dev->halt = (void *)kwgbe_halt;
694 dev->send = (void *)kwgbe_send;
695 dev->recv = (void *)kwgbe_recv;
696
697 eth_register(dev);
698
699#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
700 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
701 /* Set phy address of the port */
Simon Kagstromab9ca512009-08-20 10:12:28 +0200702 miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
703 KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
Prafulla Wadaskarb7a280d2009-06-14 22:33:46 +0530704#endif
705 }
706 return 0;
Prafulla Wadaskar12618ef2009-07-01 20:34:51 +0200707}