Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2009 |
| 4 | * Marvell Semiconductor <www.marvell.com> |
| 5 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Simon Glass | adaaa48 | 2019-11-14 12:57:43 -0700 | [diff] [blame] | 9 | #include <command.h> |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 10 | #include <cpu_func.h> |
Simon Glass | 0af6e2d | 2019-08-01 09:46:52 -0600 | [diff] [blame] | 11 | #include <env.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 12 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 13 | #include <log.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 14 | #include <net.h> |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 15 | #include <netdev.h> |
| 16 | #include <asm/cache.h> |
Lei Wen | 298ae91 | 2011-10-18 20:11:42 +0530 | [diff] [blame] | 17 | #include <asm/io.h> |
| 18 | #include <asm/arch/cpu.h> |
Stefan Roese | c243784 | 2014-10-22 12:13:06 +0200 | [diff] [blame] | 19 | #include <asm/arch/soc.h> |
DrEagle | ad88174 | 2014-07-25 21:07:30 +0200 | [diff] [blame] | 20 | #include <mvebu_mmc.h> |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 21 | |
Harald Seiler | 6f14d5f | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 22 | void reset_cpu(void) |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 23 | { |
| 24 | struct kwcpu_registers *cpureg = |
| 25 | (struct kwcpu_registers *)KW_CPU_REG_BASE; |
| 26 | |
| 27 | writel(readl(&cpureg->rstoutn_mask) | (1 << 2), |
| 28 | &cpureg->rstoutn_mask); |
| 29 | writel(readl(&cpureg->sys_soft_rst) | 1, |
| 30 | &cpureg->sys_soft_rst); |
| 31 | while (1) ; |
| 32 | } |
| 33 | |
| 34 | /* |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 35 | * Window Size |
| 36 | * Used with the Base register to set the address window size and location. |
| 37 | * Must be programmed from LSB to MSB as sequence of ones followed by |
| 38 | * sequence of zeros. The number of ones specifies the size of the window in |
| 39 | * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). |
| 40 | * NOTE: A value of 0x0 specifies 64-KByte size. |
| 41 | */ |
Prafulla Wadaskar | ecb1b02 | 2009-06-29 20:55:54 +0530 | [diff] [blame] | 42 | unsigned int kw_winctrl_calcsize(unsigned int sizeval) |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 43 | { |
| 44 | int i; |
| 45 | unsigned int j = 0; |
| 46 | u32 val = sizeval >> 1; |
| 47 | |
Prafulla Wadaskar | f9c72f6 | 2010-08-26 14:43:55 +0530 | [diff] [blame] | 48 | for (i = 0; val >= 0x10000; i++) { |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 49 | j |= (1 << i); |
| 50 | val = val >> 1; |
| 51 | } |
| 52 | return (0x0000ffff & j); |
| 53 | } |
| 54 | |
Chris Packham | 968856c | 2019-03-13 20:47:03 +1300 | [diff] [blame] | 55 | static struct mbus_win windows[] = { |
| 56 | /* Window 0: PCIE MEM address space */ |
| 57 | { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256, |
| 58 | KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM }, |
| 59 | |
| 60 | /* Window 1: PCIE IO address space */ |
| 61 | { KW_DEFADR_PCI_IO, 1024 * 64, |
| 62 | KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO }, |
| 63 | |
| 64 | /* Window 2: NAND Flash address space */ |
| 65 | { KW_DEFADR_NANDF, 1024 * 1024 * 128, |
| 66 | KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH }, |
| 67 | |
| 68 | /* Window 3: SPI Flash address space */ |
| 69 | { KW_DEFADR_SPIF, 1024 * 1024 * 128, |
| 70 | KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH }, |
| 71 | |
| 72 | /* Window 4: BOOT Memory address space */ |
| 73 | { KW_DEFADR_BOOTROM, 1024 * 1024 * 128, |
| 74 | KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM }, |
| 75 | |
| 76 | /* Window 5: Security SRAM address space */ |
| 77 | { KW_DEFADR_SASRAM, 1024 * 64, |
| 78 | KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM }, |
| 79 | }; |
| 80 | |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 81 | /* |
Prafulla Wadaskar | 2906d77 | 2009-08-20 20:59:28 +0530 | [diff] [blame] | 82 | * SYSRSTn Duration Counter Support |
| 83 | * |
| 84 | * Kirkwood SoC implements a hardware-based SYSRSTn duration counter. |
| 85 | * When SYSRSTn is asserted low, a SYSRSTn duration counter is running. |
| 86 | * The SYSRSTn duration counter is useful for implementing a manufacturer |
| 87 | * or factory reset. Upon a long reset assertion that is greater than a |
| 88 | * pre-configured environment variable value for sysrstdelay, |
| 89 | * The counter value is stored in the SYSRSTn Length Counter Register |
| 90 | * The counter is based on the 25-MHz reference clock (40ns) |
| 91 | * It is a 29-bit counter, yielding a maximum counting duration of |
| 92 | * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value, |
| 93 | * it remains at this value until counter reset is triggered by setting |
| 94 | * bit 31 of KW_REG_SYSRST_CNT |
| 95 | */ |
| 96 | static void kw_sysrst_action(void) |
| 97 | { |
| 98 | int ret; |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 99 | char *s = env_get("sysrstcmd"); |
Prafulla Wadaskar | 2906d77 | 2009-08-20 20:59:28 +0530 | [diff] [blame] | 100 | |
| 101 | if (!s) { |
| 102 | debug("Error.. %s failed, check sysrstcmd\n", |
| 103 | __FUNCTION__); |
| 104 | return; |
| 105 | } |
| 106 | |
| 107 | debug("Starting %s process...\n", __FUNCTION__); |
Simon Glass | bf8c5b0 | 2012-02-14 19:59:21 +0000 | [diff] [blame] | 108 | ret = run_command(s, 0); |
Thomas Betker | 5ac0026 | 2014-06-05 20:07:56 +0200 | [diff] [blame] | 109 | if (ret != 0) |
Prafulla Wadaskar | 2906d77 | 2009-08-20 20:59:28 +0530 | [diff] [blame] | 110 | debug("Error.. %s failed\n", __FUNCTION__); |
| 111 | else |
| 112 | debug("%s process finished\n", __FUNCTION__); |
| 113 | } |
| 114 | |
| 115 | static void kw_sysrst_check(void) |
| 116 | { |
| 117 | u32 sysrst_cnt, sysrst_dly; |
| 118 | char *s; |
| 119 | |
| 120 | /* |
| 121 | * no action if sysrstdelay environment variable is not defined |
| 122 | */ |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 123 | s = env_get("sysrstdelay"); |
Prafulla Wadaskar | 2906d77 | 2009-08-20 20:59:28 +0530 | [diff] [blame] | 124 | if (s == NULL) |
| 125 | return; |
| 126 | |
| 127 | /* read sysrstdelay value */ |
| 128 | sysrst_dly = (u32) simple_strtoul(s, NULL, 10); |
| 129 | |
| 130 | /* read SysRst Length counter register (bits 28:0) */ |
| 131 | sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT)); |
| 132 | debug("H/w Rst hold time: %d.%d secs\n", |
| 133 | sysrst_cnt / SYSRST_CNT_1SEC_VAL, |
| 134 | sysrst_cnt % SYSRST_CNT_1SEC_VAL); |
| 135 | |
| 136 | /* clear the counter for next valid read*/ |
| 137 | writel(1 << 31, KW_REG_SYSRST_CNT); |
| 138 | |
| 139 | /* |
| 140 | * sysrst_action: |
| 141 | * if H/w Reset key is pressed and hold for time |
| 142 | * more than sysrst_dly in seconds |
| 143 | */ |
| 144 | if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly) |
| 145 | kw_sysrst_action(); |
| 146 | } |
| 147 | |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 148 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 149 | int print_cpuinfo(void) |
| 150 | { |
Luka Perkov | f680edb | 2013-12-23 01:23:07 +0100 | [diff] [blame] | 151 | char *rev = "??"; |
Prafulla Wadaskar | 3149629 | 2010-09-20 17:19:42 +0530 | [diff] [blame] | 152 | u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; |
| 153 | u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 154 | |
Prafulla Wadaskar | 3149629 | 2010-09-20 17:19:42 +0530 | [diff] [blame] | 155 | if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) { |
| 156 | printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid); |
| 157 | return -1; |
| 158 | } |
| 159 | |
| 160 | switch (revid) { |
| 161 | case 0: |
Luka Perkov | f680edb | 2013-12-23 01:23:07 +0100 | [diff] [blame] | 162 | if (devid == 0x6281) |
| 163 | rev = "Z0"; |
| 164 | else if (devid == 0x6282) |
| 165 | rev = "A0"; |
| 166 | break; |
| 167 | case 1: |
| 168 | rev = "A1"; |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 169 | break; |
| 170 | case 2: |
Prafulla Wadaskar | 3149629 | 2010-09-20 17:19:42 +0530 | [diff] [blame] | 171 | rev = "A0"; |
| 172 | break; |
| 173 | case 3: |
| 174 | rev = "A1"; |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 175 | break; |
| 176 | default: |
Prafulla Wadaskar | 3149629 | 2010-09-20 17:19:42 +0530 | [diff] [blame] | 177 | break; |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 178 | } |
Prafulla Wadaskar | 3149629 | 2010-09-20 17:19:42 +0530 | [diff] [blame] | 179 | |
| 180 | printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev); |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 181 | return 0; |
| 182 | } |
| 183 | #endif /* CONFIG_DISPLAY_CPUINFO */ |
| 184 | |
| 185 | #ifdef CONFIG_ARCH_CPU_INIT |
| 186 | int arch_cpu_init(void) |
| 187 | { |
| 188 | u32 reg; |
| 189 | struct kwcpu_registers *cpureg = |
| 190 | (struct kwcpu_registers *)KW_CPU_REG_BASE; |
| 191 | |
Chris Packham | 968856c | 2019-03-13 20:47:03 +1300 | [diff] [blame] | 192 | /* Linux expects the internal registers to be at 0xf1000000 */ |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 193 | writel(KW_REGS_PHY_BASE, KW_OFFSET_REG); |
| 194 | |
| 195 | /* Enable and invalidate L2 cache in write through mode */ |
| 196 | writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg); |
| 197 | invalidate_l2_cache(); |
| 198 | |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 199 | #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8 |
| 200 | /* |
| 201 | * Configures the I/O voltage of the pads connected to Egigabit |
| 202 | * Ethernet interface to 1.8V |
Robert P. J. Day | 832d36e | 2013-09-16 07:15:45 -0400 | [diff] [blame] | 203 | * By default it is set to 3.3V |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 204 | */ |
| 205 | reg = readl(KW_REG_MPP_OUT_DRV_REG); |
| 206 | reg |= (1 << 7); |
| 207 | writel(reg, KW_REG_MPP_OUT_DRV_REG); |
| 208 | #endif |
| 209 | #ifdef CONFIG_KIRKWOOD_EGIGA_INIT |
| 210 | /* |
| 211 | * Set egiga port0/1 in normal functional mode |
| 212 | * This is required becasue on kirkwood by default ports are in reset mode |
| 213 | * OS egiga driver may not have provision to set them in normal mode |
| 214 | * and if u-boot is build without network support, network may fail at OS level |
| 215 | */ |
| 216 | reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0)); |
| 217 | reg &= ~(1 << 4); /* Clear PortReset Bit */ |
| 218 | writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0))); |
| 219 | reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1)); |
| 220 | reg &= ~(1 << 4); /* Clear PortReset Bit */ |
| 221 | writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1))); |
| 222 | #endif |
| 223 | #ifdef CONFIG_KIRKWOOD_PCIE_INIT |
| 224 | /* |
| 225 | * Enable PCI Express Port0 |
| 226 | */ |
| 227 | reg = readl(&cpureg->ctrl_stat); |
| 228 | reg |= (1 << 0); /* Set PEX0En Bit */ |
| 229 | writel(reg, &cpureg->ctrl_stat); |
| 230 | #endif |
| 231 | return 0; |
| 232 | } |
| 233 | #endif /* CONFIG_ARCH_CPU_INIT */ |
| 234 | |
| 235 | /* |
| 236 | * SOC specific misc init |
| 237 | */ |
| 238 | #if defined(CONFIG_ARCH_MISC_INIT) |
| 239 | int arch_misc_init(void) |
| 240 | { |
| 241 | volatile u32 temp; |
| 242 | |
| 243 | /*CPU streaming & write allocate */ |
| 244 | temp = readfr_extra_feature_reg(); |
| 245 | temp &= ~(1 << 28); /* disable wr alloc */ |
| 246 | writefr_extra_feature_reg(temp); |
| 247 | |
| 248 | temp = readfr_extra_feature_reg(); |
| 249 | temp &= ~(1 << 29); /* streaming disabled */ |
| 250 | writefr_extra_feature_reg(temp); |
| 251 | |
| 252 | /* L2Cache settings */ |
| 253 | temp = readfr_extra_feature_reg(); |
| 254 | /* Disable L2C pre fetch - Set bit 24 */ |
| 255 | temp |= (1 << 24); |
| 256 | /* enable L2C - Set bit 22 */ |
| 257 | temp |= (1 << 22); |
| 258 | writefr_extra_feature_reg(temp); |
| 259 | |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 260 | /* Change reset vector to address 0x0 */ |
| 261 | temp = get_cr(); |
| 262 | set_cr(temp & ~CR_V); |
| 263 | |
Chris Packham | 968856c | 2019-03-13 20:47:03 +1300 | [diff] [blame] | 264 | /* Configure mbus windows */ |
| 265 | mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); |
| 266 | |
Prafulla Wadaskar | 2906d77 | 2009-08-20 20:59:28 +0530 | [diff] [blame] | 267 | /* checks and execute resset to factory event */ |
| 268 | kw_sysrst_check(); |
| 269 | |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 270 | return 0; |
| 271 | } |
| 272 | #endif /* CONFIG_ARCH_MISC_INIT */ |
| 273 | |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 274 | #ifdef CONFIG_MVGBE |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 275 | int cpu_eth_init(struct bd_info *bis) |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 276 | { |
Albert Aribaud | e91d7d3 | 2010-07-12 22:24:28 +0200 | [diff] [blame] | 277 | mvgbe_initialize(bis); |
Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 278 | return 0; |
| 279 | } |
| 280 | #endif |
DrEagle | ad88174 | 2014-07-25 21:07:30 +0200 | [diff] [blame] | 281 | |
| 282 | #ifdef CONFIG_MVEBU_MMC |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 283 | int board_mmc_init(struct bd_info *bis) |
DrEagle | ad88174 | 2014-07-25 21:07:30 +0200 | [diff] [blame] | 284 | { |
| 285 | mvebu_mmc_init(bis); |
| 286 | return 0; |
| 287 | } |
| 288 | #endif /* CONFIG_MVEBU_MMC */ |