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Ye Li0db17f42021-08-07 16:00:41 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2021 NXP
4 */
5
6#ifndef __S400_API_H__
7#define __S400_API_H__
8
9#define AHAB_VERSION 0x6
10#define AHAB_CMD_TAG 0x17
11#define AHAB_RESP_TAG 0xe1
12
13#define AHAB_LOG_CID 0x21
14#define AHAB_AUTH_OEM_CTNR_CID 0x87
15#define AHAB_VERIFY_IMG_CID 0x88
16#define AHAB_RELEASE_CTNR_CID 0x89
Ye Lif80a41b2021-08-07 16:00:54 +080017#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91
Ye Lia61f2672021-08-07 16:00:52 +080018#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
Ye Lif80a41b2021-08-07 16:00:54 +080019#define AHAB_READ_FUSE_REQ_CID 0x97
20#define AHAB_RELEASE_RDC_REQ_CID 0xC4
21#define AHAB_WRITE_FUSE_REQ_CID 0xD6
Clement Faure26386ae2022-04-06 14:30:19 +080022#define AHAB_CAAM_RELEASE_CID 0xD7
Ye Li0db17f42021-08-07 16:00:41 +080023
24#define S400_MAX_MSG 8U
25
26struct imx8ulp_s400_msg {
27 u8 version;
28 u8 size;
29 u8 command;
30 u8 tag;
31 u32 data[(S400_MAX_MSG - 1U)];
32};
33
Ye Liacc9afe2021-08-07 16:00:53 +080034int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response);
Ye Lia61f2672021-08-07 16:00:52 +080035int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
36int ahab_release_container(u32 *response);
37int ahab_verify_image(u32 img_id, u32 *response);
38int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
Ye Lif80a41b2021-08-07 16:00:54 +080039int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
40int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
Clement Faure26386ae2022-04-06 14:30:19 +080041int ahab_release_caam(u32 core_did, u32 *response);
Ye Lia61f2672021-08-07 16:00:52 +080042
Ye Li0db17f42021-08-07 16:00:41 +080043#endif