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Eric Benard2e66f3b2014-04-04 19:05:55 +02001/*
2 * Copyright (C) 2014 Eukréa Electromatique
3 * Author: Eric Bénard <eric@eukrea.com>
4 *
5 * Configuration settings for the Embest RIoTboard
6 *
7 * based on mx6*sabre*.h which are :
8 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#ifndef __RIOTBOARD_CONFIG_H
14#define __RIOTBOARD_CONFIG_H
15
Eric Benard2e66f3b2014-04-04 19:05:55 +020016#define CONFIG_MXC_UART_BASE UART2_BASE
Simon Glass4694a742016-10-17 20:12:39 -060017#define CONSOLE_DEV "ttymxc1"
Eric Benard2e66f3b2014-04-04 19:05:55 +020018
19#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
20
Adrian Alonsoce08c362015-09-02 13:54:13 -050021#define CONFIG_IMX_THERMAL
Eric Benard2e66f3b2014-04-04 19:05:55 +020022
23/* Size of malloc() pool */
24#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
25
Eric Benard2e66f3b2014-04-04 19:05:55 +020026#define CONFIG_MXC_UART
27
Eric Benard2e66f3b2014-04-04 19:05:55 +020028/* I2C Configs */
Eric Benard2e66f3b2014-04-04 19:05:55 +020029#define CONFIG_SYS_I2C
30#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +020031#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
32#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf1a52162015-03-20 10:20:40 -070033#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Eric Benard2e66f3b2014-04-04 19:05:55 +020034#define CONFIG_SYS_I2C_SPEED 100000
35
36/* USB Configs */
Eric Benard2e66f3b2014-04-04 19:05:55 +020037#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
38#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
39#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
40#define CONFIG_MXC_USB_FLAGS 0
41
42/* MMC Configs */
Eric Benard2e66f3b2014-04-04 19:05:55 +020043#define CONFIG_SYS_FSL_ESDHC_ADDR 0
44
Eric Benard2e66f3b2014-04-04 19:05:55 +020045#define CONFIG_FEC_MXC
46#define CONFIG_MII
47#define IMX_FEC_BASE ENET_BASE_ADDR
48#define CONFIG_FEC_XCV_TYPE RGMII
49#define CONFIG_ETHPRIME "FEC"
50#define CONFIG_FEC_MXC_PHYADDR 4
51
Eric Benard2e66f3b2014-04-04 19:05:55 +020052#define CONFIG_PHY_ATHEROS
53
Eric Benard2e66f3b2014-04-04 19:05:55 +020054#ifdef CONFIG_CMD_SF
Eric Benard2e66f3b2014-04-04 19:05:55 +020055#define CONFIG_SF_DEFAULT_BUS 0
Nikita Kiryanov00cd7382014-08-20 15:08:50 +030056#define CONFIG_SF_DEFAULT_CS 0
Eric Benard2e66f3b2014-04-04 19:05:55 +020057#define CONFIG_SF_DEFAULT_SPEED 20000000
58#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
59#endif
60
Eric Benard2e66f3b2014-04-04 19:05:55 +020061#define CONFIG_ARP_TIMEOUT 200UL
62
Eric Benard2e66f3b2014-04-04 19:05:55 +020063#define CONFIG_SYS_MEMTEST_START 0x10000000
64#define CONFIG_SYS_MEMTEST_END 0x10010000
65#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
66
Eric Benard2e66f3b2014-04-04 19:05:55 +020067/* Physical Memory Map */
68#define CONFIG_NR_DRAM_BANKS 1
69#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
70
71#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
72#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
73#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
74
75#define CONFIG_SYS_INIT_SP_OFFSET \
76 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
77#define CONFIG_SYS_INIT_SP_ADDR \
78 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
79
Peter Robinson4b671502015-05-22 17:30:45 +010080/* Environment organization */
Eric Benard2e66f3b2014-04-04 19:05:55 +020081#define CONFIG_ENV_SIZE (8 * 1024)
82
83#if defined(CONFIG_ENV_IS_IN_MMC)
84/* RiOTboard */
Iain Patone90c9ab2014-12-14 14:51:46 +000085#define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
Eric Benard2e66f3b2014-04-04 19:05:55 +020086#define CONFIG_SYS_FSL_USDHC_NUM 3
87#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */
88#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
89#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
90#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
91/* MarSBoard */
Iain Patone90c9ab2014-12-14 14:51:46 +000092#define CONFIG_FDTFILE "imx6q-marsboard.dtb"
Eric Benard2e66f3b2014-04-04 19:05:55 +020093#define CONFIG_SYS_FSL_USDHC_NUM 2
94#define CONFIG_ENV_OFFSET (768 * 1024)
95#define CONFIG_ENV_SECT_SIZE (8 * 1024)
96#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
97#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
98#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
99#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
100#endif
101
Eric Benard2e66f3b2014-04-04 19:05:55 +0200102/* Framebuffer */
Eric Benard2e66f3b2014-04-04 19:05:55 +0200103#define CONFIG_VIDEO_IPUV3
Eric Benard2e66f3b2014-04-04 19:05:55 +0200104#define CONFIG_VIDEO_BMP_RLE8
105#define CONFIG_SPLASH_SCREEN
106#define CONFIG_SPLASH_SCREEN_ALIGN
107#define CONFIG_BMP_16BPP
108#define CONFIG_VIDEO_LOGO
109#define CONFIG_VIDEO_BMP_LOGO
Eric Benard2e66f3b2014-04-04 19:05:55 +0200110#define CONFIG_IMX_HDMI
111#define CONFIG_IMX_VIDEO_SKIP
112
Iain Paton2e891152014-12-14 14:51:32 +0000113#include <config_distro_defaults.h>
Peter Robinsonbe6c5f12015-05-22 17:30:52 +0100114#include "mx6_common.h"
Iain Paton2e891152014-12-14 14:51:32 +0000115
Iain Patone90c9ab2014-12-14 14:51:46 +0000116/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
117 * 1M script, 1M pxe and the ramdisk at the end */
118#define MEM_LAYOUT_ENV_SETTINGS \
119 "bootm_size=0x10000000\0" \
120 "kernel_addr_r=0x12000000\0" \
121 "fdt_addr_r=0x13000000\0" \
122 "scriptaddr=0x13100000\0" \
123 "pxefile_addr_r=0x13200000\0" \
124 "ramdisk_addr_r=0x13300000\0"
125
126#define BOOT_TARGET_DEVICES(func) \
127 func(MMC, mmc, 0) \
128 func(MMC, mmc, 1) \
129 func(MMC, mmc, 2) \
130 func(USB, usb, 0) \
131 func(PXE, pxe, na) \
132 func(DHCP, dhcp, na)
133
134#include <config_distro_bootcmd.h>
135
136#define CONSOLE_STDIN_SETTINGS \
137 "stdin=serial\0"
138
139#define CONSOLE_STDOUT_SETTINGS \
140 "stdout=serial\0" \
141 "stderr=serial\0"
142
143#define CONSOLE_ENV_SETTINGS \
144 CONSOLE_STDIN_SETTINGS \
145 CONSOLE_STDOUT_SETTINGS
146
147#define CONFIG_EXTRA_ENV_SETTINGS \
148 CONSOLE_ENV_SETTINGS \
149 MEM_LAYOUT_ENV_SETTINGS \
150 "fdtfile=" CONFIG_FDTFILE "\0" \
Fabio Bertoncd681b22017-07-10 17:04:11 -0300151 "finduuid=part uuid mmc 0:1 uuid\0" \
Iain Patone90c9ab2014-12-14 14:51:46 +0000152 BOOTENV
153
Eric Benard2e66f3b2014-04-04 19:05:55 +0200154#endif /* __RIOTBOARD_CONFIG_H */