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Chandan Nath1c959692011-10-14 02:58:22 +00001/*
2 * sys_info.c
3 *
4 * System information functions
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
11 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath1c959692011-10-14 02:58:22 +000013 */
14
15#include <common.h>
16#include <asm/io.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/arch/cpu.h>
19#include <asm/arch/clock.h>
Tom Rini52437072013-08-30 16:28:46 -040020#include <power/tps65910.h>
Igor Grinbergd5e635e2014-11-05 13:29:54 +020021#include <linux/compiler.h>
Chandan Nath1c959692011-10-14 02:58:22 +000022
23struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
24
25/**
26 * get_cpu_rev(void) - extract rev info
27 */
28u32 get_cpu_rev(void)
29{
30 u32 id;
31 u32 rev;
32
33 id = readl(DEVICE_ID);
34 rev = (id >> 28) & 0xff;
35
36 return rev;
37}
38
39/**
40 * get_cpu_type(void) - extract cpu info
41 */
42u32 get_cpu_type(void)
43{
44 u32 id = 0;
45 u32 partnum;
46
47 id = readl(DEVICE_ID);
48 partnum = (id >> 12) & 0xffff;
49
50 return partnum;
51}
52
53/**
Chandan Nath1c959692011-10-14 02:58:22 +000054 * get_sysboot_value(void) - return SYS_BOOT[4:0]
55 */
56u32 get_sysboot_value(void)
57{
Masahiro Yamada04cfea52016-09-06 22:17:38 +090058 return readl(&cstat->statusreg) & SYSBOOT_MASK;
Chandan Nath1c959692011-10-14 02:58:22 +000059}
60
Lokesh Vutla6302e532017-05-05 12:59:10 +053061u32 get_sys_clk_index(void)
62{
63 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
64 u32 ind = readl(&ctrl->statusreg);
65
66#ifdef CONFIG_AM43XX
67 u32 src;
68 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
69 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
70 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
71 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
72 else /* Value read from SYS BOOT pins */
73#endif
74 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
75 CTRL_SYSBOOT_15_14_SHIFT);
76}
77
78
Chandan Nath1c959692011-10-14 02:58:22 +000079#ifdef CONFIG_DISPLAY_CPUINFO
Sergey Alyoshin8e796c42014-05-22 11:56:03 +040080static char *cpu_revs[] = {
81 "1.0",
82 "2.0",
83 "2.1"};
84
Tero Kristo21bc35e2017-03-16 09:48:54 +020085static char *cpu_revs_am43xx[] = {
86 "1.0",
87 "1.1",
88 "1.2"};
Sergey Alyoshin8e796c42014-05-22 11:56:03 +040089
90static char *dev_types[] = {
91 "TST",
92 "EMU",
93 "HS",
94 "GP"};
95
Chandan Nath1c959692011-10-14 02:58:22 +000096/**
97 * Print CPU information
98 */
99int print_cpuinfo(void)
100{
Sergey Alyoshin8e796c42014-05-22 11:56:03 +0400101 char *cpu_s, *sec_s, *rev_s;
Tero Kristo21bc35e2017-03-16 09:48:54 +0200102 char **cpu_rev_arr = cpu_revs;
Chandan Nath1c959692011-10-14 02:58:22 +0000103
104 switch (get_cpu_type()) {
105 case AM335X:
106 cpu_s = "AM335X";
107 break;
Matt Porter691fbe32013-03-15 10:07:06 +0000108 case TI81XX:
109 cpu_s = "TI81XX";
110 break;
Lokesh Vutla72996bf2016-10-04 09:34:50 +0530111 case AM437X:
112 cpu_s = "AM437X";
Tero Kristo21bc35e2017-03-16 09:48:54 +0200113 cpu_rev_arr = cpu_revs_am43xx;
Lokesh Vutla72996bf2016-10-04 09:34:50 +0530114 break;
Chandan Nath1c959692011-10-14 02:58:22 +0000115 default:
Sergey Alyoshin8e796c42014-05-22 11:56:03 +0400116 cpu_s = "Unknown CPU type";
Chandan Nath1c959692011-10-14 02:58:22 +0000117 break;
118 }
119
Sergey Alyoshin8e796c42014-05-22 11:56:03 +0400120 if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
Tero Kristo21bc35e2017-03-16 09:48:54 +0200121 rev_s = cpu_rev_arr[get_cpu_rev()];
Sergey Alyoshin8e796c42014-05-22 11:56:03 +0400122 else
123 rev_s = "?";
124
125 if (get_device_type() < ARRAY_SIZE(dev_types))
126 sec_s = dev_types[get_device_type()];
127 else
Chandan Nath1c959692011-10-14 02:58:22 +0000128 sec_s = "?";
Chandan Nath1c959692011-10-14 02:58:22 +0000129
Lokesh Vutla72996bf2016-10-04 09:34:50 +0530130 printf("CPU : %s-%s rev %s\n", cpu_s, sec_s, rev_s);
Chandan Nath1c959692011-10-14 02:58:22 +0000131
132 return 0;
133}
134#endif /* CONFIG_DISPLAY_CPUINFO */
Tom Rini52437072013-08-30 16:28:46 -0400135
136#ifdef CONFIG_AM33XX
137int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
138{
139 int sil_rev;
140
141 sil_rev = readl(&cdev->deviceid) >> 28;
142
Lokesh Vutla1bda3732017-05-05 12:59:08 +0530143 if (sil_rev == 0) {
144 /* No efuse in PG 1.0. Use max speed */
145 return MPUPLL_M_720;
146 } else if (sil_rev >= 1) {
Tom Rini52437072013-08-30 16:28:46 -0400147 /* Check what the efuse says our max speed is. */
Lokesh Vutla1bda3732017-05-05 12:59:08 +0530148 int efuse_arm_mpu_max_freq, package_type;
Tom Rini52437072013-08-30 16:28:46 -0400149 efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
Lokesh Vutla1bda3732017-05-05 12:59:08 +0530150 package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
151 PACKAGE_TYPE_SHIFT;
152
153 /* PG 2.0, efuse may not be set. */
154 if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
155 PACKAGE_TYPE_RESERVED)
156 return MPUPLL_M_800;
157
Tom Rini52437072013-08-30 16:28:46 -0400158 switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
159 case AM335X_ZCZ_1000:
160 return MPUPLL_M_1000;
161 case AM335X_ZCZ_800:
162 return MPUPLL_M_800;
163 case AM335X_ZCZ_720:
164 return MPUPLL_M_720;
165 case AM335X_ZCZ_600:
166 case AM335X_ZCE_600:
167 return MPUPLL_M_600;
168 case AM335X_ZCZ_300:
169 case AM335X_ZCE_300:
170 return MPUPLL_M_300;
171 }
172 }
173
Lokesh Vutla1bda3732017-05-05 12:59:08 +0530174 /* unknown, use the PG1.0 max */
Tom Rini52437072013-08-30 16:28:46 -0400175 return MPUPLL_M_720;
176}
177
Felix Brack17705ac2017-10-11 18:42:23 +0200178int am335x_get_mpu_vdd(int sil_rev, int frequency)
179{
180 int sel_mask = am335x_get_tps65910_mpu_vdd(sil_rev, frequency);
181
182 switch (sel_mask) {
183 case TPS65910_OP_REG_SEL_1_3_2_5:
184 return 1325000;
185 case TPS65910_OP_REG_SEL_1_2_0:
186 return 1200000;
187 case TPS65910_OP_REG_SEL_1_1_0:
188 return 1100000;
189 default:
190 return 1262500;
191 }
192}
193
Tom Rini52437072013-08-30 16:28:46 -0400194int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
195{
Lokesh Vutla1bda3732017-05-05 12:59:08 +0530196 /* For PG2.0 and later, we have one set of values. */
197 if (sil_rev >= 1) {
Tom Rini52437072013-08-30 16:28:46 -0400198 switch (frequency) {
199 case MPUPLL_M_1000:
200 return TPS65910_OP_REG_SEL_1_3_2_5;
201 case MPUPLL_M_800:
202 return TPS65910_OP_REG_SEL_1_2_6;
203 case MPUPLL_M_720:
204 return TPS65910_OP_REG_SEL_1_2_0;
205 case MPUPLL_M_600:
Lokesh Vutla1bda3732017-05-05 12:59:08 +0530206 case MPUPLL_M_500:
Tom Rini52437072013-08-30 16:28:46 -0400207 case MPUPLL_M_300:
Lokesh Vutla1bda3732017-05-05 12:59:08 +0530208 return TPS65910_OP_REG_SEL_1_1_0;
Tom Rini52437072013-08-30 16:28:46 -0400209 }
210 }
211
Lokesh Vutla1bda3732017-05-05 12:59:08 +0530212 /* Default to PG1.0 values. */
213 return TPS65910_OP_REG_SEL_1_2_6;
Tom Rini52437072013-08-30 16:28:46 -0400214}
215#endif