blob: 55e30346ff12595879f7cd497f59d54bc36f73fc [file] [log] [blame]
Green Wan7f337432021-05-27 06:52:07 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020-201 SiFive, Inc
4 * Pragnesh Patel <pragnesh.patel@sifive.com>
5 */
6
7#include <dm.h>
8#include <log.h>
Green Wan26190b82021-05-27 06:52:14 -07009#include <asm/csr.h>
10
11#define CSR_U74_FEATURE_DISABLE 0x7c1
Green Wan7f337432021-05-27 06:52:07 -070012
13int spl_soc_init(void)
14{
15 int ret;
16 struct udevice *dev;
17
18 /* DDR init */
19 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
20 if (ret) {
21 debug("DRAM init failed: %d\n", ret);
22 return ret;
23 }
24
25 return 0;
26}
Green Wan26190b82021-05-27 06:52:14 -070027
28void harts_early_init(void)
29{
30 /*
31 * Feature Disable CSR
32 *
33 * Clear feature disable CSR to '0' to turn on all features for
34 * each core. This operation must be in M-mode.
35 */
36 if (CONFIG_IS_ENABLED(RISCV_MMODE))
37 csr_write(CSR_U74_FEATURE_DISABLE, 0);
38}