blob: 42b41fbf62619e4e823b83a9de92b27fb25e95a1 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -06007 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -07008
Simon Glassfef72b72014-07-23 06:55:03 -06009 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060011 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070012 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060013 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060014 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass0ccb0972015-01-25 08:27:05 -070016 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060017 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070019 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070021 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -050022 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060024 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060026 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020027 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070028 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020034 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060038 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020041 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020042 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060043 };
44
Simon Glassed96cde2018-12-10 10:37:33 -070045 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glassc953aaf2018-12-10 10:37:34 -070050 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060051 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Yannick Fertré9712c822019-10-07 15:29:05 +020079 dsi_host: dsi_host {
80 compatible = "sandbox,dsi-host";
81 };
82
Simon Glassb2c1cac2014-02-26 15:59:21 -070083 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -060084 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070085 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -060086 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070087 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -060088 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -070089 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
90 <0>, <&gpio_a 12>;
91 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
92 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
93 <&gpio_b 9 0xc 3 2 1>;
Simon Glass6df01f92018-12-10 10:37:37 -070094 int-value = <1234>;
95 uint-value = <(-1234)>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070096 };
97
98 junk {
Simon Glasscf61f742015-07-06 12:54:36 -060099 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700100 compatible = "not,compatible";
101 };
102
103 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600104 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700105 };
106
Simon Glass5620cf82018-10-01 12:22:40 -0600107 backlight: backlight {
108 compatible = "pwm-backlight";
109 enable-gpios = <&gpio_a 1>;
110 power-supply = <&ldo_1>;
111 pwms = <&pwm 0 1000>;
112 default-brightness-level = <5>;
113 brightness-levels = <0 16 32 64 128 170 202 234 255>;
114 };
115
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200116 bind-test {
117 bind-test-child1 {
118 compatible = "sandbox,phy";
119 #phy-cells = <1>;
120 };
121
122 bind-test-child2 {
123 compatible = "simple-bus";
124 };
125 };
126
Simon Glassb2c1cac2014-02-26 15:59:21 -0700127 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600128 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700129 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600130 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700131 ping-add = <3>;
132 };
133
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200134 phy_provider0: gen_phy@0 {
135 compatible = "sandbox,phy";
136 #phy-cells = <1>;
137 };
138
139 phy_provider1: gen_phy@1 {
140 compatible = "sandbox,phy";
141 #phy-cells = <0>;
142 broken;
143 };
144
145 gen_phy_user: gen_phy_user {
146 compatible = "simple-bus";
147 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
148 phy-names = "phy1", "phy2", "phy3";
149 };
150
Simon Glassb2c1cac2014-02-26 15:59:21 -0700151 some-bus {
152 #address-cells = <1>;
153 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600154 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600155 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600156 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700157 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600158 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700159 compatible = "denx,u-boot-fdt-test";
160 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600161 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700162 ping-add = <5>;
163 };
Simon Glass40717422014-07-23 06:55:18 -0600164 c-test@0 {
165 compatible = "denx,u-boot-fdt-test";
166 reg = <0>;
167 ping-expect = <6>;
168 ping-add = <6>;
169 };
170 c-test@1 {
171 compatible = "denx,u-boot-fdt-test";
172 reg = <1>;
173 ping-expect = <7>;
174 ping-add = <7>;
175 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700176 };
177
178 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600179 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600180 ping-expect = <6>;
181 ping-add = <6>;
182 compatible = "google,another-fdt-test";
183 };
184
185 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600186 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600187 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700188 ping-add = <6>;
189 compatible = "google,another-fdt-test";
190 };
191
Simon Glass0ccb0972015-01-25 08:27:05 -0700192 f-test {
193 compatible = "denx,u-boot-fdt-test";
194 };
195
196 g-test {
197 compatible = "denx,u-boot-fdt-test";
198 };
199
Bin Mengd9d24782018-10-10 22:07:01 -0700200 h-test {
201 compatible = "denx,u-boot-fdt-test1";
202 };
203
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200204 clocks {
205 clk_fixed: clk-fixed {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <1234>;
209 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000210
211 clk_fixed_factor: clk-fixed-factor {
212 compatible = "fixed-factor-clock";
213 #clock-cells = <0>;
214 clock-div = <3>;
215 clock-mult = <2>;
216 clocks = <&clk_fixed>;
217 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200218
219 osc {
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <20000000>;
223 };
Stephen Warrena9622432016-06-17 09:44:00 -0600224 };
225
226 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600227 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600228 #clock-cells = <1>;
229 };
230
231 clk-test {
232 compatible = "sandbox,clk-test";
233 clocks = <&clk_fixed>,
234 <&clk_sandbox 1>,
235 <&clk_sandbox 0>;
236 clock-names = "fixed", "i2c", "spi";
Simon Glass8cc4d822015-07-06 12:54:24 -0600237 };
238
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200239 ccf: clk-ccf {
240 compatible = "sandbox,clk-ccf";
241 };
242
Simon Glass5b968632015-05-22 15:42:15 -0600243 eth@10002000 {
244 compatible = "sandbox,eth";
245 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500246 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600247 };
248
249 eth_5: eth@10003000 {
250 compatible = "sandbox,eth";
251 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500252 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600253 };
254
Bin Meng04a11cb2015-08-27 22:25:53 -0700255 eth_3: sbe5 {
256 compatible = "sandbox,eth";
257 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500258 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700259 };
260
Simon Glass5b968632015-05-22 15:42:15 -0600261 eth@10004000 {
262 compatible = "sandbox,eth";
263 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500264 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600265 };
266
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700267 firmware {
268 sandbox_firmware: sandbox-firmware {
269 compatible = "sandbox,firmware";
270 };
271 };
272
Simon Glass25348a42014-10-13 23:42:11 -0600273 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700274 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700275 gpio-controller;
276 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700277 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700278 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700279 };
280
Simon Glass16e10402015-01-05 20:05:29 -0700281 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700282 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700283 gpio-controller;
284 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700285 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700286 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700287 };
Simon Glass25348a42014-10-13 23:42:11 -0600288
Simon Glass7df766e2014-12-10 08:55:55 -0700289 i2c@0 {
290 #address-cells = <1>;
291 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600292 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700293 compatible = "sandbox,i2c";
294 clock-frequency = <100000>;
295 eeprom@2c {
296 reg = <0x2c>;
297 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700298 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700299 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200300
Simon Glass336b2952015-05-22 15:42:17 -0600301 rtc_0: rtc@43 {
302 reg = <0x43>;
303 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700304 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600305 };
306
307 rtc_1: rtc@61 {
308 reg = <0x61>;
309 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700310 sandbox,emul = <&emul1>;
311 };
312
313 i2c_emul: emul {
314 reg = <0xff>;
315 compatible = "sandbox,i2c-emul-parent";
316 emul_eeprom: emul-eeprom {
317 compatible = "sandbox,i2c-eeprom";
318 sandbox,filename = "i2c.bin";
319 sandbox,size = <256>;
320 };
321 emul0: emul0 {
322 compatible = "sandbox,i2c-rtc";
323 };
324 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600325 compatible = "sandbox,i2c-rtc";
326 };
327 };
328
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200329 sandbox_pmic: sandbox_pmic {
330 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700331 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200332 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200333
334 mc34708: pmic@41 {
335 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700336 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200337 };
Simon Glass7df766e2014-12-10 08:55:55 -0700338 };
339
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100340 bootcount@0 {
341 compatible = "u-boot,bootcount-rtc";
342 rtc = <&rtc_1>;
343 offset = <0x13>;
344 };
345
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100346 adc@0 {
347 compatible = "sandbox,adc";
348 vdd-supply = <&buck2>;
349 vss-microvolts = <0>;
350 };
351
Simon Glass90b6fef2016-01-18 19:52:26 -0700352 lcd {
353 u-boot,dm-pre-reloc;
354 compatible = "sandbox,lcd-sdl";
355 xres = <1366>;
356 yres = <768>;
357 };
358
Simon Glassd783eb32015-07-06 12:54:34 -0600359 leds {
360 compatible = "gpio-leds";
361
362 iracibble {
363 gpios = <&gpio_a 1 0>;
364 label = "sandbox:red";
365 };
366
367 martinet {
368 gpios = <&gpio_a 2 0>;
369 label = "sandbox:green";
370 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200371
372 default_on {
373 gpios = <&gpio_a 5 0>;
374 label = "sandbox:default_on";
375 default-state = "on";
376 };
377
378 default_off {
379 gpios = <&gpio_a 6 0>;
380 label = "sandbox:default_off";
381 default-state = "off";
382 };
Simon Glassd783eb32015-07-06 12:54:34 -0600383 };
384
Stephen Warren62f2c902016-05-16 17:41:37 -0600385 mbox: mbox {
386 compatible = "sandbox,mbox";
387 #mbox-cells = <1>;
388 };
389
390 mbox-test {
391 compatible = "sandbox,mbox-test";
392 mboxes = <&mbox 100>, <&mbox 1>;
393 mbox-names = "other", "test";
394 };
395
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900396 cpus {
397 cpu-test1 {
398 compatible = "sandbox,cpu_sandbox";
399 u-boot,dm-pre-reloc;
400 };
Mario Sixdea5df72018-08-06 10:23:44 +0200401
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900402 cpu-test2 {
403 compatible = "sandbox,cpu_sandbox";
404 u-boot,dm-pre-reloc;
405 };
Mario Sixdea5df72018-08-06 10:23:44 +0200406
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900407 cpu-test3 {
408 compatible = "sandbox,cpu_sandbox";
409 u-boot,dm-pre-reloc;
410 };
Mario Sixdea5df72018-08-06 10:23:44 +0200411 };
412
Simon Glassc953aaf2018-12-10 10:37:34 -0700413 i2s: i2s {
414 compatible = "sandbox,i2s";
415 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700416 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700417 };
418
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200419 nop-test_0 {
420 compatible = "sandbox,nop_sandbox1";
421 nop-test_1 {
422 compatible = "sandbox,nop_sandbox2";
423 bind = "True";
424 };
425 nop-test_2 {
426 compatible = "sandbox,nop_sandbox2";
427 bind = "False";
428 };
429 };
430
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200431 misc-test {
432 compatible = "sandbox,misc_sandbox";
433 };
434
Simon Glasse4fef742017-04-23 20:02:07 -0600435 mmc2 {
436 compatible = "sandbox,mmc";
437 };
438
439 mmc1 {
440 compatible = "sandbox,mmc";
441 };
442
443 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600444 compatible = "sandbox,mmc";
445 };
446
Simon Glass53a68b32019-02-16 20:24:50 -0700447 pch {
448 compatible = "sandbox,pch";
449 };
450
Bin Meng408e5902018-08-03 01:14:41 -0700451 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700452 compatible = "sandbox,pci";
453 device_type = "pci";
454 #address-cells = <3>;
455 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600456 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700457 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700458 pci@0,0 {
459 compatible = "pci-generic";
460 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600461 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700462 };
Alex Margineanf1274432019-06-07 11:24:24 +0300463 pci@1,0 {
464 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600465 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
466 reg = <0x02000814 0 0 0 0
467 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600468 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300469 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700470 pci@1f,0 {
471 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600472 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
473 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600474 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700475 };
476 };
477
Simon Glassb98ba4c2019-09-25 08:56:10 -0600478 pci-emul0 {
479 compatible = "sandbox,pci-emul-parent";
480 swap_case_emul0_0: emul0@0,0 {
481 compatible = "sandbox,swap-case";
482 };
483 swap_case_emul0_1: emul0@1,0 {
484 compatible = "sandbox,swap-case";
485 use-ea;
486 };
487 swap_case_emul0_1f: emul0@1f,0 {
488 compatible = "sandbox,swap-case";
489 };
490 };
491
Bin Meng408e5902018-08-03 01:14:41 -0700492 pci1: pci-controller1 {
493 compatible = "sandbox,pci";
494 device_type = "pci";
495 #address-cells = <3>;
496 #size-cells = <2>;
497 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
498 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700499 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200500 0x0c 0x00 0x1234 0x5678
501 0x10 0x00 0x1234 0x5678>;
502 pci@10,0 {
503 reg = <0x8000 0 0 0 0>;
504 };
Bin Meng408e5902018-08-03 01:14:41 -0700505 };
506
Bin Meng510dddb2018-08-03 01:14:50 -0700507 pci2: pci-controller2 {
508 compatible = "sandbox,pci";
509 device_type = "pci";
510 #address-cells = <3>;
511 #size-cells = <2>;
512 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
513 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
514 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
515 pci@1f,0 {
516 compatible = "pci-generic";
517 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600518 sandbox,emul = <&swap_case_emul2_1f>;
519 };
520 };
521
522 pci-emul2 {
523 compatible = "sandbox,pci-emul-parent";
524 swap_case_emul2_1f: emul2@1f,0 {
525 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700526 };
527 };
528
Ramon Friedc64f19b2019-04-27 11:15:23 +0300529 pci_ep: pci_ep {
530 compatible = "sandbox,pci_ep";
531 };
532
Simon Glass9c433fe2017-04-23 20:10:44 -0600533 probing {
534 compatible = "simple-bus";
535 test1 {
536 compatible = "denx,u-boot-probe-test";
537 };
538
539 test2 {
540 compatible = "denx,u-boot-probe-test";
541 };
542
543 test3 {
544 compatible = "denx,u-boot-probe-test";
545 };
546
547 test4 {
548 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100549 first-syscon = <&syscon0>;
550 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100551 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600552 };
553 };
554
Stephen Warren92c67fa2016-07-13 13:45:31 -0600555 pwrdom: power-domain {
556 compatible = "sandbox,power-domain";
557 #power-domain-cells = <1>;
558 };
559
560 power-domain-test {
561 compatible = "sandbox,power-domain-test";
562 power-domains = <&pwrdom 2>;
563 };
564
Simon Glass5620cf82018-10-01 12:22:40 -0600565 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600566 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600567 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600568 };
569
570 pwm2 {
571 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600572 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600573 };
574
Simon Glass3d355e62015-07-06 12:54:31 -0600575 ram {
576 compatible = "sandbox,ram";
577 };
578
Simon Glassd860f222015-07-06 12:54:29 -0600579 reset@0 {
580 compatible = "sandbox,warm-reset";
581 };
582
583 reset@1 {
584 compatible = "sandbox,reset";
585 };
586
Stephen Warren6488e642016-06-17 09:43:59 -0600587 resetc: reset-ctl {
588 compatible = "sandbox,reset-ctl";
589 #reset-cells = <1>;
590 };
591
592 reset-ctl-test {
593 compatible = "sandbox,reset-ctl-test";
594 resets = <&resetc 100>, <&resetc 2>;
595 reset-names = "other", "test";
596 };
597
Nishanth Menonedf85812015-09-17 15:42:41 -0500598 rproc_1: rproc@1 {
599 compatible = "sandbox,test-processor";
600 remoteproc-name = "remoteproc-test-dev1";
601 };
602
603 rproc_2: rproc@2 {
604 compatible = "sandbox,test-processor";
605 internal-memory-mapped;
606 remoteproc-name = "remoteproc-test-dev2";
607 };
608
Simon Glass5620cf82018-10-01 12:22:40 -0600609 panel {
610 compatible = "simple-panel";
611 backlight = <&backlight 0 100>;
612 };
613
Ramon Fried26ed32e2018-07-02 02:57:59 +0300614 smem@0 {
615 compatible = "sandbox,smem";
616 };
617
Simon Glass76072ac2018-12-10 10:37:36 -0700618 sound {
619 compatible = "sandbox,sound";
620 cpu {
621 sound-dai = <&i2s 0>;
622 };
623
624 codec {
625 sound-dai = <&audio 0>;
626 };
627 };
628
Simon Glass25348a42014-10-13 23:42:11 -0600629 spi@0 {
630 #address-cells = <1>;
631 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600632 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600633 compatible = "sandbox,spi";
634 cs-gpios = <0>, <&gpio_a 0>;
635 spi.bin@0 {
636 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000637 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600638 spi-max-frequency = <40000000>;
639 sandbox,filename = "spi.bin";
640 };
641 };
642
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100643 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600644 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200645 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600646 };
647
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100648 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600649 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600650 reg = <0x20 5
651 0x28 6
652 0x30 7
653 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600654 };
655
Patrick Delaunayee010432019-03-07 09:57:13 +0100656 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900657 compatible = "simple-mfd", "syscon";
658 reg = <0x40 5
659 0x48 6
660 0x50 7
661 0x58 8>;
662 };
663
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800664 timer {
665 compatible = "sandbox,timer";
666 clock-frequency = <1000000>;
667 };
668
Miquel Raynal80938c12018-05-15 11:57:27 +0200669 tpm2 {
670 compatible = "sandbox,tpm2";
671 };
672
Simon Glass5b968632015-05-22 15:42:15 -0600673 uart0: serial {
674 compatible = "sandbox,serial";
675 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500676 };
677
Simon Glass31680482015-03-25 12:23:05 -0600678 usb_0: usb@0 {
679 compatible = "sandbox,usb";
680 status = "disabled";
681 hub {
682 compatible = "sandbox,usb-hub";
683 #address-cells = <1>;
684 #size-cells = <0>;
685 flash-stick {
686 reg = <0>;
687 compatible = "sandbox,usb-flash";
688 };
689 };
690 };
691
692 usb_1: usb@1 {
693 compatible = "sandbox,usb";
694 hub {
695 compatible = "usb-hub";
696 usb,device-class = <9>;
697 hub-emul {
698 compatible = "sandbox,usb-hub";
699 #address-cells = <1>;
700 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700701 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600702 reg = <0>;
703 compatible = "sandbox,usb-flash";
704 sandbox,filepath = "testflash.bin";
705 };
706
Simon Glass4700fe52015-11-08 23:48:01 -0700707 flash-stick@1 {
708 reg = <1>;
709 compatible = "sandbox,usb-flash";
710 sandbox,filepath = "testflash1.bin";
711 };
712
713 flash-stick@2 {
714 reg = <2>;
715 compatible = "sandbox,usb-flash";
716 sandbox,filepath = "testflash2.bin";
717 };
718
Simon Glassc0ccc722015-11-08 23:48:08 -0700719 keyb@3 {
720 reg = <3>;
721 compatible = "sandbox,usb-keyb";
722 };
723
Simon Glass31680482015-03-25 12:23:05 -0600724 };
725 };
726 };
727
728 usb_2: usb@2 {
729 compatible = "sandbox,usb";
730 status = "disabled";
731 };
732
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200733 spmi: spmi@0 {
734 compatible = "sandbox,spmi";
735 #address-cells = <0x1>;
736 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600737 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200738 pm8916@0 {
739 compatible = "qcom,spmi-pmic";
740 reg = <0x0 0x1>;
741 #address-cells = <0x1>;
742 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600743 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200744
745 spmi_gpios: gpios@c000 {
746 compatible = "qcom,pm8916-gpio";
747 reg = <0xc000 0x400>;
748 gpio-controller;
749 gpio-count = <4>;
750 #gpio-cells = <2>;
751 gpio-bank-name="spmi";
752 };
753 };
754 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700755
756 wdt0: wdt@0 {
757 compatible = "sandbox,wdt";
758 };
Rob Clarka471b672018-01-10 11:33:30 +0100759
Mario Six95922152018-08-09 14:51:19 +0200760 axi: axi@0 {
761 compatible = "sandbox,axi";
762 #address-cells = <0x1>;
763 #size-cells = <0x1>;
764 store@0 {
765 compatible = "sandbox,sandbox_store";
766 reg = <0x0 0x400>;
767 };
768 };
769
Rob Clarka471b672018-01-10 11:33:30 +0100770 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700771 #address-cells = <1>;
772 #size-cells = <1>;
Rob Clarka471b672018-01-10 11:33:30 +0100773 chosen-test {
774 compatible = "denx,u-boot-fdt-test";
775 reg = <9 1>;
776 };
777 };
Mario Six35616ef2018-03-12 14:53:33 +0100778
779 translation-test@8000 {
780 compatible = "simple-bus";
781 reg = <0x8000 0x4000>;
782
783 #address-cells = <0x2>;
784 #size-cells = <0x1>;
785
786 ranges = <0 0x0 0x8000 0x1000
787 1 0x100 0x9000 0x1000
788 2 0x200 0xA000 0x1000
789 3 0x300 0xB000 0x1000
790 >;
791
Fabien Dessenne22236e02019-05-31 15:11:30 +0200792 dma-ranges = <0 0x000 0x10000000 0x1000
793 1 0x100 0x20000000 0x1000
794 >;
795
Mario Six35616ef2018-03-12 14:53:33 +0100796 dev@0,0 {
797 compatible = "denx,u-boot-fdt-dummy";
798 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100799 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100800 };
801
802 dev@1,100 {
803 compatible = "denx,u-boot-fdt-dummy";
804 reg = <1 0x100 0x1000>;
805
806 };
807
808 dev@2,200 {
809 compatible = "denx,u-boot-fdt-dummy";
810 reg = <2 0x200 0x1000>;
811 };
812
813
814 noxlatebus@3,300 {
815 compatible = "simple-bus";
816 reg = <3 0x300 0x1000>;
817
818 #address-cells = <0x1>;
819 #size-cells = <0x0>;
820
821 dev@42 {
822 compatible = "denx,u-boot-fdt-dummy";
823 reg = <0x42>;
824 };
825 };
826 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200827
828 osd {
829 compatible = "sandbox,sandbox_osd";
830 };
Tom Rinib93eea72018-09-30 18:16:51 -0400831
Mario Sixab664ff2018-07-31 11:44:13 +0200832 board {
833 compatible = "sandbox,board_sandbox";
834 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200835
836 sandbox_tee {
837 compatible = "sandbox,tee";
838 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700839
840 sandbox_virtio1 {
841 compatible = "sandbox,virtio1";
842 };
843
844 sandbox_virtio2 {
845 compatible = "sandbox,virtio2";
846 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200847
848 pinctrl {
849 compatible = "sandbox,pinctrl";
850 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100851
852 hwspinlock@0 {
853 compatible = "sandbox,hwspinlock";
854 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100855
856 dma: dma {
857 compatible = "sandbox,dma";
858 #dma-cells = <1>;
859
860 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
861 dma-names = "m2m", "tx0", "rx0";
862 };
Alex Marginean0daa53a2019-06-03 19:12:28 +0300863
Alex Marginean0649be52019-07-12 10:13:53 +0300864 /*
865 * keep mdio-mux ahead of mdio so that the mux is removed first at the
866 * end of the test. If parent mdio is removed first, clean-up of the
867 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
868 * active at the end of the test. That it turn doesn't allow the mdio
869 * class to be destroyed, triggering an error.
870 */
871 mdio-mux-test {
872 compatible = "sandbox,mdio-mux";
873 #address-cells = <1>;
874 #size-cells = <0>;
875 mdio-parent-bus = <&mdio>;
876
877 mdio-ch-test@0 {
878 reg = <0>;
879 };
880 mdio-ch-test@1 {
881 reg = <1>;
882 };
883 };
884
885 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +0300886 compatible = "sandbox,mdio";
887 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700888};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200889
890#include "sandbox_pmic.dtsi"