Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 2 | /* |
Bin Meng | 8c5acf4 | 2014-12-12 21:05:22 +0800 | [diff] [blame] | 3 | * U-Boot - x86 Startup Code |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 4 | * |
Graeme Russ | 45fc1d8 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 5 | * (C) Copyright 2008-2011 |
| 6 | * Graeme Russ, <graeme.russ@gmail.com> |
| 7 | * |
| 8 | * (C) Copyright 2002 |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 9 | * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 10 | */ |
| 11 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 12 | #include <config.h> |
Graeme Russ | 5fb91cc | 2010-10-07 20:03:29 +1100 | [diff] [blame] | 13 | #include <asm/global_data.h> |
Simon Glass | 245561d | 2014-11-12 22:42:09 -0700 | [diff] [blame] | 14 | #include <asm/post.h> |
Graeme Russ | 391bb95 | 2011-12-31 10:24:36 +1100 | [diff] [blame] | 15 | #include <asm/processor.h> |
Graeme Russ | 93efcb2 | 2011-02-12 15:11:32 +1100 | [diff] [blame] | 16 | #include <asm/processor-flags.h> |
Graeme Russ | 3536896 | 2011-12-31 22:58:15 +1100 | [diff] [blame] | 17 | #include <generated/generic-asm-offsets.h> |
Bin Meng | 8c5acf4 | 2014-12-12 21:05:22 +0800 | [diff] [blame] | 18 | #include <generated/asm-offsets.h> |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 19 | |
Alexander Graf | 94a10f2 | 2018-06-12 07:48:37 +0200 | [diff] [blame] | 20 | .section .text.start |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 21 | .code32 |
| 22 | .globl _start |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 23 | .type _start, @function |
Graeme Russ | cbfce1d | 2011-04-13 19:43:28 +1000 | [diff] [blame] | 24 | .globl _x86boot_start |
| 25 | _x86boot_start: |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 26 | /* |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 27 | * This is the fail-safe 32-bit bootstrap entry point. |
| 28 | * |
| 29 | * This code is used when booting from another boot loader like |
| 30 | * coreboot or EFI. So we repeat some of the same init found in |
| 31 | * start16. |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 32 | */ |
| 33 | cli |
| 34 | cld |
| 35 | |
Graeme Russ | c379b5d | 2011-11-08 02:33:23 +0000 | [diff] [blame] | 36 | /* Turn off cache (this might require a 486-class CPU) */ |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 37 | movl %cr0, %eax |
Graeme Russ | 93efcb2 | 2011-02-12 15:11:32 +1100 | [diff] [blame] | 38 | orl $(X86_CR0_NW | X86_CR0_CD), %eax |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 39 | movl %eax, %cr0 |
| 40 | wbinvd |
| 41 | |
Gabe Black | ef89932 | 2012-11-03 11:41:28 +0000 | [diff] [blame] | 42 | /* Tell 32-bit code it is being entered from an in-RAM copy */ |
Simon Glass | 5d18dc9 | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 43 | movl $GD_FLG_WARM_BOOT, %ebx |
Simon Glass | f95ad8c | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 44 | |
| 45 | /* |
| 46 | * Zero the BIST (Built-In Self Test) value since we don't have it. |
| 47 | * It must be 0 or the previous loader would have reported an error. |
| 48 | */ |
| 49 | movl $0, %ebp |
| 50 | |
Gabe Black | ef89932 | 2012-11-03 11:41:28 +0000 | [diff] [blame] | 51 | jmp 1f |
Simon Glass | 5d18dc9 | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 52 | |
| 53 | /* Add a way for tools to discover the _start entry point */ |
| 54 | .align 4 |
| 55 | .long 0x12345678 |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 56 | _start: |
Gabe Black | ef89932 | 2012-11-03 11:41:28 +0000 | [diff] [blame] | 57 | /* |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 58 | * This is the 32-bit cold-reset entry point, coming from start16. |
Simon Glass | 5d18dc9 | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 59 | * Set %ebx to GD_FLG_COLD_BOOT to indicate this. |
Gabe Black | ef89932 | 2012-11-03 11:41:28 +0000 | [diff] [blame] | 60 | */ |
Simon Glass | 5d18dc9 | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 61 | movl $GD_FLG_COLD_BOOT, %ebx |
Simon Glass | f95ad8c | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 62 | |
Simon Glass | 1f4476c | 2014-11-06 13:20:10 -0700 | [diff] [blame] | 63 | /* Save BIST */ |
| 64 | movl %eax, %ebp |
Simon Glass | f95ad8c | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 65 | 1: |
| 66 | |
| 67 | /* Save table pointer */ |
| 68 | movl %ecx, %esi |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 69 | |
Andy Shevchenko | 2ae7da0 | 2017-02-05 16:52:00 +0300 | [diff] [blame] | 70 | #ifdef CONFIG_X86_LOAD_FROM_32_BIT |
Simon Glass | b4ded74 | 2016-03-16 07:44:40 -0600 | [diff] [blame] | 71 | lgdt gdt_ptr2 |
| 72 | #endif |
| 73 | |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 74 | /* Load the segement registers to match the GDT loaded in start16.S */ |
Graeme Russ | 391bb95 | 2011-12-31 10:24:36 +1100 | [diff] [blame] | 75 | movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax |
Graeme Russ | 3e6ec38 | 2010-10-07 20:03:21 +1100 | [diff] [blame] | 76 | movw %ax, %fs |
| 77 | movw %ax, %ds |
| 78 | movw %ax, %gs |
| 79 | movw %ax, %es |
| 80 | movw %ax, %ss |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 81 | |
Mike Williams | bf895ad | 2011-07-22 04:01:30 +0000 | [diff] [blame] | 82 | /* Clear the interrupt vectors */ |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 83 | lidt blank_idt_ptr |
| 84 | |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 85 | /* |
| 86 | * Critical early platform init - generally not used, we prefer init |
| 87 | * to happen later when we have a console, in case something goes |
| 88 | * wrong. |
| 89 | */ |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 90 | jmp early_board_init |
Graeme Russ | 157b0e9 | 2010-10-07 20:03:27 +1100 | [diff] [blame] | 91 | .globl early_board_init_ret |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 92 | early_board_init_ret: |
Simon Glass | 245561d | 2014-11-12 22:42:09 -0700 | [diff] [blame] | 93 | post_code(POST_START) |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 94 | |
Graeme Russ | bc76193 | 2011-02-12 15:11:52 +1100 | [diff] [blame] | 95 | /* Initialise Cache-As-RAM */ |
| 96 | jmp car_init |
| 97 | .globl car_init_ret |
| 98 | car_init_ret: |
Bin Meng | 005f0af | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 99 | #ifndef CONFIG_HAVE_FSP |
Graeme Russ | bc76193 | 2011-02-12 15:11:52 +1100 | [diff] [blame] | 100 | /* |
| 101 | * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, |
| 102 | * or fully initialised SDRAM - we really don't care which) |
| 103 | * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 104 | * and early malloc() area. The MRC requires some space at the top. |
Simon Glass | a4fd0db | 2014-11-06 13:20:04 -0700 | [diff] [blame] | 105 | * |
| 106 | * Stack grows down from top of CAR. We have: |
| 107 | * |
| 108 | * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 109 | * MRC area |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 110 | * global_data with x86 global descriptor table |
Simon Glass | a4fd0db | 2014-11-06 13:20:04 -0700 | [diff] [blame] | 111 | * early malloc area |
| 112 | * stack |
| 113 | * bottom-> CONFIG_SYS_CAR_ADDR |
Graeme Russ | bc76193 | 2011-02-12 15:11:52 +1100 | [diff] [blame] | 114 | */ |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 115 | movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp |
| 116 | #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE |
| 117 | subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp |
| 118 | #endif |
Bin Meng | 005f0af | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 119 | #else |
| 120 | /* |
Bin Meng | 73574dc | 2015-08-20 06:40:20 -0700 | [diff] [blame] | 121 | * U-Boot enters here twice. For the first time it comes from |
| 122 | * car_init_done() with esp points to a temporary stack and esi |
| 123 | * set to zero. For the second time it comes from fsp_init_done() |
| 124 | * with esi holding the HOB list address returned by the FSP. |
Bin Meng | 005f0af | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 125 | */ |
| 126 | #endif |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 127 | /* Set up global data */ |
| 128 | mov %esp, %eax |
Albert ARIBAUD | 6cb4c46 | 2015-11-25 17:56:32 +0100 | [diff] [blame] | 129 | call board_init_f_alloc_reserve |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 130 | mov %eax, %esp |
Albert ARIBAUD | 6cb4c46 | 2015-11-25 17:56:32 +0100 | [diff] [blame] | 131 | call board_init_f_init_reserve |
Graeme Russ | 007818a | 2012-11-27 15:38:36 +0000 | [diff] [blame] | 132 | |
Simon Glass | 4773012 | 2015-10-18 19:51:26 -0600 | [diff] [blame] | 133 | #ifdef CONFIG_DEBUG_UART |
| 134 | call debug_uart_init |
| 135 | #endif |
Simon Glass | 9bbb37f | 2015-08-02 18:07:21 -0600 | [diff] [blame] | 136 | |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 137 | /* Get address of global_data */ |
| 138 | mov %fs:0, %edx |
Bin Meng | 005f0af | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 139 | #ifdef CONFIG_HAVE_FSP |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 140 | /* Store the HOB list if we have one */ |
Bin Meng | d560c5c | 2015-06-07 11:33:14 +0800 | [diff] [blame] | 141 | test %esi, %esi |
| 142 | jz skip_hob |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 143 | movl %esi, GD_HOB_LIST(%edx) |
Bin Meng | 005f0af | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 144 | |
Bin Meng | 12440cd | 2015-08-20 06:40:19 -0700 | [diff] [blame] | 145 | /* |
| 146 | * After fsp_init() returns, the stack has already been switched to a |
| 147 | * place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR. |
| 148 | * Enlarge the size of malloc() pool before relocation since we have |
| 149 | * plenty of memory now. |
| 150 | */ |
| 151 | subl $CONFIG_FSP_SYS_MALLOC_F_LEN, %esp |
| 152 | movl %esp, GD_MALLOC_BASE(%edx) |
Bin Meng | d560c5c | 2015-06-07 11:33:14 +0800 | [diff] [blame] | 153 | skip_hob: |
Simon Glass | f95ad8c | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 154 | #else |
| 155 | /* Store table pointer */ |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 156 | movl %esi, GD_TABLE(%edx) |
Bin Meng | d560c5c | 2015-06-07 11:33:14 +0800 | [diff] [blame] | 157 | #endif |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 158 | /* Store BIST */ |
| 159 | movl %ebp, GD_BIST(%edx) |
Graeme Russ | 3536896 | 2011-12-31 22:58:15 +1100 | [diff] [blame] | 160 | |
Graeme Russ | 3818393 | 2011-02-12 15:11:54 +1100 | [diff] [blame] | 161 | /* Set parameter to board_init_f() to boot flags */ |
Simon Glass | 245561d | 2014-11-12 22:42:09 -0700 | [diff] [blame] | 162 | post_code(POST_START_DONE) |
Graeme Russ | 45fc1d8 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 163 | xorl %eax, %eax |
Graeme Russ | 5fb91cc | 2010-10-07 20:03:29 +1100 | [diff] [blame] | 164 | |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 165 | /* Enter, U-Boot! */ |
Graeme Russ | 45fc1d8 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 166 | call board_init_f |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 167 | |
| 168 | /* indicate (lack of) progress */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 169 | movw $0x85, %ax |
Graeme Russ | 9c44afc | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 170 | jmp die |
| 171 | |
Graeme Russ | d7755b4 | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 172 | .globl board_init_f_r_trampoline |
| 173 | .type board_init_f_r_trampoline, @function |
| 174 | board_init_f_r_trampoline: |
Graeme Russ | 9c44afc | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 175 | /* |
| 176 | * SDRAM has been initialised, U-Boot code has been copied into |
| 177 | * RAM, BSS has been cleared and relocation adjustments have been |
| 178 | * made. It is now time to jump into the in-RAM copy of U-Boot |
| 179 | * |
Graeme Russ | d7755b4 | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 180 | * %eax = Address of top of new stack |
Graeme Russ | 9c44afc | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 181 | */ |
| 182 | |
Graeme Russ | 007818a | 2012-11-27 15:38:36 +0000 | [diff] [blame] | 183 | /* Stack grows down from top of SDRAM */ |
Graeme Russ | 9c44afc | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 184 | movl %eax, %esp |
| 185 | |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 186 | /* See if we need to disable CAR */ |
Simon Glass | 78da72c | 2015-01-01 16:18:13 -0700 | [diff] [blame] | 187 | .weak car_uninit |
| 188 | movl $car_uninit, %eax |
| 189 | cmpl $0, %eax |
| 190 | jz 1f |
| 191 | |
| 192 | call car_uninit |
| 193 | 1: |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 194 | /* Re-enter U-Boot by calling board_init_f_r() */ |
Graeme Russ | d7755b4 | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 195 | call board_init_f_r |
Graeme Russ | 9c44afc | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 196 | |
Graeme Russ | c379b5d | 2011-11-08 02:33:23 +0000 | [diff] [blame] | 197 | die: |
| 198 | hlt |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 199 | jmp die |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 200 | hlt |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 201 | |
| 202 | blank_idt_ptr: |
| 203 | .word 0 /* limit */ |
| 204 | .long 0 /* base */ |
Graeme Russ | 786c395 | 2011-11-08 02:33:19 +0000 | [diff] [blame] | 205 | |
| 206 | .p2align 2 /* force 4-byte alignment */ |
| 207 | |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 208 | /* Add a multiboot header so U-Boot can be loaded by GRUB2 */ |
Graeme Russ | 786c395 | 2011-11-08 02:33:19 +0000 | [diff] [blame] | 209 | multiboot_header: |
| 210 | /* magic */ |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 211 | .long 0x1badb002 |
Graeme Russ | 786c395 | 2011-11-08 02:33:19 +0000 | [diff] [blame] | 212 | /* flags */ |
| 213 | .long (1 << 16) |
| 214 | /* checksum */ |
| 215 | .long -0x1BADB002 - (1 << 16) |
| 216 | /* header addr */ |
| 217 | .long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE |
| 218 | /* load addr */ |
| 219 | .long CONFIG_SYS_TEXT_BASE |
| 220 | /* load end addr */ |
| 221 | .long 0 |
| 222 | /* bss end addr */ |
| 223 | .long 0 |
| 224 | /* entry addr */ |
| 225 | .long CONFIG_SYS_TEXT_BASE |
Simon Glass | b4ded74 | 2016-03-16 07:44:40 -0600 | [diff] [blame] | 226 | |
Andy Shevchenko | 2ae7da0 | 2017-02-05 16:52:00 +0300 | [diff] [blame] | 227 | #ifdef CONFIG_X86_LOAD_FROM_32_BIT |
Simon Glass | b4ded74 | 2016-03-16 07:44:40 -0600 | [diff] [blame] | 228 | /* |
| 229 | * The following Global Descriptor Table is just enough to get us into |
| 230 | * 'Flat Protected Mode' - It will be discarded as soon as the final |
| 231 | * GDT is setup in a safe location in RAM |
| 232 | */ |
| 233 | gdt_ptr2: |
| 234 | .word 0x1f /* limit (31 bytes = 4 GDT entries - 1) */ |
| 235 | .long gdt_rom2 /* base */ |
| 236 | |
| 237 | /* Some CPUs are picky about GDT alignment... */ |
| 238 | .align 16 |
| 239 | .globl gdt_rom2 |
| 240 | gdt_rom2: |
| 241 | /* |
| 242 | * The GDT table ... |
| 243 | * |
| 244 | * Selector Type |
| 245 | * 0x00 NULL |
| 246 | * 0x08 Unused |
| 247 | * 0x10 32bit code |
| 248 | * 0x18 32bit data/stack |
| 249 | */ |
| 250 | /* The NULL Desciptor - Mandatory */ |
| 251 | .word 0x0000 /* limit_low */ |
| 252 | .word 0x0000 /* base_low */ |
| 253 | .byte 0x00 /* base_middle */ |
| 254 | .byte 0x00 /* access */ |
| 255 | .byte 0x00 /* flags + limit_high */ |
| 256 | .byte 0x00 /* base_high */ |
| 257 | |
| 258 | /* Unused Desciptor - (matches Linux) */ |
| 259 | .word 0x0000 /* limit_low */ |
| 260 | .word 0x0000 /* base_low */ |
| 261 | .byte 0x00 /* base_middle */ |
| 262 | .byte 0x00 /* access */ |
| 263 | .byte 0x00 /* flags + limit_high */ |
| 264 | .byte 0x00 /* base_high */ |
| 265 | |
| 266 | /* |
| 267 | * The Code Segment Descriptor: |
| 268 | * - Base = 0x00000000 |
| 269 | * - Size = 4GB |
| 270 | * - Access = Present, Ring 0, Exec (Code), Readable |
| 271 | * - Flags = 4kB Granularity, 32-bit |
| 272 | */ |
| 273 | .word 0xffff /* limit_low */ |
| 274 | .word 0x0000 /* base_low */ |
| 275 | .byte 0x00 /* base_middle */ |
| 276 | .byte 0x9b /* access */ |
| 277 | .byte 0xcf /* flags + limit_high */ |
| 278 | .byte 0x00 /* base_high */ |
| 279 | |
| 280 | /* |
| 281 | * The Data Segment Descriptor: |
| 282 | * - Base = 0x00000000 |
| 283 | * - Size = 4GB |
| 284 | * - Access = Present, Ring 0, Non-Exec (Data), Writable |
| 285 | * - Flags = 4kB Granularity, 32-bit |
| 286 | */ |
| 287 | .word 0xffff /* limit_low */ |
| 288 | .word 0x0000 /* base_low */ |
| 289 | .byte 0x00 /* base_middle */ |
| 290 | .byte 0x93 /* access */ |
| 291 | .byte 0xcf /* flags + limit_high */ |
| 292 | .byte 0x00 /* base_high */ |
| 293 | #endif |