stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001-2003 |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <asm/processor.h> |
Matthias Fuchs | 5dde4e2 | 2009-02-20 10:19:19 +0100 | [diff] [blame] | 26 | #include <asm/io.h> |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 27 | #include <command.h> |
| 28 | #include <malloc.h> |
| 29 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 30 | DECLARE_GLOBAL_DATA_PTR; |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 31 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 32 | int board_early_init_f (void) |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 33 | { |
| 34 | /* |
| 35 | * IRQ 0-15 405GP internally generated; active high; level sensitive |
| 36 | * IRQ 16 405GP internally generated; active low; level sensitive |
| 37 | * IRQ 17-24 RESERVED |
| 38 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
| 39 | * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive |
| 40 | * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive |
| 41 | * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive |
| 42 | * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive |
| 43 | * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive |
| 44 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
| 45 | */ |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 46 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
| 47 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ |
| 48 | mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ |
| 49 | mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ |
| 50 | mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ |
| 51 | mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
| 52 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 53 | |
| 54 | /* |
| 55 | * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us |
| 56 | */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 57 | mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 58 | |
stroese | 4d34bbf | 2004-12-16 18:35:58 +0000 | [diff] [blame] | 59 | /* |
| 60 | * Reset CPLD via GPIO13 (CS4) pin |
| 61 | */ |
Matthias Fuchs | 5dde4e2 | 2009-02-20 10:19:19 +0100 | [diff] [blame] | 62 | out_be32((void *)GPIO0_OR, |
| 63 | in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13)); |
stroese | 4d34bbf | 2004-12-16 18:35:58 +0000 | [diff] [blame] | 64 | udelay(1000); /* wait 1ms */ |
Matthias Fuchs | 5dde4e2 | 2009-02-20 10:19:19 +0100 | [diff] [blame] | 65 | out_be32((void *)GPIO0_OR, |
| 66 | in_be32((void *)GPIO0_OR) | (0x80000000 >> 13)); |
stroese | 4d34bbf | 2004-12-16 18:35:58 +0000 | [diff] [blame] | 67 | udelay(1000); /* wait 1ms */ |
| 68 | |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 69 | return 0; |
| 70 | } |
| 71 | |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 72 | int misc_init_r (void) |
| 73 | { |
stroese | 4d34bbf | 2004-12-16 18:35:58 +0000 | [diff] [blame] | 74 | /* adjust flash start and offset */ |
| 75 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
| 76 | gd->bd->bi_flashoffset = 0; |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 77 | |
| 78 | return (0); |
| 79 | } |
| 80 | |
| 81 | |
| 82 | /* |
| 83 | * Check Board Identity: |
| 84 | */ |
| 85 | |
| 86 | int checkboard (void) |
| 87 | { |
Wolfgang Denk | 7fb5266 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 88 | char str[64]; |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 89 | int i = getenv_r ("serial#", str, sizeof(str)); |
| 90 | unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe, |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 91 | 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf}; |
Matthias Fuchs | ddfaf73 | 2009-04-29 09:51:01 +0200 | [diff] [blame] | 92 | unsigned char id1, id2, rev; |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 93 | |
| 94 | puts ("Board: "); |
| 95 | |
Matthias Fuchs | ddfaf73 | 2009-04-29 09:51:01 +0200 | [diff] [blame] | 96 | if (i == -1) |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 97 | puts ("### No HW ID - assuming DP405"); |
Matthias Fuchs | ddfaf73 | 2009-04-29 09:51:01 +0200 | [diff] [blame] | 98 | else |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 99 | puts(str); |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 100 | |
Matthias Fuchs | 5dde4e2 | 2009-02-20 10:19:19 +0100 | [diff] [blame] | 101 | id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f]; |
| 102 | id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f]; |
Matthias Fuchs | ddfaf73 | 2009-04-29 09:51:01 +0200 | [diff] [blame] | 103 | |
Wolfgang Denk | 1d695be | 2009-07-07 22:35:02 +0200 | [diff] [blame] | 104 | rev = in_8((void *)0xf0001000); |
| 105 | if (rev & 0x10) /* old DP405 compatibility */ |
| 106 | rev = in_8((void *)0xf0000800); |
Matthias Fuchs | ddfaf73 | 2009-04-29 09:51:01 +0200 | [diff] [blame] | 107 | |
Wolfgang Denk | 1d695be | 2009-07-07 22:35:02 +0200 | [diff] [blame] | 108 | switch (rev & 0xc0) { |
| 109 | case 0x00: |
| 110 | puts(" (HW=DP405"); |
| 111 | break; |
| 112 | case 0x80: |
| 113 | puts(" (HW=DP405/CO"); |
| 114 | break; |
| 115 | case 0xc0: |
| 116 | puts(" (HW=DN405"); |
| 117 | break; |
| 118 | } |
| 119 | printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f); |
Matthias Fuchs | ddfaf73 | 2009-04-29 09:51:01 +0200 | [diff] [blame] | 120 | |
Wolfgang Denk | 1d695be | 2009-07-07 22:35:02 +0200 | [diff] [blame] | 121 | if ((rev & 0xc0) == 0xc0) { |
| 122 | printf(", C5V=%s", |
| 123 | in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on"); |
| 124 | } |
| 125 | puts(")\n"); |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 126 | |
| 127 | return 0; |
| 128 | } |